Bio-Medical Materials and Engineering 24 (2014) 1009–1017 DOI 10.3233/BME-130898 IOS Press
1009
A 1-Channel 3-Band Wide Dynamic Range Compression Chip for Vibration Transducer of Implantable Hearing Aids DongWook Kim a, KiWoong Seongb, MyoungNam Kimc, JinHo Chod, and JyungHyun Lee b,* a
Department of Electrical Engineering Graduate School, Kyungpook National University, Deagu, South Korea b Department of Biomedical Engineering, Kyungpook Nation University Hospital, [email protected], Daegu, South Korea c Graduate School of Medicine, Kyungpook National University, Daegu, South Korea d School of Electronics Engineering, College of IT Engineering, Kyungpook National University, Deagu, South Korea
Abstract. In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level. Keywords: wide dynamic range compression, implantable hearing aids, vibration transducer, fitting formula, application specific integrated circuit
1. Introduction The various types of hearing aids are being rapidly developed due to the improvements in digital signal processing and integrated circuit design. In particular, the implantable hearing aids (IHA) are being actively studied for sensorineural hearing-impaired people [1-4]. A Korea research team at Kyungpook National University has developed an IHA system which consists of an implantable microphone, an audio processor and a 3-coil vibration transducer [5-8]. The IHA detects sound by using a microphone and converts it into an electrical signal for audio processing. The vibration transducer has frequency characteristics similar to the middle and a frequency resonance at 1.5 ~ 2 kHz. The audio processor amplifies the electrical input signal to a calculated frequency-gain using the WDRC algorithm. The output stage of the audio processor needs to be designed to take into account the vibration characteristics of the vibration transducer. *Corresponding author. E-mail: JyungHyun [email protected] 0959-2989/14/$27.50 © 2014 – IOS Press and the authors. All rights reserved
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However, the previous audio processor cannot be applied to the IHA system, because it does not take into account the frequency resonance of vibration transducer. In this paper, a digital audio processing chip which is a 1-channel 3-band WDRC is designed and implemented, using computer simulation and 0.18 um application specific integrated circuit (ASIC) process. The designed chip has a 50 MHz system clock and uses a single 1.8V and 3.3 V voltage supply. The bandwidth of chip ranges from 100 Hz to 16 kHz. In addition, the output stage of designed chip drives a 16 bit parallel output at a sample rate of 32 kHz. The designed chip separates the input signal band by using a filter bank and determines the input signal level is determined with a level detector. The output gains in each band are controlled by FIG-6 fitting rule to reflect hearing loss level. 2. Design of 1-channel 3-band wide dynamic range compression The 1-channel 3-band WDRC chip for the IHA system was designed to take into account the vibration transducer characteristics with frequency resonance. 2.1. Characteristics of the vibration transducer Figure 1-(a) shows the structure of the 3-coil vibration transducer used in the IHA system. The 3piece coil consists of a central coil wound in one direction and two end coils wound in the opposite direction. Two magnets attached to the opposite direction were positioned inside the 3-piece coil. The vibrational force was generated by the interaction between the magnetic fields of the two magnets in the center and currents flowed through the central and end coils. Figure 1-(b) shows displacement of the vibration transducer. The frequency characteristic of the vibration transducer had a flat vibration at 100~1000 Hz, a frequency resonance at 1.5 ~ 2 kHz, and exhibits resonance attenuation at 2 ~10 kHz [9-13]. These results mean that designed chip has 3 frequency bands to consider the transducer characteristic.
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Fig. 1. Structure of the vibration transducer and self characteristic.
2.2. 1-channel 3-band wide dynamic range compression The basic role of the WDRC algorithm is to automatically reduce the dynamic range of a hearing impaired person and adjust the gain and maximum output level of each frequency channel based on
D.W. Kim et al. / A 1-channel 3-band wide dynamic range compression chip for vibration transducer
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the intensity levels of the input signals. These improve sound intelligibility and quality and make low intensity sounds more audible and prevent high intensity sounds from becoming uncomfortably loud [14-16]. In this study, a designed 1-channel 3-band WDRC algorithm is designed by using Matlab-simulink. The designed WDRC was composed of 3 parts, namely, a FIR filter bank, a level detector, and a compression as showed in Figure 2. The filter bank was used to divide input signals into a multiplicity of frequency bands using a 127 order FIR filter at a sample rate of 32 kHz. The direct-form structure was used to design a FIR filter and its transfer function is Eq. (1) and shown in Figure 3. The lowest frequencies were outputted by a low-pass filter, the highest frequencies by a high-pass filter, and remaining frequencies by a band-pass filter. The filter banks were designed for application with the vibration transducer, which has filter cutoff frequencies of 800 Hz, 1000 ~ 2500 Hz, and 3000Hz. Figure 4. shows a frequency response of designed FIR filter bank.
b0 + b1 z −1 + b2 z −2 + !+ bM −1 z M −1 H ( z) = z M −1
Fig. 2. The wide dynamic range compression block using Matlab-Simulink.
Fig. 3. The structure of direct-form Finite Impulse Response filter.
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The level detector estimates the signal level by using peak envelope detection to follow the maximum incoming signal, because compression gain depends on input signal level in each band. The level detector should have a quick response to prevent over amplification of increasing signal as uncomfortable loudness level and should have smooth out to perceive loudness sound of decreasing signal. The level detector algorithm is shown in Eq. (2), the output y[n] depends on alpha, beta, and input x[n]. Alpha is referred to as attack time and is fixed at 6 ms and beta is referred to as release time and it is fixed at 97 ms. Output y[n] had some ripples that were reduced by increasing the attack and release times or smoothing filter. In this paper, 64 order FIR filters were used as smoothing filters to reduce the output ripples because increasing the attack and release times lead to a group delay. The compression part adjusts the compression gain and the high level output limit using the FIG6 non-linear fitting rule. The FIG6 can be utilized to calculate gain and frequency response for low-level (40dB SPL), moderate-level (65 dB SPL), and high-level sound (95 dB SPL) [17-18]. To devise a computer-based approach to compression, FIG6 algorithm was programmed by using the embedded Simulink block in Matlab. y [n ] = alpha
× y [n − 1 ] + (1 − alpha ) × x [n ]
for x [n ] ≥ y [n − 1 ],
y [n ] = beta × y [n − 1 ] for
otherwise
(2)
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To verify the designed WDRC algorithm, input source frequency and compression hearing loss were set in different conditions. The filter banks were inputted at 500, 2000, and 4000 Hz and hearing losses for compression gains were selected at 10, 40, and 60 dB HL. Figure 3 shows the simulation results of the designed WDRC.
Fig. 5. Matlab simulation output of the designed WDRC.
3. Implementation of the application specific integrated circuit The 0.18 um ASIC process needs 2-stage of computer simulation to optimize the algorithm. The first stage involved the verification of the verilog-HDL code for semi-custom design and the second for placing and routing digital logic cells. 3.1. Verilog-HDL simulation for semi-custom process For the 0.18 um ASIC process, the designed WDRC algorithm has to be converted into verilogHDL code. To perform the verilog simulation, Spartan6 XC6SLX45T (Xilinx Inc., USA) which runs a 50 MHz system clock, with a 3.3 V operating voltage was used, and programmed verilog code by Xilinx ISE software. Simulations were carried out in the same condition when utilizing input signal source and compression hearing loss at the Matlab simulink. The simulation data in Figure 4 shows the performance of the compression algorithm for verilog-HDL code. 3.2. Implementation of ASIC For the implementation of ASIC, Design Compiler and Astro (Synopsys Inc., USA) were used. The Design Compiler provided logic synthesis of verilog-HDL code and was used to optimize design so as to provide the smallest and fastest logical representation. After synthesis, a logical net-list file was generated for Astro and the design was ready for placing and routing. Astro provided the automatic placing and routing of the logic cells. Moreover, Astro confirmed the design rule check and layout versus schematic check. Figure 5 shows the placing and routing results, die micrograph, and implemented digital audio processing chip. This final chip had a 216,159 total cell area and a data slack time of 0.03ns.
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Fig. 6. Verilog-HDL simulation output of the designed WDRC algorithm.
Fig. 7. Designed digital audio processing chip.
4. Methods and results 4.1. Frequency response of designed digital chip To measure designed chip performance, PXI-1042 (National Instruments, USA), a computer-based measurement system was used. The designed chip based on the digital algorithm did not have ADC and DAC and thus, we fabricated a test board with external ADC and DAC circuits. The external ADC used a 16-bit parallel output ADS1605 with high speed, high precision and a delta-sigma analog-todigital converter. The ADS1605 operated from a 5V analog supply and a 3V digital supply. And the digital I/O operated from 3V to 5V which was as same as input voltage level of the designed chip. Furthermore, 2nd order delta-sigma ADC with analog ASIC is being designed, so ADS1605 can utilize the designed digital chip properly. The DAC used a 16-bit parallel input DAC8822 (Texas Instruments) which was operated in low power from single 2.7V to 5V with low noise and high speed. Also, the 16 bit parallel input interface is appropriate for the designed digital chip. When a signal source was inputted into the ADC, a 16-bit digitized signal was transmitted to the designed chip and then chip performed the WDRC algorithm. Final output was measured at the DAC output port. Experiments were focusing on the frequency splitting ability of the filter bank and on the peak detecting by the level detector. The input frequency range was from 100 to 6000 Hz at the peak amplitude of 100 mV in fre-
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quency sweep test. Figure 5 shows the fast fourier transform (FFT) responses of frequency splitting at 400, 2000, and 4000 Hz, which were selected to compare the above simulation results. The measured output showed that the designed chip did not exhibit frequency distortion when the level detector performed well.
Fig. 8. Experimental results of designed digital audio processing chip.
4.2. Results of temporal bone experimentation To verify the performance of designed chip, temporal bone experiment was fabricated by using designed chip and vibration transducer. One fresh temporal bone extracted from a 62 year old male Caucasoid was used for the experiment. This experiment was based on ASTM regulation (F2504)[19]. The measurement system set up consists of DAQ system (SYsidII, www.sysidlabs.com), LDV (HLV-1000, Polytek GmbH) and probe microphone system (ER7-C, Etymotic). Simultaneously, DAQ system can generate sound source and pick up output signals. The signal source was amplified with an audio amplifier (D-75, Crown Audio inc.). First, we measured frequency response of temporal bone at 94 dB SPL and vibration characteristic of vibration transducer which is attached round window and driven 1mA rms current [20]. Figure 9. (a) shows that the frequency response of temporal bone is similar with normal stapes velocity regulated by ASTM F-2504 and vibration transducer is well attached to the round window. The discrepancies between the loaded and unloaded states were observed after attaching the transducer to round window because loading effect of transducer change vibration force and frequency resonance. But there was no significant variation in the frequency resonance. Second, the performance of designed digital chip was measured with vibration transducer. The output stage of the designed chip was connected to the input of vibration transducer. The hearing loss level of low frequency, middle frequency, and high frequency were programmed to 40 dB HL, 50 dB HL, and 60 dB HL respectively. The 0.16 Vpeak and 1.6 Vpeak sinusoidal inputs were applied to the input stage of designed chip. The 0.6 Vpeak signal means the output level of the implantable microphone which had 30 dB sensitivity approximately to 4 mV at 74 dB SPL and pre-amplifier with 40 times amplification in IHA system. And the 1.6 Vpeak signal means the input signal of the implantable microphone was 94 dB SPL. Figure 9. (b) shows the driven results of vibration transducer which is attached to round win-
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dow with designed chip. With the frequency range below 4 kHz, the vibration characteristics were similar to vibration transducer. When the input source applied 1.6 Vpeak, the frequency resonance result of designed chip was lower than self-characteristic of vibration transducer which is driven 1 mA rms. The reason of this difference is output compression limit which prevent the uncomfortable loudness level of designed chip, but there was no significant variation in the frequency resonance. As shown in Figure 9. (b), the experiment results indicate that the designed chip can reflect the frequency resonance of vibration transducer and able to apply the signal processor of IHA system. 10
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Fig. 9. Output results of cadaver experiment; (a) velocity of temporal bone and vibration transducer, (b) velocity of vibration transducer with designed digital chip
5. Conclusion The digital audio processing chip for implantable hearing aids system should be designed by considering the vibration characteristics of the vibration transducer. In this study, a 1-channel 3-band wide dynamic range compression algorithm is designed and implemented to 0.18 um process ASIC chip. The designed chip was operated at a single 1.8V supply for core power and a 3.3V for input and output interface. The chip composed of a FIR filter bank, a level detector, and a compression part, had 16 bit parallel input and output interface at 3.3V and its bandwidth was 16 kHz. From the experimental results, we confirmed performance of designed chip that successfully worked band splitting and signal level detecting and the designed chip can reflect the frequency resonance of vibration transducer in temporal bone experiment. Furthermore, gain in each band is controlled by an adjustable hearing loss variable. Therefore, it is expected that the designed chip can be applied for implantable hearing aids. In the future work, the ADC and DAC circuits will be implemented for the designed chip. 6. Acknowledgment This study was supported by a grant of the Korea Healthcare Technology R&D Project, Ministry of Health & Welfare (A092106). And this work was supported by the National Research Foundation of
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Korea (NRF) grant funded by the Korea government (MEST) (No.2012R1A1A2006475). This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2013R1A2A1A09015677). References [1]
[2] [3] [4] [5] [6]
[7]
[8]
[9]
[10] [11] [12]
[13]
[14] [15] [16] [17] [18] [19] [20]
O. Sterkers, D. Bouccara, S. Labassi, J. P. Bebear, C. Dubreuil, B. Frachet, B. Fraysse, J. P. Lavieille, J. Mabnan, C, Martin, E. Truy, A. Uziel, and Vaneecloo, A middle ear implant, the Symphonix Vibrant Soundbridge: Retrospective study of the first 125 patients implanted in France, Otology and Neurotology, vol. 24, pp. 427-436, 2003. D. D. Backous and W. Duke, Implantable middle ear hearing devices: Current state of technology and market challenges, Current Opinion in Otolaryngology & Head and Neck Sugery, vol. 14, pp. 314-318, 2006. D. S. Haynes, J. A. Uoung, G. B Wanna, and M. E. Glasscock, Middle ear implantable hearing device: An overview, Trends in Amplification, vol. 13, no. 3, pp. 206-214, 2009. A. Amold, C. Stieger, C. Candreia, F. Pfiffner, and M. Kopis, Factors improving the vibration transfer of the floating mass transducer at the round window, Otology and Neurotology, vol. 31, No. 1, pp. 122-128, Jan., 2010. B. S. Song, M. K. Kim, Y. H. Yoon, S. H. Lee, and J. H. Cho, Design of differential electromagnetic transducer for use in IME system, IEICE T TRANS. INF. & SYST., vol. E87-D, no. 5, pp. 1231-1237, 2004. Ki-Woong Seong, Eui-Sung Jung, Hyung-Gyu Lim, Jang-Woo Lee, Min-Woo Kim, Sang-Hyo Woo, Jyung-Hyun Lee, Il-Yong Park, and Jin-Ho Cho, Vibration Analysis of Human Middle Ear with Differential Floating Mass Transducer Using electrical Model, IEICE TRANS. INF. & SYST., vol. E92-D, no. 10, pp. 2156-2158, 2009. E. S. Jung, K. W. Seong, H. G. Lim, J. W. Lee, D. W. Kim, J. H. Lee, M. N. Kim, and J. H Cho, Study of frequency response of implantable microphone and vibrating transducer for the gain compensation of implantable middle ear hearing aid, Journal of Korean Sensor Society, vol. 19, no. 3, pp. 361-368, 2010. Il-Yong Park, Yoshitaka Shimizu, Kevin N. C’Connor, Sunil Puria, Jin-Ho Cho, Comparisons of electromagnetic and piezoelectric floating-mass transducers in human cadaveric temporal bones, Hearing Research, vol. 272, pp. 187-192. 2011. Min-Kyu Kim, Il-Yong Park, Byung-Seop Song, Jin-Ho Cho, Fabrication and optimal design of differential electromagnetic transducer for implantable middle ear hearing device, Biosensors and Bioelectronics, vol. 21, no. 11, pp. 2170-2175, 2006. Min-Kyu Kim, Yong-Ho Yoon, Il-Yong Park, Jin-Ho Cho, Design of differential electromagnetic transducer for implantable middle ear hearing device using finite element method, Sensors and Actuators vol. 130, pp. 234-240, 2006. H. G. Lim, “Design of Electromagnetic Vibrator for Round Window Driving Implantable hearing Aids, Doctoral Dissertation, Kyungpook National Univ., 2010. Ki-Woong Seong, Min-Woo Kim, Jyung-Hyun Lee, Myung-Nam Kim, and Jin-Ho Cho, Design of A New Vibration Transducer for Implantable Middle Ear Hearing Devices, IEEJ Transactions On Electrical And Electronic Engineering, vol. 5, pp. 608-610, 2010. Dong Ho Shin, Hyung Gyu Lim, Eui Sung Jung, Ki Woong Seong, Jyung Hyun Lee, and Jin Ho Cho, A Physical Cochlear Model for Transducer Performance Evaluation of Implantable Hearing Aid with Round Window Driver, vol. 22, no. 2, pp. 150-155, 2013. Harvey Dillon, Hearing Aids, Boomerang Press, Sydney, 2011. J. M. Kates, Digital Hearing Aids, Plural Publishing, San Diego, 2008. J. M. Kates, Principles of Digital Dynamic-Range Compression, Trends in Amplification, vol. 9, no. 2, pp. 45-76, 2005. Toni C. Gitles, and Patty T. Niquette, FIG6 in Ten, The hearing Review, vol. 2, no. 10, pp. 28-30, 1995. Mead C. Killion, Loudness-data basis for “FIG6” hearing-aid fitting targets, Journal of the Acoustical Society of America, vol. 98, issue 5, pp. 2927-2927, 1995. Http://www.astm.org/standards/F2504.htm, American society for testing and materials, U.S.A. T.G. Dietz, G.R. Ball, B. H. Katz, Partially implantable vibrating ossicular prosthesis, International Conference on Solid State Sensors and Actuator, Chicago, U.S.A., 1997.
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1009
A 1-Channel 3-Band Wide Dynamic Range Compression Chip for Vibration Transducer of Implantable Hearing Aids DongWook Kim a, KiWoong Seongb, MyoungNam Kimc, JinHo Chod, and JyungHyun Lee b,* a
Department of Electrical Engineering Graduate School, Kyungpook National University, Deagu, South Korea b Department of Biomedical Engineering, Kyungpook Nation University Hospital, [email protected], Daegu, South Korea c Graduate School of Medicine, Kyungpook National University, Daegu, South Korea d School of Electronics Engineering, College of IT Engineering, Kyungpook National University, Deagu, South Korea
Abstract. In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level. Keywords: wide dynamic range compression, implantable hearing aids, vibration transducer, fitting formula, application specific integrated circuit
1. Introduction The various types of hearing aids are being rapidly developed due to the improvements in digital signal processing and integrated circuit design. In particular, the implantable hearing aids (IHA) are being actively studied for sensorineural hearing-impaired people [1-4]. A Korea research team at Kyungpook National University has developed an IHA system which consists of an implantable microphone, an audio processor and a 3-coil vibration transducer [5-8]. The IHA detects sound by using a microphone and converts it into an electrical signal for audio processing. The vibration transducer has frequency characteristics similar to the middle and a frequency resonance at 1.5 ~ 2 kHz. The audio processor amplifies the electrical input signal to a calculated frequency-gain using the WDRC algorithm. The output stage of the audio processor needs to be designed to take into account the vibration characteristics of the vibration transducer. *Corresponding author. E-mail: JyungHyun [email protected] 0959-2989/14/$27.50 © 2014 – IOS Press and the authors. All rights reserved
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However, the previous audio processor cannot be applied to the IHA system, because it does not take into account the frequency resonance of vibration transducer. In this paper, a digital audio processing chip which is a 1-channel 3-band WDRC is designed and implemented, using computer simulation and 0.18 um application specific integrated circuit (ASIC) process. The designed chip has a 50 MHz system clock and uses a single 1.8V and 3.3 V voltage supply. The bandwidth of chip ranges from 100 Hz to 16 kHz. In addition, the output stage of designed chip drives a 16 bit parallel output at a sample rate of 32 kHz. The designed chip separates the input signal band by using a filter bank and determines the input signal level is determined with a level detector. The output gains in each band are controlled by FIG-6 fitting rule to reflect hearing loss level. 2. Design of 1-channel 3-band wide dynamic range compression The 1-channel 3-band WDRC chip for the IHA system was designed to take into account the vibration transducer characteristics with frequency resonance. 2.1. Characteristics of the vibration transducer Figure 1-(a) shows the structure of the 3-coil vibration transducer used in the IHA system. The 3piece coil consists of a central coil wound in one direction and two end coils wound in the opposite direction. Two magnets attached to the opposite direction were positioned inside the 3-piece coil. The vibrational force was generated by the interaction between the magnetic fields of the two magnets in the center and currents flowed through the central and end coils. Figure 1-(b) shows displacement of the vibration transducer. The frequency characteristic of the vibration transducer had a flat vibration at 100~1000 Hz, a frequency resonance at 1.5 ~ 2 kHz, and exhibits resonance attenuation at 2 ~10 kHz [9-13]. These results mean that designed chip has 3 frequency bands to consider the transducer characteristic.
Velocity [mm/sec]
100
10
1
0.1
Vibration transducer self-characterristic 0.01 100
1000
10000
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(a)
(b)
Fig. 1. Structure of the vibration transducer and self characteristic.
2.2. 1-channel 3-band wide dynamic range compression The basic role of the WDRC algorithm is to automatically reduce the dynamic range of a hearing impaired person and adjust the gain and maximum output level of each frequency channel based on
D.W. Kim et al. / A 1-channel 3-band wide dynamic range compression chip for vibration transducer
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the intensity levels of the input signals. These improve sound intelligibility and quality and make low intensity sounds more audible and prevent high intensity sounds from becoming uncomfortably loud [14-16]. In this study, a designed 1-channel 3-band WDRC algorithm is designed by using Matlab-simulink. The designed WDRC was composed of 3 parts, namely, a FIR filter bank, a level detector, and a compression as showed in Figure 2. The filter bank was used to divide input signals into a multiplicity of frequency bands using a 127 order FIR filter at a sample rate of 32 kHz. The direct-form structure was used to design a FIR filter and its transfer function is Eq. (1) and shown in Figure 3. The lowest frequencies were outputted by a low-pass filter, the highest frequencies by a high-pass filter, and remaining frequencies by a band-pass filter. The filter banks were designed for application with the vibration transducer, which has filter cutoff frequencies of 800 Hz, 1000 ~ 2500 Hz, and 3000Hz. Figure 4. shows a frequency response of designed FIR filter bank.
b0 + b1 z −1 + b2 z −2 + !+ bM −1 z M −1 H ( z) = z M −1
Fig. 2. The wide dynamic range compression block using Matlab-Simulink.
Fig. 3. The structure of direct-form Finite Impulse Response filter.
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The level detector estimates the signal level by using peak envelope detection to follow the maximum incoming signal, because compression gain depends on input signal level in each band. The level detector should have a quick response to prevent over amplification of increasing signal as uncomfortable loudness level and should have smooth out to perceive loudness sound of decreasing signal. The level detector algorithm is shown in Eq. (2), the output y[n] depends on alpha, beta, and input x[n]. Alpha is referred to as attack time and is fixed at 6 ms and beta is referred to as release time and it is fixed at 97 ms. Output y[n] had some ripples that were reduced by increasing the attack and release times or smoothing filter. In this paper, 64 order FIR filters were used as smoothing filters to reduce the output ripples because increasing the attack and release times lead to a group delay. The compression part adjusts the compression gain and the high level output limit using the FIG6 non-linear fitting rule. The FIG6 can be utilized to calculate gain and frequency response for low-level (40dB SPL), moderate-level (65 dB SPL), and high-level sound (95 dB SPL) [17-18]. To devise a computer-based approach to compression, FIG6 algorithm was programmed by using the embedded Simulink block in Matlab. y [n ] = alpha
× y [n − 1 ] + (1 − alpha ) × x [n ]
for x [n ] ≥ y [n − 1 ],
y [n ] = beta × y [n − 1 ] for
otherwise
(2)
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To verify the designed WDRC algorithm, input source frequency and compression hearing loss were set in different conditions. The filter banks were inputted at 500, 2000, and 4000 Hz and hearing losses for compression gains were selected at 10, 40, and 60 dB HL. Figure 3 shows the simulation results of the designed WDRC.
Fig. 5. Matlab simulation output of the designed WDRC.
3. Implementation of the application specific integrated circuit The 0.18 um ASIC process needs 2-stage of computer simulation to optimize the algorithm. The first stage involved the verification of the verilog-HDL code for semi-custom design and the second for placing and routing digital logic cells. 3.1. Verilog-HDL simulation for semi-custom process For the 0.18 um ASIC process, the designed WDRC algorithm has to be converted into verilogHDL code. To perform the verilog simulation, Spartan6 XC6SLX45T (Xilinx Inc., USA) which runs a 50 MHz system clock, with a 3.3 V operating voltage was used, and programmed verilog code by Xilinx ISE software. Simulations were carried out in the same condition when utilizing input signal source and compression hearing loss at the Matlab simulink. The simulation data in Figure 4 shows the performance of the compression algorithm for verilog-HDL code. 3.2. Implementation of ASIC For the implementation of ASIC, Design Compiler and Astro (Synopsys Inc., USA) were used. The Design Compiler provided logic synthesis of verilog-HDL code and was used to optimize design so as to provide the smallest and fastest logical representation. After synthesis, a logical net-list file was generated for Astro and the design was ready for placing and routing. Astro provided the automatic placing and routing of the logic cells. Moreover, Astro confirmed the design rule check and layout versus schematic check. Figure 5 shows the placing and routing results, die micrograph, and implemented digital audio processing chip. This final chip had a 216,159 total cell area and a data slack time of 0.03ns.
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Fig. 6. Verilog-HDL simulation output of the designed WDRC algorithm.
Fig. 7. Designed digital audio processing chip.
4. Methods and results 4.1. Frequency response of designed digital chip To measure designed chip performance, PXI-1042 (National Instruments, USA), a computer-based measurement system was used. The designed chip based on the digital algorithm did not have ADC and DAC and thus, we fabricated a test board with external ADC and DAC circuits. The external ADC used a 16-bit parallel output ADS1605 with high speed, high precision and a delta-sigma analog-todigital converter. The ADS1605 operated from a 5V analog supply and a 3V digital supply. And the digital I/O operated from 3V to 5V which was as same as input voltage level of the designed chip. Furthermore, 2nd order delta-sigma ADC with analog ASIC is being designed, so ADS1605 can utilize the designed digital chip properly. The DAC used a 16-bit parallel input DAC8822 (Texas Instruments) which was operated in low power from single 2.7V to 5V with low noise and high speed. Also, the 16 bit parallel input interface is appropriate for the designed digital chip. When a signal source was inputted into the ADC, a 16-bit digitized signal was transmitted to the designed chip and then chip performed the WDRC algorithm. Final output was measured at the DAC output port. Experiments were focusing on the frequency splitting ability of the filter bank and on the peak detecting by the level detector. The input frequency range was from 100 to 6000 Hz at the peak amplitude of 100 mV in fre-
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quency sweep test. Figure 5 shows the fast fourier transform (FFT) responses of frequency splitting at 400, 2000, and 4000 Hz, which were selected to compare the above simulation results. The measured output showed that the designed chip did not exhibit frequency distortion when the level detector performed well.
Fig. 8. Experimental results of designed digital audio processing chip.
4.2. Results of temporal bone experimentation To verify the performance of designed chip, temporal bone experiment was fabricated by using designed chip and vibration transducer. One fresh temporal bone extracted from a 62 year old male Caucasoid was used for the experiment. This experiment was based on ASTM regulation (F2504)[19]. The measurement system set up consists of DAQ system (SYsidII, www.sysidlabs.com), LDV (HLV-1000, Polytek GmbH) and probe microphone system (ER7-C, Etymotic). Simultaneously, DAQ system can generate sound source and pick up output signals. The signal source was amplified with an audio amplifier (D-75, Crown Audio inc.). First, we measured frequency response of temporal bone at 94 dB SPL and vibration characteristic of vibration transducer which is attached round window and driven 1mA rms current [20]. Figure 9. (a) shows that the frequency response of temporal bone is similar with normal stapes velocity regulated by ASTM F-2504 and vibration transducer is well attached to the round window. The discrepancies between the loaded and unloaded states were observed after attaching the transducer to round window because loading effect of transducer change vibration force and frequency resonance. But there was no significant variation in the frequency resonance. Second, the performance of designed digital chip was measured with vibration transducer. The output stage of the designed chip was connected to the input of vibration transducer. The hearing loss level of low frequency, middle frequency, and high frequency were programmed to 40 dB HL, 50 dB HL, and 60 dB HL respectively. The 0.16 Vpeak and 1.6 Vpeak sinusoidal inputs were applied to the input stage of designed chip. The 0.6 Vpeak signal means the output level of the implantable microphone which had 30 dB sensitivity approximately to 4 mV at 74 dB SPL and pre-amplifier with 40 times amplification in IHA system. And the 1.6 Vpeak signal means the input signal of the implantable microphone was 94 dB SPL. Figure 9. (b) shows the driven results of vibration transducer which is attached to round win-
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dow with designed chip. With the frequency range below 4 kHz, the vibration characteristics were similar to vibration transducer. When the input source applied 1.6 Vpeak, the frequency resonance result of designed chip was lower than self-characteristic of vibration transducer which is driven 1 mA rms. The reason of this difference is output compression limit which prevent the uncomfortable loudness level of designed chip, but there was no significant variation in the frequency resonance. As shown in Figure 9. (b), the experiment results indicate that the designed chip can reflect the frequency resonance of vibration transducer and able to apply the signal processor of IHA system. 10
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Fig. 9. Output results of cadaver experiment; (a) velocity of temporal bone and vibration transducer, (b) velocity of vibration transducer with designed digital chip
5. Conclusion The digital audio processing chip for implantable hearing aids system should be designed by considering the vibration characteristics of the vibration transducer. In this study, a 1-channel 3-band wide dynamic range compression algorithm is designed and implemented to 0.18 um process ASIC chip. The designed chip was operated at a single 1.8V supply for core power and a 3.3V for input and output interface. The chip composed of a FIR filter bank, a level detector, and a compression part, had 16 bit parallel input and output interface at 3.3V and its bandwidth was 16 kHz. From the experimental results, we confirmed performance of designed chip that successfully worked band splitting and signal level detecting and the designed chip can reflect the frequency resonance of vibration transducer in temporal bone experiment. Furthermore, gain in each band is controlled by an adjustable hearing loss variable. Therefore, it is expected that the designed chip can be applied for implantable hearing aids. In the future work, the ADC and DAC circuits will be implemented for the designed chip. 6. Acknowledgment This study was supported by a grant of the Korea Healthcare Technology R&D Project, Ministry of Health & Welfare (A092106). And this work was supported by the National Research Foundation of
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Korea (NRF) grant funded by the Korea government (MEST) (No.2012R1A1A2006475). This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2013R1A2A1A09015677). References [1]
[2] [3] [4] [5] [6]
[7]
[8]
[9]
[10] [11] [12]
[13]
[14] [15] [16] [17] [18] [19] [20]
O. Sterkers, D. Bouccara, S. Labassi, J. P. Bebear, C. Dubreuil, B. Frachet, B. Fraysse, J. P. Lavieille, J. Mabnan, C, Martin, E. Truy, A. Uziel, and Vaneecloo, A middle ear implant, the Symphonix Vibrant Soundbridge: Retrospective study of the first 125 patients implanted in France, Otology and Neurotology, vol. 24, pp. 427-436, 2003. D. D. Backous and W. Duke, Implantable middle ear hearing devices: Current state of technology and market challenges, Current Opinion in Otolaryngology & Head and Neck Sugery, vol. 14, pp. 314-318, 2006. D. S. Haynes, J. A. Uoung, G. B Wanna, and M. E. Glasscock, Middle ear implantable hearing device: An overview, Trends in Amplification, vol. 13, no. 3, pp. 206-214, 2009. A. Amold, C. Stieger, C. Candreia, F. Pfiffner, and M. Kopis, Factors improving the vibration transfer of the floating mass transducer at the round window, Otology and Neurotology, vol. 31, No. 1, pp. 122-128, Jan., 2010. B. S. Song, M. K. Kim, Y. H. Yoon, S. H. Lee, and J. H. Cho, Design of differential electromagnetic transducer for use in IME system, IEICE T TRANS. INF. & SYST., vol. E87-D, no. 5, pp. 1231-1237, 2004. Ki-Woong Seong, Eui-Sung Jung, Hyung-Gyu Lim, Jang-Woo Lee, Min-Woo Kim, Sang-Hyo Woo, Jyung-Hyun Lee, Il-Yong Park, and Jin-Ho Cho, Vibration Analysis of Human Middle Ear with Differential Floating Mass Transducer Using electrical Model, IEICE TRANS. INF. & SYST., vol. E92-D, no. 10, pp. 2156-2158, 2009. E. S. Jung, K. W. Seong, H. G. Lim, J. W. Lee, D. W. Kim, J. H. Lee, M. N. Kim, and J. H Cho, Study of frequency response of implantable microphone and vibrating transducer for the gain compensation of implantable middle ear hearing aid, Journal of Korean Sensor Society, vol. 19, no. 3, pp. 361-368, 2010. Il-Yong Park, Yoshitaka Shimizu, Kevin N. C’Connor, Sunil Puria, Jin-Ho Cho, Comparisons of electromagnetic and piezoelectric floating-mass transducers in human cadaveric temporal bones, Hearing Research, vol. 272, pp. 187-192. 2011. Min-Kyu Kim, Il-Yong Park, Byung-Seop Song, Jin-Ho Cho, Fabrication and optimal design of differential electromagnetic transducer for implantable middle ear hearing device, Biosensors and Bioelectronics, vol. 21, no. 11, pp. 2170-2175, 2006. Min-Kyu Kim, Yong-Ho Yoon, Il-Yong Park, Jin-Ho Cho, Design of differential electromagnetic transducer for implantable middle ear hearing device using finite element method, Sensors and Actuators vol. 130, pp. 234-240, 2006. H. G. Lim, “Design of Electromagnetic Vibrator for Round Window Driving Implantable hearing Aids, Doctoral Dissertation, Kyungpook National Univ., 2010. Ki-Woong Seong, Min-Woo Kim, Jyung-Hyun Lee, Myung-Nam Kim, and Jin-Ho Cho, Design of A New Vibration Transducer for Implantable Middle Ear Hearing Devices, IEEJ Transactions On Electrical And Electronic Engineering, vol. 5, pp. 608-610, 2010. Dong Ho Shin, Hyung Gyu Lim, Eui Sung Jung, Ki Woong Seong, Jyung Hyun Lee, and Jin Ho Cho, A Physical Cochlear Model for Transducer Performance Evaluation of Implantable Hearing Aid with Round Window Driver, vol. 22, no. 2, pp. 150-155, 2013. Harvey Dillon, Hearing Aids, Boomerang Press, Sydney, 2011. J. M. Kates, Digital Hearing Aids, Plural Publishing, San Diego, 2008. J. M. Kates, Principles of Digital Dynamic-Range Compression, Trends in Amplification, vol. 9, no. 2, pp. 45-76, 2005. Toni C. Gitles, and Patty T. Niquette, FIG6 in Ten, The hearing Review, vol. 2, no. 10, pp. 28-30, 1995. Mead C. Killion, Loudness-data basis for “FIG6” hearing-aid fitting targets, Journal of the Acoustical Society of America, vol. 98, issue 5, pp. 2927-2927, 1995. Http://www.astm.org/standards/F2504.htm, American society for testing and materials, U.S.A. T.G. Dietz, G.R. Ball, B. H. Katz, Partially implantable vibrating ossicular prosthesis, International Conference on Solid State Sensors and Actuator, Chicago, U.S.A., 1997.
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