A 15 MHz bandwidth, 60 Vpp, low distortion power amplifier for driving high power piezoelectric transducers Lorenzo Capineri Citation: Review of Scientific Instruments 85, 104701 (2014); doi: 10.1063/1.4897155 View online: http://dx.doi.org/10.1063/1.4897155 View Table of Contents: http://scitation.aip.org/content/aip/journal/rsi/85/10?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Characterization of piezoelectric ceramics and 1-3 composites for high power transducers Appl. Phys. Lett. 101, 032902 (2012); 10.1063/1.4737651 Design and characterization of a high-power ultrasound driver with ultralow-output impedance Rev. Sci. Instrum. 80, 114704 (2009); 10.1063/1.3258207 A megahertz bandwidth dual amplifier for driving piezoelectric actuators and other highly capacitive loads Rev. Sci. Instrum. 80, 104701 (2009); 10.1063/1.3234261 Harmonic distortion and intermodulation products in the microstrip amplifier based on a superconducting quantum interference device Appl. Phys. Lett. 78, 3666 (2001); 10.1063/1.1377043 Analysis of harmonic distortion in electroacoustic transducers under indirect drive conditions J. Acoust. Soc. Am. 101, 297 (1997); 10.1121/1.418010
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REVIEW OF SCIENTIFIC INSTRUMENTS 85, 104701 (2014)
A 15 MHz bandwidth, 60 Vpp , low distortion power amplifier for driving high power piezoelectric transducers Lorenzo Capineria) Dipartimento Ingegneria dell’Informazione, Università degli Studi di Firenze, Via S. Marta 3, 50139 Firenze, Italy
(Received 13 July 2014; accepted 21 September 2014; published online 6 October 2014) This paper presents the design and the realization of a linear power amplifier with large bandwidth (15 MHz) capable of driving low impedance ultrasonic transducers. The output current driving capability (up to 5 A) and low distortion makes it suitable for new research applications using high power ultrasound in the medical and industrial fields. The electronic design approach is modular so that the characteristics can be scaled according to specific applications and implementation details for the circuit layout are reported. Finally the characterization of the power amplifier module is presented. © 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4897155] I. INTRODUCTION
In the last decade the electronic design of power amplifiers for different ultrasonic applications have been extensively reported in the literature. The research of new noninvasive investigation methods with ultrasonic techniques with diagnostic purposes as well as for nondestructive testing often requires the use of piezoelectric probes capable of generating ultrasonic fields with high intensity and a controlled spectrum. For example, harmonic imaging requires high linearity of the power amplifier driving the transmitting element in order to separate the contributions of harmonics from the fundamental frequency. Moreover, the system resolution improvement is generally obtained by increasing the transducer bandwidth up to 10 MHz in several applications of current research and medical diagnostic equipments with ultrasonic arrays. The high number of channels and the portability of the equipment are requirements that have stimulated the design of integrated power amplifiers for ultrasonic array front end. In Ref. 1 an integrated push-pull amplifier has been proposed capable of 40 Vpp , 400 mA current output with an integrated multiplexer, demonstrating a good linearity up to 40 MHz. Another integrated solution for a class B power amplifier is reported in Refs. 2 and 3 with 90 Vpp output voltage with large GBW product up to 720 MHz across a 100 //150 pF load simulating the transducer impedance. More recently the study of ultrasonic imaging techniques with very high frequency (>100 MHz) stimulated the design of wideband power amplifiers with low distortion; an example is the single channel class A power amplifier described in Refs. 4 and 5 where passive networks have been adopted to achieve impedance matching and pre-distortion of the driving signal. For certain medical and NDT ultrasonic applications, large size ultrasonic transducers are employed to reach high power density at the operating central frequencies where the equivalent transducer impedance6 can be low as few ohms near the resonant frequency and higher of one or two order of magnitude in the bandwidth of interest. The problem of a) Email: [email protected]. Tel.: +39 055 4796376.
0034-6748/2014/85(10)/104701/11/$30.00
driving of such variable load with a power amplifier can be overcome by the design of impedance matching network7, 8 that equalize the impedance at a standard value of 50 of radiofrequency commercial power amplifiers; the passive components matching network can be rather complex when the fractional bandwidth is large (e.g., 100%) and introduces some power losses. This solution has also the disadvantage of poor flexibility because strongly depends on the complex impedance (magnitude and phase) specifically of a transducer. Another important ultrasound medical application is High Intensity Focused Ultrasound (HIFU) where ultrasonic transducers need to be driven by power amplifiers to generate high intensity ultrasonic fields for therapeutic applications. A review of the different approaches to the power amplifier design is reported in Ref. 9 where different solutions are compared for operating frequency, efficiency, output power, implanting technology, output matching, and excitation wavelet. For output power up to 50 W and bandwidth up to 10 MHz, a power amplifier with discrete components is described in Ref. 10. The authors describe in detail the design of the layout of the amplifier including the solution for thermal conditioning and the Printed Circuit Board (PCB) layout. The test on a PZT-4, 1.54 MHz transducer confirms the capability of driving low impedance transducers with high voltage (100 Vpp ) and low impedance voltage amplifier (0.01 –0.05 ). Today the research interest in new applications of high power ultrasound11 requires the availability of reliable and robust amplifiers to drive ultrasonic transducers with spectrum controlled signals. The solution presented in this work is the design of a power amplifier with output impedance very low in comparison of the transducer impedance in the frequency range of interest so that the transducer is voltage driven. The high linearity of the amplifier is another design issue to obtain the flexibility of the excitation with spectrum controlled driving signals. These signals can be generated by an arbitrary waveform generator and easily changed according to each transducer characteristics. Another issue of this amplifier design is to avoid the use of magnetic components such as inductors or transformers12 because their behavior with large frequency range (10 MHz) and large output currents (e.g., 5 A)
85, 104701-1
© 2014 AIP Publishing LLC
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Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 1. Three stages architecture of the broad bandwidth power amplifier. The maximum output current is enhanced by parallel power module and maximum voltage output and slew rate by the bridge amplifier. The duplexer circuit is an auxiliary circuit useful for ultrasonic applications that require separation of the transmitting amplifier with the low voltage low noise amplifier for the received signal. Whereas is necessary a duplexer circuit can be designed to have a negligible influence on the power amplifier characteristics.
has to be carefully studied and characterized. This choice discards high efficient class D amplifiers9 and in favor of a Class AB amplifier that is a good compromise between linearity and efficiency. The amplifier design proposed in this work is based on the bridge amplifier solution which allows doubling the voltage swing across the load respect to the voltage power supply that is limited to tens of volts. There are several integrated components that can be selected to operate at this voltage range with high slew rate and large bandwidth with unity gain. The large output current is achieved by parallelizing several power modules on both sections of the bridge amplifier. The two sections of the bridge amplifier are driven by a phase splitter stage which is in turn driven by a buffer design for a standard input impedance of 50 of the overall amplifier. The overall architecture of the amplifier is shown in Figure 1. The paper first describes the design of the amplifier according to the requirements for driving a typical ultrasonic immersion transducer (see Sec. I) and the solutions adopted to overcome the criticalities due to the asymmetric behavior of the two sections of the bridge amplifiers. The simulations of the power module sections and the overall amplifier are reported in Sec. II. In Sec. III the implementation of the power amplifier circuit with the component layout and connectors is described. In Sec. III a complete set of measurements for the amplifier characterization are finally reported. In the Conclusions possible applications of the power amplifier are discussed.
II. POWER AMPLIFIER DESIGN REQUIREMENTS
In our study was considered a typical commercial ultrasonic immersion transducer Panametrics SOT, diameter = 0.25 in., 10 MHz, internally compensated with a parallel inductor. This transducer was selected because of interest for experimentation on 2nd harmonic imaging that has been studied for more than a decade.13 The transducer bandwidth was estimated with voltage amplitude of the excitation and eco signals in a water tank with a steel planar reflector at the focal distance of the transducer, corresponding to 22 mm, and the results are reported in Table I. The electrical impedance characterization carried out in the laboratory with a vector impedance meter model HP4815A in the transducer bandwidth and the results are reported in Table II. Considering acceptable for research studies an upper value of the acoustic power density Dp = 1 W/cm2 and the transducer insertion losses I.L. = −19.3 dB, the delivered acoustic power of the transducer can be calculated Pt = 1 TABLE I. Lower fl and upper frequency fh measured at −3 dB and at −6 dB and corresponding bandwidth B for the SOT 14 ultrasonic probe.
B−3dB B−6dB
fl (MHz)
fh (MHz)
B = fh − fl (MHz)
8.36 7.85
9.58 10.03
1.22 2.18
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Rev. Sci. Instrum. 85, 104701 (2014)
TABLE II. Module and phase of SOT 14 ultrasonic probe measured at −3 dB and −6 dB lower fl and upper frequency fh . The lower impedance value in the bandwidth corresponds to the series resonance frequency fres .
|Z| () Z (deg)
fl-3dB = 8.36 (MHz)
fh-3dB = 9.58 (MHz)
fl-6dB = 7.85 (MHz)
fh-6dB = 10.03 (MHz)
fres = 11.25 (MHz)
40.3 − 68.7
21.7 − 58
54.5 − 74
17.7 − 55
6.5 −3
× (π × r2 ) = 1 × (π × 0.31752 ) = 0.3165 W = 316.5 mW, where r = /2. The electrical power required by the amplifier is estimated by the insertion losses and corresponds to Pg = Pt / (I.L. linear) = 0.3165/0.1084 = 2.91 W. If we assume that this power is converted by the real part of the transducer impedance, we can calculate the rms voltage of the driving signal generated by the amplifier for different operating frequencies. For example, in the following we estimate the Vrms for two cases: Case 1: Z(f = 10MHz) = 18 ,√ θ (10 MHz) = −55◦ , Vrms = ZPg / cos θ = 18 · 2.91/ cos(−55) = 9.55 V Case 2: Z(f = 6 MHz) = 500 ,√ θ (6 MHz) = 50◦ , Vrms = ZPg / cos θ = 500 · 2.91/ cos(50) = 47.57 V From this example we can derive the requirements for the design of the amplifier introducing also some margins: (1) Large bandwidth B(−3 dB) from 0 to fmax = 15 MHz, (2) Maximum Output voltage swing Vout = 60 Vpp , (3) Low distortion (Total Harmonic Distortion (THD) ≤ 8%), (4) |Zout | < 6.5 over the bandwidth B, (5) Voltage gain Av = 20 (26 dB), considering an output voltage of the arbitrary function generator of 3 Vpp . (6) Slew rate ≥ 2 × π × Vout max × fmax = 6.28 × 30 V × 15 MHz = 2830 V/μs (7) Iout max ≥ 0.5 × Vout max / | Zsmin | = 30 V/6.5 = 4.61 A (8) Protection from short circuits and over temperature. It can be noted that the assumed maximum value for the THD is derived from previous experience in the design of power amplifiers for ultrasonic transducers and also to be comparable with other design published in the literature5 even if our main goal is to achieve large output current capability. Moreover, in medical ultrasound application is suitable a low distortion to avoid collateral effects due to conversion of electrical to mechanical energy at frequencies different from the fundamental. III. DESIGN OF THE WIDE BANDWIDTH LINEAR POWER AMPLIFIER
The design requirements reported in Sec. II are not currently meet by any power integrated circuit. The three stages amplifier architecture shown in Figure 1 splits the problem of the requirements accomplishment by using the peculiar characteristics of each stage and so relaxing the choice of the electronic components.
The final bridge amplifier has the following advantages:
r Double the output voltage swing on the load that implies to power supply can be generated with a bench power supply unit (typically 30 V dc max) r Double the slew rate r Cancellation of even harmonics r Each power module can be operated over a large bandwidth with low distortion and the parallelization makes possible low output impedance and large output current capability. The phase splitter stage does the separation between the final power bridge amplifier and the input buffer providing voltage gain and circuit stability. The output impedance of the phase splitter will be kept low to avoid the influence of parasitic capacitance and then preserving the bandwidth specification. The input buffer with standard 50 input impedance provides a voltage source for driving the phase splitter. This design approach is effective for the realization with integrated solid circuit technology at lower power level but in the case of a discrete components solution some criticalities must be considered: (1) The two branches of the amplifier must have symmetric responses (phase and module); (2) In general for large capacitive loads, as in the case of large size ultrasonic transducers, the slew rate decreases; (3) Tolerances of integrated final power modules: in particular output impedance and slew rate. The first point is mitigated by considering a symmetric layout and the component selection with design margins; the second point is mitigated by the bridge amplifier that doubles the slew rate; finally the third point is solved by adding an equalization resistor on each module and increasing the number of modules. The details of the design choices according to the selection of components are reported in Secs. III A–III E.
A. Design and simulation of the bridge amplifier with parallel modules
The selection of an integrated component for the amplifier module has been done considering primarily the voltage power supply and slew rate requirements. A component with such characteristics is monolithic bipolar integrated buffer amplifier EL2009CT produced by èlantec.14 The main features of this component are:
r High slew rate 3000 V/μs.
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Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 2. Power amplifier module. Decoupling capacitances on the power supply are omitted.
r Wide bandwidth 125 MHz @ RL = 50 or 90 MHz r r r r
@ RL = 10 . Output current 1 A continuous. Output impedance 1 . Short circuit protected. Maximum power supply voltage Vcc = ±18 V.
In Figure 2 is reported the schematic of the designed power amplifier module. In order to explain the circuit design of Figure 2, it is necessary to analyze the characteristic of the selected power buffer amplifier. The SR of the EL2009 decreases with load capacitance to 1500 V/μs with a RLOAD 10 and CLOAD = 200 pF. Considering a possible range of transducer capacitance CLOAD from 50 pF up to 4 nF, it is clear that a single amplifier cannot satisfy the requirements. Another harmful effect of CLOAD can be estimated on the bandwidth: the 15 MHz bandwidth can be reached at unity voltage gain with CLOAD < 1000 pF. Finally the output impedance remains low as 1 up to 10 MHz with output current of 1 A. To obtain the desired module voltage gain Vout /Vin is added a driving amplifier with voltage gain Vout /Vin = 10 V/V. This stage has been realized with an AD811 current feed-back amplifier. The output voltage swing of 30 Vpp is achieved with dual power supply voltage of ±18 V. For such voltage gain the bandwidth is about 100 MHz @ −3 dB that ensures little distortion for our target fmax = 15 MHz. Another parameter provided by the manufacturer is the THD = −74 dB @ 10 MHz, Vout = 2 Vpp and voltage gain +2 V/V. The low THD provided in this test condition guarantees some tolerances but the accurate evaluation will be carried out by simulations and experimental measurements. For the design of a large bandwidth with little voltage gain oscillation is necessary to isolate the capacitive load from the output of the AD811 and then a series resistor R3 has been introduced. Because R3 will decrease the voltage gain the even-
tual compensation of this effect is obtained by an increment of the feedback resistor R2 . The analysis of phase margin for the overall stability in presence of capacitive load suggested inserting the buffer amplifier EL2009 in open loop configuration. The series resistor R3 is calculated by considering also the protection of AD811 respect to the maximum output current that is Icc = 150 mA when accidentally the output of the bridge amplifier is connected to power supply voltage Vcc = ±18 V. In this case the input of the EL2009 can be modeled with the protection circuit formed by 4 diodes that clamp the voltage to 4 Vγ and a total resistance Rγ + R3 results from the following equation: R3 + Rγ = R3 + 20 =
2Vcc − 4Vγ 150 ·
10−3
=
36 − 2.5 = 223.3 150 · 10−3 (1)
and then R3 = 223.3 − 20 = 203.3 .
(2)
The final commercial value set for R3 is 215 . The presence of this resistor generates a pole in the frequency domain voltage gain at the frequency fP = 1 / (2π × 215 × 25 × 10−12 F) ≈ 29 MHz, where it is assumed an input capacitance of 25 pF for the EL2009. Because this frequency is lower than the unity gain bandwidth of the EL2009, it confirms the choice of keeping the open loop configuration of the output buffer to maintain sufficient phase margin for the negative feed-back stability. Finally, the voltage gain of the inverting amplifier Vout /Vin = −R2 /R1 = −10 is set with RiA1 = R1 = 100 , R2 = 1 k, where RiA1 represents the input impedance seen by the phase splitter for each module (see schematic in Figure 2). The choice of the value for R1 is dictated by the tradeoff of low impedance for neglecting the parasitic capacitance of the resistor and the max load output current of the phase splitter. It is assumed to realize the phase splitter also with
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Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
Vout’/Vin
Vout/Vin
Iout
FIG. 3. Simulations for bandwidth estimation: (Black line) Vout /Vin [dB], (Dark gray line) V out /Vin [dB], (Light gray line) Iout on load resistor Rl [A]. (see schematic in Figure 2). The legend of the probe cursor indicates the values corresponding at the frequency of 51.752 MHz with the cross-air.
an AD811 current feed-back amplifier that can provide a max output current of 100 mA in linear operation. With 1.5 V maximum driving voltage (or 3 Vpp ) the input current for each module is 1.5 V/ R1 . If n is the number of parallel modules on each branch of the bridge amplifier we can verify that with n = 6 the total output current is 1.5 × n/R1 = 1.5 × 6/100 = 90 mA. The limit of n = 6 also satisfies the max output load current, because each EL2009 can deliver 1 A of current and so the max output current of the overall amplifier can reach 6 A. The estimated Zout1 ≈ 3.5 (@ Iout = 100 mA and f = 15 MHz); this value does not include the equalization resistor R1 = 1 as explained in Sec. II. Finally, the simulated overall gain response Vout /Vin provides a bandwidth of 51.75 MHz @ −3 dB (see Figure 3). This simulated result for a single module is obtained with a RL = 16.25 , which is equivalent to a load resistance of 6.5 considering n = 5 and the load impedance doubling due to the bridge amplifier configuration. Moreover, the simulation shows that the output current provided by the EL2009 is 896 mA even further on 15 MHz.
with two resistors of 590 for the inverting amplifier and a feed-back 750 resistor for the non inverting amplifier (see Figure 5). This difference is +VoutPS = 1.47 V and −VoutPS = 1.5 V evaluated at 15 MHz. In order to compensate this asymmetric behavior a trimmer of 100 is added to the input resistor of the inverting amplifier (see schematic in Figure 4). The gain response is flat and without oscillations in the bandwidth. The final version of the phase splitter was tailored to the final application that does not require any gain in DC (e.g., power driver of an inductive load). For these aim two capacitors where introduced at the output to have a high pass filter with cut off frequency fl-3dB equal to fl−3 dB =
1 = 7.96 kHz, 2π × 20 × 10−6 F
(3)
where the load of 20 is considered for n = 5 and capacitance of 1 μF. A consequence of this choice is also to decoupling the offset in DC between the phase splitter and the final bridge amplifier with n parallel modules. However, in practice the offset found in the prototype results negligible and the amplifier can be operated also in DC.
B. Design of the phase splitter driver
The phase splitter is designed with two AD811 amplifiers with voltage gain Av = +1 e Av = −1, respectively (see Figure 4). Of primary importance is the symmetry of the response of these two amplifiers for reducing distortion effects; to verify this feature the datasheet for the inverting and non inverting unity gain amplifier provides a 100 MHz bandwidth that is quite larger of the 15 MHz requirements; a further verification of the full power bandwidth is 132 MHz with a 3 Vpp output voltage across 100 /n = 20 load. The simulations pointed out a little difference in the voltage gain obtained
C. Design of input buffer
The input buffer was designed again with an EL2009 buffer because it has the capability to drive the phase splitter with low impedance over a large bandwidth. Moreover, the components with the metal case can be mounted on the same array of n output buffers with the same heat sink; further details are reported in Sec. III E. The input impedance of 50 was set with an input resistor with adequate power rating to sustain a 3 Vpp sinusoidal input signal. However, to prevent
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104701-6
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 4. Schematic of the input buffer and phase splitter.
Non Inverting Amplifier
Inverting Amplifier
FIG. 5. Simulation of the output voltage [V] of the unity gain phase splitter : inverting amplifier (black line); non inverting amplifier (white line). The legend of the probe cursor indicates the values corresponding at the frequency of 15.215 MHz with the cross-air.
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Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
Iout
Voltage Gain
FIG. 6. Simulation of the complete amplifier with Vin = 1.5 V and RL = 6.5 . (White line) Voltage gain [dB]. (Dark grey line) Output current Iout [A]. The legend of the probe cursor indicates the values corresponding at the frequency of 36.905 MHz with the cross-air.
circuit oscillation due to large input capacitance of the driving cable an isolation resistor Rs = 215 has been introduced (see Figure 4). D. Complete amplifier simulation
At the end of the design of the single blocks of the amplifier architecture described in Figure 1, a simulation of the amplifier is carried out considering the conditions of the design requirements: Rload = 6.5 , Vcc = ±18 V, Vin = 3 Vpp . The simulation in the frequency domain is reported in Figure 6 up to the frequency of 100 MHz. The simulation results are satisfactory with an upper cut off frequency fh-3dB = 36.9 MHz, and the output load current of 4.22 A. The lower cut off frequency fl-3dB = 27.11 kHz results higher than expected in (3). This discrepancy has been solved by increasing the value of 1 μF of the decoupling capacitors, besides, this is not a critical parameter for the driving of our ultrasonic transducer. The output voltage swing at 1 MHz is Vpp = 54.8 V and at 15 MHz is Vpp = 51.8 V on RL = 6.5 . Moreover, by the EL2009 datasheet we can estimate the single buffer amplifier output resistance that is R0 = 3.5 at 15 MHz, consequently the total amplifier output resistance R0eq can be evaluated: Roeq
2 2 = × Ro = × (3.5 + 1) = 1.8 . n 5
quirements of many ultrasound applications but this design is intended also for other uses such as power magnetic core drives. The thermal design is essential to keep the temperature of the power components within the admissible range. The most critical ones are the two arrays of n = 5 EL2009 output buffers that require the heat sink design. For this calculation is added also another EL2009 that is the input buffer. These 11 (2 × 5 + 1) components are provided with TO-220 case with junction-case θ JC = 4 ◦ C/W. An estimation of the thermal resistance of gel layer between the TO-220 and the heat sink is θ CS = 0.5 ◦ C/W with a TJMAX = 175 ◦ C of the EL2009. The thermal resistance between the heat sink and the environment with temperature TA is θ SA , while PD is the dissipated power. The following relationship is used to estimate the maximum θ SA : θSA =
TJ MAX − TA (θ + θCS ) . − JC PD 11
(5)
By substituting the known values and assuming TA = 25 ◦ C: θSA =
175◦ C − 25◦ C (4◦ C/W + 0.5◦ C/W) . − PD 11
(6)
(4)
E. Thermal design
The designed amplifier is a class AB and the estimated output averaging power rating is in the order of 50 W considering the operation with sinusoidal bursts and low duty cycle (less than 50%). This level of available power exceeds the re-
By simulation is calculated a PD = 41.98 W for RL = 120 at f = 10 MHz with full voltage output swing that corresponds to θ SA = 3.16 ◦ C/W. The aluminum metal case is chosen with a lower θ SA equal to 1.2 ◦ C/W. The layout of the components on the PCB is shown in Figure 7. The amplifiers AD811 are at the centre and their heat can be removed by a fan. In Figure 8(b) is shown the realization of the PCB so it can be reproduced by interested researchers.
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Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 7. Layout of components for thermal design. Central components are the phase splitter and the driver are cooled with a fan and the 11 (5 on the left and 6 on the right) power buffer are mounted on the heat sink (two aluminum bars) fixed on the two broad sides of the case.
(a)
IV. AMPLIFIER REALIZATION AND CHARACTERIZATION
The circuit layout was carefully designed to maintain symmetry between the two sections and with connections made with silver plated wire with diameter 0.8 mm to avoid increase of resistance tracks due to skin effect. The ground plane of the Eurocard board (220 mm × 100 mm, through hole pitch 2.54 mm) was essential to avoid ground loops. The first laboratory prototype is shown in Figure 8(a). After the debug of this prototype, a PCB was designed and some replicas were assembled; the final amplifier with aluminum metal case and connectors was assembled with the two-sides PCB layout shown in Figure 8(b). The resistors used are 1% tolerance and low noise and the power supply connections to each component decoupled with R-C filters. (b)
A. Amplifier characterization
For the characterization of the power amplifier a series of measurements was carried out with a laboratory set up. A digital oscilloscope Tektronix model TDS520C with two calibrated active probes TEK P6139A is interfaced with Matlab for the acquisition of signals traces of 5000 samples and the FFT calculated with Hanning window. The sampling frequency was 250 MSamples/s and this ensures that at least 20 cycles were captured. The definition of the Total Harmonic Distortion coefficient is reported below: B (7) Ds ≡ s . B 1
Ds is the distortion coefficient of order s and Bi are the Fourier coefficients, with B1 corresponding to the fundamental frequency. The THD definition follows: THD = D2 2 + D3 2 + D4 2 + D5 2 . (8) The THD was calculated considering the first five (s = 5) harmonics. The input signal was generated by an arbitrary function generator that provided an excitation sinusoidal burst signal with amplitude 3 Vpp , duration Tw = 20 μs, and
FIG. 8. (a) Final assembly of the power amplifier with metal case working also as heat sink (b) Final two sides PCB layout with Eurocard dimensions 220 mm × 100 mm × 1.6 mm. The array of output buffer in parallel are connected with large size PCB tracks.
PRF = 1 kHz. The characterization was done with three different values of power loads: 5.6 , 18 , and 120 . B. Frequency response
In Figure 9 the frequency response measured over a frequency range up to 20 MHz is reported. The gain decreases from the initial value of 25 dB at 100 kHz of 2.5 dB at 20 MHz. The phase is almost linear in this range that is important to avoid distortion of broadband signals. C. Total harmonic distortion
In Figure 10 the estimates of the THD for the input and output signals are reported. The THD (%) is calculated by applying a Hanning window on the acquired signals. The results show that THD increases with signal frequency and the amplifier introduces additional distortion respect to input driving signal: at 100 kHz the distortion introduced by the amplifier
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Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 9. Voltage gain frequency response.
is 1.5% and at 15 MHz is 3.5%. A more detailed analysis was carried out to determine the various contribution of distortion of the three stages of the amplifier. The main contribution to the distortion appears at the output of the AD811 drivers with the full voltage swing (see Fig. 11).
at 15 MHz. This result is important because it demonstrates the feasibility of very low output impedance amplifier over a large bandwidth with driving capability of low impedance transducers or loads. In Table IV are reported the measurements of the efficiency η defined as
D. Output resistance and efficiency
In Table III the values of measured output resistance of the amplifier in the bandwidth of interest are reported. It can be noticed that the output resistance remains lower than the expected value up to 10 MHz and slightly higher than 6.5
η=
Pout where Pcc = 2 · Vcc × Icc Pcc
(9)
The adopted dual power supply voltage is Vcc = 18 V.
FIG. 10. Characterization of THD [%].
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Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
TABLE III. Amplifier output resistance. f (MHz)
Rout ()
1 5 10 15
0.92 2.34 4.05 7.24
The results obtained for the efficiency are consistent with the adoption of class AB amplifiers and also with the measured output impedance. The efficiency decreases when the load impedance value is remarkably mismatched with amplifier internal impedance. In general, η decreases with the frequency except for the case of the 5.6 load where an increase at 10 MHz is measured; a possible explanation is the output impedance (around 4 , see Table III) matching with the load impedance that include also the effects of parasitic elements (series inductor and parallel capacitance).
E. Thermal design verification
The data on dissipated power can be derived directly by the measurements of efficiency reported in Table IV. It is important to estimate the fraction of the dissipated power EL2009 arrays in order to verify the assumed heat sink thermal resistance in Sec. III E. Considering the worst case with the lowest efficiency η = 5.66% and Pcc = 54.57 W, the resulting Pd is Pd = Pcc · (1 − η) = 54.57 W · (1 − 5.66/100) = 51.48 W (10) This value includes also the dissipated power of the 12 AD811. Their dissipated power is measured as ≈9.50 W that can be subtracted from the previous value: PD = Pd − 9.50 W = 51.48 W − 9.50 W = 41.98 W. (11) According to the relationship (6) in Sec. III E, the maximum estimation for θ SA = 3.16 ◦ C/W is determined, while the metal case has a lower θ SA = 1.2 ◦ C/W. Moreover, the low duty cycle in the burst type excitation as low as 1%, the thermal design has enough margins to keep the operating junction temperature of the EL2009 buffer below the maximum rating of 175 ◦ C. TABLE IV. Efficiency measurements. Load 5.6
18
120
η
1 MHz
10 MHz
1 MHz
10 MHz
1 MHz
10 MHz
Vout (V) Pout (W) Icc (A) Pcc (W) η (%)
25.8 59.89 2.950 106.2 56.39
22 43.21 1.850 66.6 64.88
29.05 23.44 1.560 56.16 41.73
26.4 19.36 1.655 59.58 32.49
29.6 3.65 1.030 37.08 9.84
27.25 3.09 1.516 54.57 5.66
FIG. 11. Harmonic distortion for a load resistance 5.6 with input sinusoidal signal of 3 Vpp at 10 MHz and full output voltage swing 52 Vpp . The bottom (gray line) viewgraph shows the distortion of the input signal. The top (black line) viewgraph the distortion on across the load.
V. CONCLUSIONS
This paper reports and discusses the electronic design architecture for a large bandwidth (15 MHz@ −3 dB) power amplifier for driving very low impedance ultrasonic transducers or actuators. The design approach has been a three stages amplifier with the final stage consisting of a bridge amplifier with large current driving capability. This is obtained with two arrays of power buffer in parallel. The methods for obtaining linearity and stability and separation between input and output over the bandwidth are discussed. The realization of the prototype including the thermal design led to a compact, low noise, efficient amplifier with the characteristics summarized below:
r B-3 dB = 20 MHz with load impedance R from 5.6 L to 120 .
rV out max = 60 Vpp (RL = 120 ) and Vout max = 52 Vpp (R = 5.6 ).
r I L = 4.65 A protected against short circuits. out max r THD (5 harmonics)
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REVIEW OF SCIENTIFIC INSTRUMENTS 85, 104701 (2014)
A 15 MHz bandwidth, 60 Vpp , low distortion power amplifier for driving high power piezoelectric transducers Lorenzo Capineria) Dipartimento Ingegneria dell’Informazione, Università degli Studi di Firenze, Via S. Marta 3, 50139 Firenze, Italy
(Received 13 July 2014; accepted 21 September 2014; published online 6 October 2014) This paper presents the design and the realization of a linear power amplifier with large bandwidth (15 MHz) capable of driving low impedance ultrasonic transducers. The output current driving capability (up to 5 A) and low distortion makes it suitable for new research applications using high power ultrasound in the medical and industrial fields. The electronic design approach is modular so that the characteristics can be scaled according to specific applications and implementation details for the circuit layout are reported. Finally the characterization of the power amplifier module is presented. © 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4897155] I. INTRODUCTION
In the last decade the electronic design of power amplifiers for different ultrasonic applications have been extensively reported in the literature. The research of new noninvasive investigation methods with ultrasonic techniques with diagnostic purposes as well as for nondestructive testing often requires the use of piezoelectric probes capable of generating ultrasonic fields with high intensity and a controlled spectrum. For example, harmonic imaging requires high linearity of the power amplifier driving the transmitting element in order to separate the contributions of harmonics from the fundamental frequency. Moreover, the system resolution improvement is generally obtained by increasing the transducer bandwidth up to 10 MHz in several applications of current research and medical diagnostic equipments with ultrasonic arrays. The high number of channels and the portability of the equipment are requirements that have stimulated the design of integrated power amplifiers for ultrasonic array front end. In Ref. 1 an integrated push-pull amplifier has been proposed capable of 40 Vpp , 400 mA current output with an integrated multiplexer, demonstrating a good linearity up to 40 MHz. Another integrated solution for a class B power amplifier is reported in Refs. 2 and 3 with 90 Vpp output voltage with large GBW product up to 720 MHz across a 100 //150 pF load simulating the transducer impedance. More recently the study of ultrasonic imaging techniques with very high frequency (>100 MHz) stimulated the design of wideband power amplifiers with low distortion; an example is the single channel class A power amplifier described in Refs. 4 and 5 where passive networks have been adopted to achieve impedance matching and pre-distortion of the driving signal. For certain medical and NDT ultrasonic applications, large size ultrasonic transducers are employed to reach high power density at the operating central frequencies where the equivalent transducer impedance6 can be low as few ohms near the resonant frequency and higher of one or two order of magnitude in the bandwidth of interest. The problem of a) Email: [email protected]. Tel.: +39 055 4796376.
0034-6748/2014/85(10)/104701/11/$30.00
driving of such variable load with a power amplifier can be overcome by the design of impedance matching network7, 8 that equalize the impedance at a standard value of 50 of radiofrequency commercial power amplifiers; the passive components matching network can be rather complex when the fractional bandwidth is large (e.g., 100%) and introduces some power losses. This solution has also the disadvantage of poor flexibility because strongly depends on the complex impedance (magnitude and phase) specifically of a transducer. Another important ultrasound medical application is High Intensity Focused Ultrasound (HIFU) where ultrasonic transducers need to be driven by power amplifiers to generate high intensity ultrasonic fields for therapeutic applications. A review of the different approaches to the power amplifier design is reported in Ref. 9 where different solutions are compared for operating frequency, efficiency, output power, implanting technology, output matching, and excitation wavelet. For output power up to 50 W and bandwidth up to 10 MHz, a power amplifier with discrete components is described in Ref. 10. The authors describe in detail the design of the layout of the amplifier including the solution for thermal conditioning and the Printed Circuit Board (PCB) layout. The test on a PZT-4, 1.54 MHz transducer confirms the capability of driving low impedance transducers with high voltage (100 Vpp ) and low impedance voltage amplifier (0.01 –0.05 ). Today the research interest in new applications of high power ultrasound11 requires the availability of reliable and robust amplifiers to drive ultrasonic transducers with spectrum controlled signals. The solution presented in this work is the design of a power amplifier with output impedance very low in comparison of the transducer impedance in the frequency range of interest so that the transducer is voltage driven. The high linearity of the amplifier is another design issue to obtain the flexibility of the excitation with spectrum controlled driving signals. These signals can be generated by an arbitrary waveform generator and easily changed according to each transducer characteristics. Another issue of this amplifier design is to avoid the use of magnetic components such as inductors or transformers12 because their behavior with large frequency range (10 MHz) and large output currents (e.g., 5 A)
85, 104701-1
© 2014 AIP Publishing LLC
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104701-2
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 1. Three stages architecture of the broad bandwidth power amplifier. The maximum output current is enhanced by parallel power module and maximum voltage output and slew rate by the bridge amplifier. The duplexer circuit is an auxiliary circuit useful for ultrasonic applications that require separation of the transmitting amplifier with the low voltage low noise amplifier for the received signal. Whereas is necessary a duplexer circuit can be designed to have a negligible influence on the power amplifier characteristics.
has to be carefully studied and characterized. This choice discards high efficient class D amplifiers9 and in favor of a Class AB amplifier that is a good compromise between linearity and efficiency. The amplifier design proposed in this work is based on the bridge amplifier solution which allows doubling the voltage swing across the load respect to the voltage power supply that is limited to tens of volts. There are several integrated components that can be selected to operate at this voltage range with high slew rate and large bandwidth with unity gain. The large output current is achieved by parallelizing several power modules on both sections of the bridge amplifier. The two sections of the bridge amplifier are driven by a phase splitter stage which is in turn driven by a buffer design for a standard input impedance of 50 of the overall amplifier. The overall architecture of the amplifier is shown in Figure 1. The paper first describes the design of the amplifier according to the requirements for driving a typical ultrasonic immersion transducer (see Sec. I) and the solutions adopted to overcome the criticalities due to the asymmetric behavior of the two sections of the bridge amplifiers. The simulations of the power module sections and the overall amplifier are reported in Sec. II. In Sec. III the implementation of the power amplifier circuit with the component layout and connectors is described. In Sec. III a complete set of measurements for the amplifier characterization are finally reported. In the Conclusions possible applications of the power amplifier are discussed.
II. POWER AMPLIFIER DESIGN REQUIREMENTS
In our study was considered a typical commercial ultrasonic immersion transducer Panametrics SOT, diameter = 0.25 in., 10 MHz, internally compensated with a parallel inductor. This transducer was selected because of interest for experimentation on 2nd harmonic imaging that has been studied for more than a decade.13 The transducer bandwidth was estimated with voltage amplitude of the excitation and eco signals in a water tank with a steel planar reflector at the focal distance of the transducer, corresponding to 22 mm, and the results are reported in Table I. The electrical impedance characterization carried out in the laboratory with a vector impedance meter model HP4815A in the transducer bandwidth and the results are reported in Table II. Considering acceptable for research studies an upper value of the acoustic power density Dp = 1 W/cm2 and the transducer insertion losses I.L. = −19.3 dB, the delivered acoustic power of the transducer can be calculated Pt = 1 TABLE I. Lower fl and upper frequency fh measured at −3 dB and at −6 dB and corresponding bandwidth B for the SOT 14 ultrasonic probe.
B−3dB B−6dB
fl (MHz)
fh (MHz)
B = fh − fl (MHz)
8.36 7.85
9.58 10.03
1.22 2.18
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104701-3
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
TABLE II. Module and phase of SOT 14 ultrasonic probe measured at −3 dB and −6 dB lower fl and upper frequency fh . The lower impedance value in the bandwidth corresponds to the series resonance frequency fres .
|Z| () Z (deg)
fl-3dB = 8.36 (MHz)
fh-3dB = 9.58 (MHz)
fl-6dB = 7.85 (MHz)
fh-6dB = 10.03 (MHz)
fres = 11.25 (MHz)
40.3 − 68.7
21.7 − 58
54.5 − 74
17.7 − 55
6.5 −3
× (π × r2 ) = 1 × (π × 0.31752 ) = 0.3165 W = 316.5 mW, where r = /2. The electrical power required by the amplifier is estimated by the insertion losses and corresponds to Pg = Pt / (I.L. linear) = 0.3165/0.1084 = 2.91 W. If we assume that this power is converted by the real part of the transducer impedance, we can calculate the rms voltage of the driving signal generated by the amplifier for different operating frequencies. For example, in the following we estimate the Vrms for two cases: Case 1: Z(f = 10MHz) = 18 ,√ θ (10 MHz) = −55◦ , Vrms = ZPg / cos θ = 18 · 2.91/ cos(−55) = 9.55 V Case 2: Z(f = 6 MHz) = 500 ,√ θ (6 MHz) = 50◦ , Vrms = ZPg / cos θ = 500 · 2.91/ cos(50) = 47.57 V From this example we can derive the requirements for the design of the amplifier introducing also some margins: (1) Large bandwidth B(−3 dB) from 0 to fmax = 15 MHz, (2) Maximum Output voltage swing Vout = 60 Vpp , (3) Low distortion (Total Harmonic Distortion (THD) ≤ 8%), (4) |Zout | < 6.5 over the bandwidth B, (5) Voltage gain Av = 20 (26 dB), considering an output voltage of the arbitrary function generator of 3 Vpp . (6) Slew rate ≥ 2 × π × Vout max × fmax = 6.28 × 30 V × 15 MHz = 2830 V/μs (7) Iout max ≥ 0.5 × Vout max / | Zsmin | = 30 V/6.5 = 4.61 A (8) Protection from short circuits and over temperature. It can be noted that the assumed maximum value for the THD is derived from previous experience in the design of power amplifiers for ultrasonic transducers and also to be comparable with other design published in the literature5 even if our main goal is to achieve large output current capability. Moreover, in medical ultrasound application is suitable a low distortion to avoid collateral effects due to conversion of electrical to mechanical energy at frequencies different from the fundamental. III. DESIGN OF THE WIDE BANDWIDTH LINEAR POWER AMPLIFIER
The design requirements reported in Sec. II are not currently meet by any power integrated circuit. The three stages amplifier architecture shown in Figure 1 splits the problem of the requirements accomplishment by using the peculiar characteristics of each stage and so relaxing the choice of the electronic components.
The final bridge amplifier has the following advantages:
r Double the output voltage swing on the load that implies to power supply can be generated with a bench power supply unit (typically 30 V dc max) r Double the slew rate r Cancellation of even harmonics r Each power module can be operated over a large bandwidth with low distortion and the parallelization makes possible low output impedance and large output current capability. The phase splitter stage does the separation between the final power bridge amplifier and the input buffer providing voltage gain and circuit stability. The output impedance of the phase splitter will be kept low to avoid the influence of parasitic capacitance and then preserving the bandwidth specification. The input buffer with standard 50 input impedance provides a voltage source for driving the phase splitter. This design approach is effective for the realization with integrated solid circuit technology at lower power level but in the case of a discrete components solution some criticalities must be considered: (1) The two branches of the amplifier must have symmetric responses (phase and module); (2) In general for large capacitive loads, as in the case of large size ultrasonic transducers, the slew rate decreases; (3) Tolerances of integrated final power modules: in particular output impedance and slew rate. The first point is mitigated by considering a symmetric layout and the component selection with design margins; the second point is mitigated by the bridge amplifier that doubles the slew rate; finally the third point is solved by adding an equalization resistor on each module and increasing the number of modules. The details of the design choices according to the selection of components are reported in Secs. III A–III E.
A. Design and simulation of the bridge amplifier with parallel modules
The selection of an integrated component for the amplifier module has been done considering primarily the voltage power supply and slew rate requirements. A component with such characteristics is monolithic bipolar integrated buffer amplifier EL2009CT produced by èlantec.14 The main features of this component are:
r High slew rate 3000 V/μs.
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104701-4
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 2. Power amplifier module. Decoupling capacitances on the power supply are omitted.
r Wide bandwidth 125 MHz @ RL = 50 or 90 MHz r r r r
@ RL = 10 . Output current 1 A continuous. Output impedance 1 . Short circuit protected. Maximum power supply voltage Vcc = ±18 V.
In Figure 2 is reported the schematic of the designed power amplifier module. In order to explain the circuit design of Figure 2, it is necessary to analyze the characteristic of the selected power buffer amplifier. The SR of the EL2009 decreases with load capacitance to 1500 V/μs with a RLOAD 10 and CLOAD = 200 pF. Considering a possible range of transducer capacitance CLOAD from 50 pF up to 4 nF, it is clear that a single amplifier cannot satisfy the requirements. Another harmful effect of CLOAD can be estimated on the bandwidth: the 15 MHz bandwidth can be reached at unity voltage gain with CLOAD < 1000 pF. Finally the output impedance remains low as 1 up to 10 MHz with output current of 1 A. To obtain the desired module voltage gain Vout /Vin is added a driving amplifier with voltage gain Vout /Vin = 10 V/V. This stage has been realized with an AD811 current feed-back amplifier. The output voltage swing of 30 Vpp is achieved with dual power supply voltage of ±18 V. For such voltage gain the bandwidth is about 100 MHz @ −3 dB that ensures little distortion for our target fmax = 15 MHz. Another parameter provided by the manufacturer is the THD = −74 dB @ 10 MHz, Vout = 2 Vpp and voltage gain +2 V/V. The low THD provided in this test condition guarantees some tolerances but the accurate evaluation will be carried out by simulations and experimental measurements. For the design of a large bandwidth with little voltage gain oscillation is necessary to isolate the capacitive load from the output of the AD811 and then a series resistor R3 has been introduced. Because R3 will decrease the voltage gain the even-
tual compensation of this effect is obtained by an increment of the feedback resistor R2 . The analysis of phase margin for the overall stability in presence of capacitive load suggested inserting the buffer amplifier EL2009 in open loop configuration. The series resistor R3 is calculated by considering also the protection of AD811 respect to the maximum output current that is Icc = 150 mA when accidentally the output of the bridge amplifier is connected to power supply voltage Vcc = ±18 V. In this case the input of the EL2009 can be modeled with the protection circuit formed by 4 diodes that clamp the voltage to 4 Vγ and a total resistance Rγ + R3 results from the following equation: R3 + Rγ = R3 + 20 =
2Vcc − 4Vγ 150 ·
10−3
=
36 − 2.5 = 223.3 150 · 10−3 (1)
and then R3 = 223.3 − 20 = 203.3 .
(2)
The final commercial value set for R3 is 215 . The presence of this resistor generates a pole in the frequency domain voltage gain at the frequency fP = 1 / (2π × 215 × 25 × 10−12 F) ≈ 29 MHz, where it is assumed an input capacitance of 25 pF for the EL2009. Because this frequency is lower than the unity gain bandwidth of the EL2009, it confirms the choice of keeping the open loop configuration of the output buffer to maintain sufficient phase margin for the negative feed-back stability. Finally, the voltage gain of the inverting amplifier Vout /Vin = −R2 /R1 = −10 is set with RiA1 = R1 = 100 , R2 = 1 k, where RiA1 represents the input impedance seen by the phase splitter for each module (see schematic in Figure 2). The choice of the value for R1 is dictated by the tradeoff of low impedance for neglecting the parasitic capacitance of the resistor and the max load output current of the phase splitter. It is assumed to realize the phase splitter also with
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104701-5
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
Vout’/Vin
Vout/Vin
Iout
FIG. 3. Simulations for bandwidth estimation: (Black line) Vout /Vin [dB], (Dark gray line) V out /Vin [dB], (Light gray line) Iout on load resistor Rl [A]. (see schematic in Figure 2). The legend of the probe cursor indicates the values corresponding at the frequency of 51.752 MHz with the cross-air.
an AD811 current feed-back amplifier that can provide a max output current of 100 mA in linear operation. With 1.5 V maximum driving voltage (or 3 Vpp ) the input current for each module is 1.5 V/ R1 . If n is the number of parallel modules on each branch of the bridge amplifier we can verify that with n = 6 the total output current is 1.5 × n/R1 = 1.5 × 6/100 = 90 mA. The limit of n = 6 also satisfies the max output load current, because each EL2009 can deliver 1 A of current and so the max output current of the overall amplifier can reach 6 A. The estimated Zout1 ≈ 3.5 (@ Iout = 100 mA and f = 15 MHz); this value does not include the equalization resistor R1 = 1 as explained in Sec. II. Finally, the simulated overall gain response Vout /Vin provides a bandwidth of 51.75 MHz @ −3 dB (see Figure 3). This simulated result for a single module is obtained with a RL = 16.25 , which is equivalent to a load resistance of 6.5 considering n = 5 and the load impedance doubling due to the bridge amplifier configuration. Moreover, the simulation shows that the output current provided by the EL2009 is 896 mA even further on 15 MHz.
with two resistors of 590 for the inverting amplifier and a feed-back 750 resistor for the non inverting amplifier (see Figure 5). This difference is +VoutPS = 1.47 V and −VoutPS = 1.5 V evaluated at 15 MHz. In order to compensate this asymmetric behavior a trimmer of 100 is added to the input resistor of the inverting amplifier (see schematic in Figure 4). The gain response is flat and without oscillations in the bandwidth. The final version of the phase splitter was tailored to the final application that does not require any gain in DC (e.g., power driver of an inductive load). For these aim two capacitors where introduced at the output to have a high pass filter with cut off frequency fl-3dB equal to fl−3 dB =
1 = 7.96 kHz, 2π × 20 × 10−6 F
(3)
where the load of 20 is considered for n = 5 and capacitance of 1 μF. A consequence of this choice is also to decoupling the offset in DC between the phase splitter and the final bridge amplifier with n parallel modules. However, in practice the offset found in the prototype results negligible and the amplifier can be operated also in DC.
B. Design of the phase splitter driver
The phase splitter is designed with two AD811 amplifiers with voltage gain Av = +1 e Av = −1, respectively (see Figure 4). Of primary importance is the symmetry of the response of these two amplifiers for reducing distortion effects; to verify this feature the datasheet for the inverting and non inverting unity gain amplifier provides a 100 MHz bandwidth that is quite larger of the 15 MHz requirements; a further verification of the full power bandwidth is 132 MHz with a 3 Vpp output voltage across 100 /n = 20 load. The simulations pointed out a little difference in the voltage gain obtained
C. Design of input buffer
The input buffer was designed again with an EL2009 buffer because it has the capability to drive the phase splitter with low impedance over a large bandwidth. Moreover, the components with the metal case can be mounted on the same array of n output buffers with the same heat sink; further details are reported in Sec. III E. The input impedance of 50 was set with an input resistor with adequate power rating to sustain a 3 Vpp sinusoidal input signal. However, to prevent
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104701-6
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 4. Schematic of the input buffer and phase splitter.
Non Inverting Amplifier
Inverting Amplifier
FIG. 5. Simulation of the output voltage [V] of the unity gain phase splitter : inverting amplifier (black line); non inverting amplifier (white line). The legend of the probe cursor indicates the values corresponding at the frequency of 15.215 MHz with the cross-air.
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104701-7
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
Iout
Voltage Gain
FIG. 6. Simulation of the complete amplifier with Vin = 1.5 V and RL = 6.5 . (White line) Voltage gain [dB]. (Dark grey line) Output current Iout [A]. The legend of the probe cursor indicates the values corresponding at the frequency of 36.905 MHz with the cross-air.
circuit oscillation due to large input capacitance of the driving cable an isolation resistor Rs = 215 has been introduced (see Figure 4). D. Complete amplifier simulation
At the end of the design of the single blocks of the amplifier architecture described in Figure 1, a simulation of the amplifier is carried out considering the conditions of the design requirements: Rload = 6.5 , Vcc = ±18 V, Vin = 3 Vpp . The simulation in the frequency domain is reported in Figure 6 up to the frequency of 100 MHz. The simulation results are satisfactory with an upper cut off frequency fh-3dB = 36.9 MHz, and the output load current of 4.22 A. The lower cut off frequency fl-3dB = 27.11 kHz results higher than expected in (3). This discrepancy has been solved by increasing the value of 1 μF of the decoupling capacitors, besides, this is not a critical parameter for the driving of our ultrasonic transducer. The output voltage swing at 1 MHz is Vpp = 54.8 V and at 15 MHz is Vpp = 51.8 V on RL = 6.5 . Moreover, by the EL2009 datasheet we can estimate the single buffer amplifier output resistance that is R0 = 3.5 at 15 MHz, consequently the total amplifier output resistance R0eq can be evaluated: Roeq
2 2 = × Ro = × (3.5 + 1) = 1.8 . n 5
quirements of many ultrasound applications but this design is intended also for other uses such as power magnetic core drives. The thermal design is essential to keep the temperature of the power components within the admissible range. The most critical ones are the two arrays of n = 5 EL2009 output buffers that require the heat sink design. For this calculation is added also another EL2009 that is the input buffer. These 11 (2 × 5 + 1) components are provided with TO-220 case with junction-case θ JC = 4 ◦ C/W. An estimation of the thermal resistance of gel layer between the TO-220 and the heat sink is θ CS = 0.5 ◦ C/W with a TJMAX = 175 ◦ C of the EL2009. The thermal resistance between the heat sink and the environment with temperature TA is θ SA , while PD is the dissipated power. The following relationship is used to estimate the maximum θ SA : θSA =
TJ MAX − TA (θ + θCS ) . − JC PD 11
(5)
By substituting the known values and assuming TA = 25 ◦ C: θSA =
175◦ C − 25◦ C (4◦ C/W + 0.5◦ C/W) . − PD 11
(6)
(4)
E. Thermal design
The designed amplifier is a class AB and the estimated output averaging power rating is in the order of 50 W considering the operation with sinusoidal bursts and low duty cycle (less than 50%). This level of available power exceeds the re-
By simulation is calculated a PD = 41.98 W for RL = 120 at f = 10 MHz with full voltage output swing that corresponds to θ SA = 3.16 ◦ C/W. The aluminum metal case is chosen with a lower θ SA equal to 1.2 ◦ C/W. The layout of the components on the PCB is shown in Figure 7. The amplifiers AD811 are at the centre and their heat can be removed by a fan. In Figure 8(b) is shown the realization of the PCB so it can be reproduced by interested researchers.
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104701-8
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 7. Layout of components for thermal design. Central components are the phase splitter and the driver are cooled with a fan and the 11 (5 on the left and 6 on the right) power buffer are mounted on the heat sink (two aluminum bars) fixed on the two broad sides of the case.
(a)
IV. AMPLIFIER REALIZATION AND CHARACTERIZATION
The circuit layout was carefully designed to maintain symmetry between the two sections and with connections made with silver plated wire with diameter 0.8 mm to avoid increase of resistance tracks due to skin effect. The ground plane of the Eurocard board (220 mm × 100 mm, through hole pitch 2.54 mm) was essential to avoid ground loops. The first laboratory prototype is shown in Figure 8(a). After the debug of this prototype, a PCB was designed and some replicas were assembled; the final amplifier with aluminum metal case and connectors was assembled with the two-sides PCB layout shown in Figure 8(b). The resistors used are 1% tolerance and low noise and the power supply connections to each component decoupled with R-C filters. (b)
A. Amplifier characterization
For the characterization of the power amplifier a series of measurements was carried out with a laboratory set up. A digital oscilloscope Tektronix model TDS520C with two calibrated active probes TEK P6139A is interfaced with Matlab for the acquisition of signals traces of 5000 samples and the FFT calculated with Hanning window. The sampling frequency was 250 MSamples/s and this ensures that at least 20 cycles were captured. The definition of the Total Harmonic Distortion coefficient is reported below: B (7) Ds ≡ s . B 1
Ds is the distortion coefficient of order s and Bi are the Fourier coefficients, with B1 corresponding to the fundamental frequency. The THD definition follows: THD = D2 2 + D3 2 + D4 2 + D5 2 . (8) The THD was calculated considering the first five (s = 5) harmonics. The input signal was generated by an arbitrary function generator that provided an excitation sinusoidal burst signal with amplitude 3 Vpp , duration Tw = 20 μs, and
FIG. 8. (a) Final assembly of the power amplifier with metal case working also as heat sink (b) Final two sides PCB layout with Eurocard dimensions 220 mm × 100 mm × 1.6 mm. The array of output buffer in parallel are connected with large size PCB tracks.
PRF = 1 kHz. The characterization was done with three different values of power loads: 5.6 , 18 , and 120 . B. Frequency response
In Figure 9 the frequency response measured over a frequency range up to 20 MHz is reported. The gain decreases from the initial value of 25 dB at 100 kHz of 2.5 dB at 20 MHz. The phase is almost linear in this range that is important to avoid distortion of broadband signals. C. Total harmonic distortion
In Figure 10 the estimates of the THD for the input and output signals are reported. The THD (%) is calculated by applying a Hanning window on the acquired signals. The results show that THD increases with signal frequency and the amplifier introduces additional distortion respect to input driving signal: at 100 kHz the distortion introduced by the amplifier
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104701-9
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
FIG. 9. Voltage gain frequency response.
is 1.5% and at 15 MHz is 3.5%. A more detailed analysis was carried out to determine the various contribution of distortion of the three stages of the amplifier. The main contribution to the distortion appears at the output of the AD811 drivers with the full voltage swing (see Fig. 11).
at 15 MHz. This result is important because it demonstrates the feasibility of very low output impedance amplifier over a large bandwidth with driving capability of low impedance transducers or loads. In Table IV are reported the measurements of the efficiency η defined as
D. Output resistance and efficiency
In Table III the values of measured output resistance of the amplifier in the bandwidth of interest are reported. It can be noticed that the output resistance remains lower than the expected value up to 10 MHz and slightly higher than 6.5
η=
Pout where Pcc = 2 · Vcc × Icc Pcc
(9)
The adopted dual power supply voltage is Vcc = 18 V.
FIG. 10. Characterization of THD [%].
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP: 134.71.135.191 On: Tue, 25 Nov 2014 10:30:53
104701-10
Lorenzo Capineri
Rev. Sci. Instrum. 85, 104701 (2014)
TABLE III. Amplifier output resistance. f (MHz)
Rout ()
1 5 10 15
0.92 2.34 4.05 7.24
The results obtained for the efficiency are consistent with the adoption of class AB amplifiers and also with the measured output impedance. The efficiency decreases when the load impedance value is remarkably mismatched with amplifier internal impedance. In general, η decreases with the frequency except for the case of the 5.6 load where an increase at 10 MHz is measured; a possible explanation is the output impedance (around 4 , see Table III) matching with the load impedance that include also the effects of parasitic elements (series inductor and parallel capacitance).
E. Thermal design verification
The data on dissipated power can be derived directly by the measurements of efficiency reported in Table IV. It is important to estimate the fraction of the dissipated power EL2009 arrays in order to verify the assumed heat sink thermal resistance in Sec. III E. Considering the worst case with the lowest efficiency η = 5.66% and Pcc = 54.57 W, the resulting Pd is Pd = Pcc · (1 − η) = 54.57 W · (1 − 5.66/100) = 51.48 W (10) This value includes also the dissipated power of the 12 AD811. Their dissipated power is measured as ≈9.50 W that can be subtracted from the previous value: PD = Pd − 9.50 W = 51.48 W − 9.50 W = 41.98 W. (11) According to the relationship (6) in Sec. III E, the maximum estimation for θ SA = 3.16 ◦ C/W is determined, while the metal case has a lower θ SA = 1.2 ◦ C/W. Moreover, the low duty cycle in the burst type excitation as low as 1%, the thermal design has enough margins to keep the operating junction temperature of the EL2009 buffer below the maximum rating of 175 ◦ C. TABLE IV. Efficiency measurements. Load 5.6
18
120
η
1 MHz
10 MHz
1 MHz
10 MHz
1 MHz
10 MHz
Vout (V) Pout (W) Icc (A) Pcc (W) η (%)
25.8 59.89 2.950 106.2 56.39
22 43.21 1.850 66.6 64.88
29.05 23.44 1.560 56.16 41.73
26.4 19.36 1.655 59.58 32.49
29.6 3.65 1.030 37.08 9.84
27.25 3.09 1.516 54.57 5.66
FIG. 11. Harmonic distortion for a load resistance 5.6 with input sinusoidal signal of 3 Vpp at 10 MHz and full output voltage swing 52 Vpp . The bottom (gray line) viewgraph shows the distortion of the input signal. The top (black line) viewgraph the distortion on across the load.
V. CONCLUSIONS
This paper reports and discusses the electronic design architecture for a large bandwidth (15 MHz@ −3 dB) power amplifier for driving very low impedance ultrasonic transducers or actuators. The design approach has been a three stages amplifier with the final stage consisting of a bridge amplifier with large current driving capability. This is obtained with two arrays of power buffer in parallel. The methods for obtaining linearity and stability and separation between input and output over the bandwidth are discussed. The realization of the prototype including the thermal design led to a compact, low noise, efficient amplifier with the characteristics summarized below:
r B-3 dB = 20 MHz with load impedance R from 5.6 L to 120 .
rV out max = 60 Vpp (RL = 120 ) and Vout max = 52 Vpp (R = 5.6 ).
r I L = 4.65 A protected against short circuits. out max r THD (5 harmonics)
