Journal of Neuroscience Methods 227 (2014) 140–150

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Journal of Neuroscience Methods journal homepage: www.elsevier.com/locate/jneumeth

Computational Neuroscience

A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants Yuning Yang a,∗ , Awais M. Kamboh b , Andrew J. Mason a a b

Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI 48824, USA School of Electrical Engineering and Computer Science, National University of Science and Technology, Islamabad, Pakistan

h i g h l i g h t s • This paper presents the design of a complete multi-channel neural recording compression and communication system suitable for intra-cortical neural interfaces.

• The compression engine offers a practical data compression solution that faithfully preserves neural information. • The communication engine utilizes a protocol capable of error handling. • A 32-channel neural compression and communication chip designed in 0.13 ␮m CMOS occupies only 1.21 mm2 and consumes 800 ␮W of power.

a r t i c l e

i n f o

Article history: Received 15 August 2013 Received in revised form 12 February 2014 Accepted 13 February 2014 Keywords: Neural compression Communication protocol Discrete wavelet transform VLSI

a b s t r a c t This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13 ␮m CMOS, the core of the neural compression and communication chip occupies only 1.21 mm2 and consumes 800 ␮W of power (25 ␮W per channel at 26 KS/s) demonstrating an effective solution for intra-cortical neural interfaces. © 2014 Elsevier B.V. All rights reserved.

1. Introduction Brain machine interfaces have come to be recognized as a powerful tool in assisting patients with neural disorders. Individuals with severe motor limitations can especially benefit from advances in neuroprosthetic devices. Control of artificial limbs is dependent on accurate decoding of the neural signals containing preset movement parameters. In order to enable extraction of these parameters, the activity of cortical neurons needs to be recorded using microelectrode arrays of hundreds of element (Nicolelis, 2001). Because the algorithms required to extract useful information from these neural signals are computationally complex and resource hungry, the signals need to be transmitted out of the body to computationally powerful external processing units (EPU).

∗ Corresponding author. Tel.: +1 5174323506. E-mail address: [email protected] (Y. Yang). http://dx.doi.org/10.1016/j.jneumeth.2014.02.009 0165-0270/© 2014 Elsevier B.V. All rights reserved.

One of the challenges that neural engineers face is the wireless transmission of data and power between the body and the EPU. The need for a wireless link arises from various surgical complications and limited patient mobility. The solution lies in the use of implantable wireless transceivers. Enabling wireless data and power telemetry has four major hurdles, limited bandwidth, limited implantable area, limited power and high bit error rate. The data rate increases linearly with increasing number of channels or sampling rate, necessitating signal compression before transmission. The wireless transmission of data and power simultaneously results in a high data transmission error rate that necessitates error correction protocols. The implantable hardware required for signal compression and data communication must, firstly, be area efficient, to enable minimally invasive surgical procedures, and secondly, be power efficient, to avoid any damage to surrounding tissues due to temperature increase. A power density of 0.5811 mW/mm2 results in an increase of 1 ◦ C in the surrounding cortical tissue (Kim et al., 2007), establishing an effective

Y. Yang et al. / Journal of Neuroscience Methods 227 (2014) 140–150

physiological ceiling for power in any implantable device where further temperature increase can damage tissue permanently. High power efficiency is also necessary to enable longer periods of operation with little available power. A complete neural recording system typically consists of analog front end for amplification and digitization, digital circuits for signal processing and a wireless telemetry for data/power transmission. Some of the recent work on neural systems covers only the analog front end (Wattanapanitch and Sarpeshkar, 2011; Gao et al., 2012; Lopez et al., 2012). Some add wireless power/data telemetry to an analog front end (Roham et al., 2009; Song et al., 2009; Lee et al., 2010; Abdelhalim et al., 2013; Biederman et al., 2013; Yin et al., 2013). Others have added some signal processing to the analog front end for data compression to minimize bandwidth in multi-channel systems. These include systems that provide spike detection and transmit spike wavefoms (Gosselin et al., 2009) and those that generate and transmit spike time stamps (Harris et al., 2008; Sodagar et al., 2009). More extensive signal processing including feature extraction for spike sorting has been reported (Moo-Sung et al., 2009; Rizk et al., 2009) but at significant cost to the power budget. To permit low power spike sorting, digital signal processing architectures have been developed (Hoang et al., 2009; Karkare et al., 2011), but these approaches require very high bandwidth for multi-channel recordings. This bandwidth limitation becomes critical when neural activity in the region of interest is high. For wireless telemetry, efforts have been made to minimize the interference between the power and data links (Uei-Ming and Ghovanloo, 2010; Guoxing et al., 2012). It has been shown that this interference would degrade data quality by 30 dB (Guoxing et al., 2012). It has been reported that a bit error rate BER below 2 × 10−6 is necessary to preserve spike information (Bulach et al., 2012). However, a BER of 10−2.5 , which is greater than the design requirement, has reported (Harrison et al., 2009). BER was measured as a function of SNR, and it was shown that the BER is above 10−4 even for SNR as high as 7 dB (Biederman et al., 2013). To guarantee error free data transmission, an efficient error-correcting communication protocol would greatly help. Such a communication protocol would also enable exchange of configuration and control data within a complete wireless neural recording system. Although numerous building blocks for neural recording, compression and wireless transmission have been reported, the design of communication protocol hardware for such systems has been largely neglected. This paper demonstrates a 32-channel neural signal processor (NSP) that interfaces with analog front-end and RF modules of an implantable neural recording system. The NSP can simultaneously provide significant compression of multi-channel neural recordings and efficient error-free communication based on a new protocol tailored to neural implant applications. The compression system builds on prior work in discrete wavelet transform (DWT) hardware (Oweiss, 2006; Kamboh et al., 2007; Oweiss et al., 2007) and utilizes multi-level DTW, thresholding and run length encoding to minimize transmission bandwidth while preserving information for spike sorting. Error free communication is achieved based on the careful design of the data packet structure while maximizing the throughput. In addition, the NSP provides tremendous flexibility in terms of multi-channel signal fidelity vs. signal compression. The entire NSP was implemented in Verilog and tested on an FPGA. Section 2 describes the system architecture for the NSP and its relation to other blocks within a complete neural recording implant. Section 3 details the theory and design details of the compression engine. Section 4 presents an application tailored communication protocol that ensures error-free data telemetry and analyzes efficiency and throughput. Section 5 outlines the operation of the global controller and explains the configurability built into the system. Finally, VLSI implementation of the complete

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Fig. 1. High level architecture of the wireless implantable neural recording system including neural signal processor presented in this paper.

NSP and performance characterization results are presented in Section 6. 2. Architecture The high-level architecture of the wireless neural recording system is shown in Fig. 1 (Abu-Nimeh et al., 2009). It consists of two modules, defined herein as the Wireless Neural Recorder (WNR) and the Extra-cutaneous Neuro Relay (XNR). The XNR is responsible for providing power to the WNR through inductive coupling, receiving data from the WNR, relaying neural data to the external processing unit (EPU) and sending configuration commands to the WNR. The WNR is placed on the cortex under the skull and interfaces with the implanted electrode array. The WNR is composed of an RF transceiver, an analog front-end, and the NSP that is the focuses of this paper. Within this architecture, the NSP is required to compress raw signal, send compressed data and receive commands. To achieve these goals, an NSP architecture consisting of a compression engine, a communication controller and a global controller, as shown in Fig. 2, was developed. The compression engine is required to receive signals from the analog front-end circuitry where neural signals are amplified, filtered and digitized. A number of analog front-end blocks have been reported to satisfy the gain-bandwidth requirements of neural recording systems (Gosselin et al., 2009; Harrison et al., 2009; Moo-Sung et al., 2009). The NSP has been designed to work with analog front-end blocks that provide 10-bit

Fig. 2. Block diagram of the neural signal processor that provides data compression within the implantable neural recording system.

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Fig. 3. Operational flow of DWT algorithm with four levels of decomposition. thx represents a thresholding operation resulting in new values represented by primes (‘).

resolution and 26 KS/s per channel. Within the compression engine, neural signals should be processed to reduce the bandwidth with limited information loss and then delivered to the communication controller where data is stuffed into packets that are sent to a bidirectional telemetry link outside of the NSP. Our NSP design assumes the telemetry link is an inductively coupled transceiver architecture that provides high power transmission efficiency in biomedical implanted devices. Specifically, we utilize a transceiver with a 13.56 MHz carrier frequency and maximum data rate of 1 Mbps (Ghovanloo and Atluri, 2007). The NSP clock frequency of 13.56 MHz is extracted from this carrier frequency, and the communication protocol design is based on this data rate. The communication controller is required to implement a protocol for inductive links that maximizes the throughput for data transmission and reception with highly efficient error-free performance. The global controller should unite the compression engine and the communication controller into a highly configurable system. It should also interpret commands from the EPU and manage several modes of operation and various configuration settings. 3. Compression The compression engine of the NSP has been designed to employ both lossy and lossless techniques to compress neural data. As shown in Fig. 2, the compression engine is composed of three main stages: a DWT circuit that generates a sparse representation of the incoming neural signals, a multi-level threshold circuit that serves a dual purpose of de-noising and spike detection, and a run length encoder (RLE) that removes any redundancy from the streaming data before it is formatted into packets for wireless transmission.

Fig. 4. Block diagram for sequential calculation of DWT (adapted from Kamboh et al. 2007).

generally result in fewer significant coefficients. The relatively long intervals between samples of neural signals allow the use of computation hardware that prioritizes power and area efficiency over speed. As derived in our prior system-level analysis (Oweiss et al., 2007), the power-area product can be minimized by an architecture that sequentially evaluates the DWT of multi-channel data in real time. The lifting scheme was used to compute the transform coefficients and has been shown to require fewer computations than convolution based filtering (Kamboh et al., 2008). Although the architecture permits scaling up to any number of channels, implementation is limited by technology-based factors including clock frequency, power density and chip size. 32 channels were chosen for our design based on the chip real estate available for DWT within the overall system. Utilizing the Verilog code from our prior DWT design (Kamboh et al., 2007), the circuit in Fig. 4 was incorporated as a block within the new compression engine. The computation core performs sequential calculation of DWT coefficients. The memory blocks store temporary data and intermediate results and have been partitioned based on different access patterns. The state-machine controller manages timing and data flow among the blocks. The controller was synthesized using a standard cells library while the other blocks were custom designed to minimize power and chip area. 3.2. Lossy compression

3.1. Discrete wavelet transform DWT utilizes low pass and high pass filters to decompose signals into different frequency bands as described by aj+1 (k) =



h0 (n − 2k)aj (k)

 n

dj+1 (k) =

g0 (n − 2k)aj (k)

n

where aj and dj are approximation and detail coefficients, respectively, at each level j, and h0 and g0 are the low and high pass filters, respectively. Fig. 3 shows the operational flow for a fourlevel DWT decomposition. At each level, aj is filtered by h0 and g0 , generating coefficients (aj+1 )temp and (dj+1 )temp respectively. Then (aj+1 )temp and (dj+1 )temp are downsampled by two to obtain aj+1 and dj+1 . DWT has a capability for high compression while preserving the temporal information of neural signals (Oweiss, 2006). In prior work (Kamboh et al., 2007), we developed a DWT circuit that supports 4 levels of wavelet decomposition with up to 32 channels of simultaneous data. Multiple decomposition levels

Coefficients at the output of the DWT stage can be viewed as sparse packets of energy that do not, by themselves, result in any compression. However, compression can be achieved by following the DWT with a thresholding stage that reduces the insignificant low-energy coefficients to zero and let high-energy coefficients pass. The low-energy coefficients have little or no significant information and mainly contribute to noise. The high energy coefficients invariably correspond to different spikes and events within the neural signal, allowing spike sorting even without reconstruction (Oweiss, 2006). Fig. 3 shows the operational flow for a four-level DWT decomposition and where the threshold values are applied. After decomposition of the previous level’s aj coefficients, the threshold is applied to the current level dj+1 coefficients. At the last level, thresholds are applied to a4 and d4 separately. Thus, there are a total of five thresholds for the four-level DWT. “Symmlet4” was chosen as the wavelet basis for DWT because it has been demonstrated to generate an optimal compression for neural signals (Oweiss, 2006). The values to which the thresholds are set are of critical importance since they determine both the quality of reconstruction

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Fig. 5. System diagram for the threshold and the RLE blocks.

and the final rate of compression. Methods to determine the optimal threshold is an ongoing investigation. However, it has been established that the best compression is achieved by using separate threshold values for each decomposition level (Oweiss, 2006). Thus, results from each level of each channel must be treated separately and will form a stream of data containing information that is virtually independent of the information from other channels and levels within the data stream. As explained in Section 5, the overall compression system was designed to operate in two modes: monitor mode and compression mode. In monitor mode the system bypasses the DWT, threshold and RLE blocks and sends the uncompressed neural signal directly to the packet formatter. Monitor mode is used by the XNR to analyze the statistical properties of individual channels and calculate the optimal threshold values for each channel and level. These threshold values are then transmitted back to the implanted system to set compression parameters for use in compression mode, where all system blocks are activated to compress data. Main functional blocks of the multi-level threshold and RLE stages are shown in Fig. 5. The threshold block includes a set of memory registers that contain threshold values for each level of each channel. Since the last level of DWT produces two separate coefficients streams, an N level system would have N + 1 threshold values for each channel. These values would be determined externally and then stored into the memory sequentially before the DWT operation begins. Threshold values are stored in each of the corresponding memory registers. Any of these values can be updated during system operation. Input data (from ADC output) are assigned 10-bit digital codes having unitless values between +511 to −511. Correspondingly, the thresholds are 9-bit digital codes representing the magnitude 0–511. The DWT block generates values in signed-magnitude form. The magnitude is compared against the threshold value using a magnitude comparator; if found smaller than the threshold, a 10-bit zero is generated at the output. If equal or greater, the original value is relayed to the output. 3.3. Lossless compression Several lossless data compressors exist in literature, with varied computational complexity and storage requirements. A few popular techniques are Huffman coders, Lempel Ziv coder, arithmetic encoders and their variants. Most of these algorithms require prior statistical knowledge of the incoming data set, and thus the rate of compression achieved is directly related to the accuracy of this information. Since the algorithms are variable length encoders, under certain conditions, they approach the theoretical limits of compression, limited by the entropy of the incoming signal. However, these algorithms require prohibitively large storage to maintain the dictionary of codes. Use of Huffman coding is not possible since, in this application, the size and statistical properties of the source alphabet (number of possible data values) depend on

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the threshold values, which are ideally controllable by the neuroscientist. The only statistical information available for this thresholding compression system is that much of the data stream consists of zeroes. Run length encoding is best suited for data with long repetitive strings of values; in addition, it is very conservative in required resources. Because long strings of zeros are expected at the output of the threshold block, RLE is a good lossless compression choice. Though RLE is not an optimal encoding scheme in general, when given very long repetitive sequences it approaches the performance of near-optimal algorithms. Given that, for this implementation, one word refers to 10-bit values and that a 10-bit counter can count up to 1023, our implementation of RLE can be summarized by the following rules. (1) Transmit all non-zero words as is. (2) Convert all negative zeros (represented by X) to positive zeros. (3) Replace a sequence of zeros (two or more) with an X (negative zero) word and a zero-count word. (4) If the zero count reaches 1023, send 1023 and restart a new sequence of zeros. Following these rules, an example 40 word sequence of input data given by BD000A0000000A000000CB0A0000000000D00000D where {0,A,B,C,D} is the source alphabet and X represents a negative zero, would be reduced (by half) to the 20 word output sequence BDX3AX7AX6CB0AX10DX5D Sequences from real neural recordings have been observed to yield much better compression ratios. Since we do not expect long sequences of repeating non-zero values, this implementation compresses only the sequences of zeros. This scheme results in fixed length codes, which have a computational resource advantage. Furthermore, since the entire signal (not spikes only) is represented by the transmitted data, timing information can be reconstructed at the receiver without adding time stamps to the data packet. 4. Communication The communication system transmits compressed neural spike data from the WNR to the XNR and at the same time receives configuration settings and commands from the XNR. For cortical implants, this communication takes place across the skull and the scalp, thus the WNR and XNR are effectively only a few millimeters apart. The system has been designed assuming that the WNR will receive power and a clock signal wirelessly from the XNR. In designing the communication system, several requirements must be met. As with all circuits in the WNR, power dissipation is a primary concern and must be minimized. Also, wireless carrier frequencies in the range of a few megahertz are best because human tissue is known to absorb higher radio frequencies. This system has been designed to abide by the FCC Part 15 recommendation of 13.56 MHz for biomedical applications. Finally, because neural data is considered pristine, error detection is necessary at both ends of the communication channel. This also requires packets to be retransmitted until error free data has been received. 4.1. Packet structures Two different packet structures are used during communication, one for uplink from WNR to XNR and the other for the downlink from XNR to WNR. As shown in Fig. 6, the uplink packet, also called

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corresponding Command Data. As in the Data Packet, the Command Packet also contains identification and request bits. A 5-bit CRC is used in the command packet. 4.2. Protocol design

Fig. 6. (Top) XNR to WNR command packet. (Bottom) WNR to XNR data packet.

the Data Packet, is large and contains up to eighty 10-bit values representing the compressed neural data. The Data Packet header word contains 8-bits of channel and DWT level information for the first data word; all, subsequent values conform to a predetermined sequence of channels and levels. The packet also contains one current Packet ID bit to establish proper data sequencing at the receiving side and a Command Request ID as an acknowledgment for the last packet received. If the request ID is the same as the ID of the last transmitted packet, the receiver is requesting retransmission of the last packet. Finally, the packet contains 8-bits of Cyclic Redundancy Check (CRC) for error detection. The CRC bits allow error-detection at the receiver side. The choice of CRC depends on the desired percentage of error detection. No CRC choice can guarantee absolutely error free communication; however, greater number of CRC bits corresponds to better error detection capabilities. These capabilities are achieved, essentially, at the cost of higher redundancy and thus lower throughput. For the uplink frame of 210 bits, an 8-bit CRC-8-CCITT (International Telecommunication Union) standard has been selected for this application. This code guarantees to detect all single bit and double bit errors as well as all odd number of errors. It also guarantees detection for burst errors of up to 8 consecutive bits. Some errors may pass through if the error pattern results in another valid pattern. For the 8-bit CRC there is an average of 1 error pattern that will not be detected for every 255 that would be detected, i.e., it should be able to detect 255/256 or 99.6% of all possible errors (Tanenbaum, 2002). As a result, the data packet has a size of 818 bits. The downlink packet, also called the Command Packet, is used to send commands from XNR to WNR. As shown in Fig. 6, this 25bit packet contains 8 bits for the Command Code and 10 bits for

To conserve power and bandwidth, a half-duplex transceiver was chosen, with significant impact on protocol design. A single 1 Mbps channel is used for both uplink and downlink data transfer. A stop-and-wait based approach has been taken to meet the requirements of the system, including a need for the WNR to wait for a packet to fill before transmission of streaming data. At the same time, the XNR has to transfer various configurations and commands to the WNR. However, the XNR does not have to wait for streaming data to become available. Since the system clock is generated wirelessly, another issue is the transmitter-receiver re-synchronization once a disruption takes place. Several sophisticated window-based protocols have been reported in the literature. However, with streaming data, where the transmitter sometimes has to wait for the data to become available, window-based protocols may take very long to hand channel control back to the XNR. This would preclude instant changes in configuration of the WNR. In addition, the protocol presented here has the obvious hardware area and complexity advantage of not having to maintain a number of previous packets. Fig. 7(a) shows the normal flow diagram of the modified protocol. The diagram depicts normal flow of data as well as error handling. Command Packets are represented with a ‘C,’ and the Data Packets are represented with a ‘D’. Three important parameters in the flow diagram are the three configurable timeout values described below. An essential feature included in the protocol is the programmable ‘Data Not Ready’ timeout, referred to in Fig. 7(b) as TimeOut N1 (TN1 ). This timeout occurs when the XNR requests new data from WNR but the WNR packet is not filled completely and thus not ready for transmission. TN1 is the maximum time that the WNR waits before stuffing and transmitting the packet if it is incompletely filled. This timeout is only relevant when neural activity is low and the spikes are sparse. A packet is transmitted as soon as the buffer fills. However, if a single spike is followed by a very long string of zeros it can take up to approximately 100 ms to completely fill the Data Packet. This ‘delay’ in transmission

Fig. 7. Flow diagrams for the communication protocol. The diagram shows normal flow as well as handling of error conditions. (a) Normal operation. (b) Timeout TN1 when neural activity is low. (c) Timeout TN2 when a data or command packet is loss. (d) Timeout TN3 acting as a watchdog to reset.

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global controller is responsible for synchronization of data flow between blocks, generation of respective clocks, and the engagement or bypass of certain blocks in the data path. It provides chip-level power management, interprets commands from the XNR, and changes the configuration and operation of the WNR according to the command. The operation of the WNR is controlled by several configuration registers that can be changed by commands from the XNR. 5.1. Modes of operation Fig. 8. Functional diagram for the communication controller.

may not be acceptable for certain applications where real-time spike recording and decoding is important. The timeout feature effectively provides a dynamic scaling of the Data Packet to ensure a limit to the delay in transmitting data. The default value of TN1 is set to 8 ms, but it can be reconfigured to any temporally relevant value of less than 32 ms through a command from the XNR. The XNR transmits a Command Packet as soon as it receives a Data Packet from the WNR; it does not have to wait for a new command to become available and always maintains a preconfigured Command Packet. If the WNR does not receive a command within a specified time, then TimeOut N2 (TN2 ) occurs as shown in Fig. 7(c). The WNR assumes a ‘Data or Command Packet lost’ error and retransmits the Data Packet. Let ‘TD ’ be the time to transmit a Data Packet and ‘TC ’ be the transmit time of a Command Packet. With a transmission frequency of 1 Mbps, the 818-bit Data Packet takes TD = 0.818 ms for transmission, and the 25 bit Command Packet takes TC = 0.025 ms. TN2 can then be expressed as TN2 ≥ TD + TC + 2 × TP ≈ 0.85 ms

(1)

where TP is the packet propagation delay, which is negligible due to the close proximity of the WNR and XNR. Similarly the idle time between reception of a packet and transmission of a preconfigured packet is also negligible. The reconfigurable TimeOut N3 (TN3 ) shown in Fig. 7(d) acts as a watchdog timer for the communication controller. If the WNR does not receive a packet from the XNR for three consecutive Data Packet transmissions, then the WNR communication controller resets itself assuming a ‘Break’ in communication requiring re-synchronization. TN3 can be expressed as TN3 ≥ TN1 + 3 × TN2

(2)

The default value of TN1 = 8 ms gives TN3 ≈ 10.6 ms. If needed, a reset command can be issued through the XNR that resets the WNR and initializes all settings to their default values. The functional diagram of the communication controller is shown in Fig. 8. The transmitter and the receiver use serial data in and out lines in conjunction with corresponding clock signals to communicate with the transceiver. The controller contains two frames. At any given time, one frame is the active frame while the other acts as a reserve frame. The reserve frame is filled while data from the active frame are being transmitted. It is desirable to be able to transmit the active frame twice (in case of an error) before the reserve frame fills and data overflows. As a result, from (1), the buffer should be large enough to store incoming data for a time greater than 2 × TN2 ≈ 1.7 ms. This can be achieved by settings the appropriate frame size and multi-level thresholds in the preceding block. 5. Global controller In addition to the local controller for each functional block, a global controller manages system-level operation of the WNR. The

The system operates in three modes determined by values in the configuration registers. The first two are monitor modes in which the data is transmitted without compression. These modes are called monitor spikes (MS) mode and monitor LFP (MF) mode, where LFP refers to local field potential. In the monitor mode, the compression engine is disabled and no compression takes place. Because data is uncompressed in monitor modes, only one selectable channel can be active at a given time. In MF mode, the system bypasses the high gain amplifiers and filters, routing the analog signals directly to the ADC. The transmitted signal thus contains the information embedded in the LFP as well as the neural spikes. Since MF mode includes spikes, the sampling rate is the same as MS mode. In MS mode, the amplifiers and filters are activated, resulting in a signal that contains only neural spikes without LFP effects. Four adjustable amplifier gain settings are available in the configuration registers. The third mode is called the compression mode (CM). This mode engages the digital signal compression blocks in the WNR and is capable of processing and transmitting up to 32 channels simultaneously. The configuration registers dictate which channels will be sampled and which, if any, will be ignored, permitting users to deselect inactive channels. The channels are sampled in a time division multiplexed manner maintaining separate gain settings for each channel. The ADC output is then fed to the DWT block which computes the wavelet coefficients for up to four levels of scaling. These coefficients are generated in a predefined sequence and then passed through the threshold block that replaces any insignificant values with a zero. The threshold values are assigned by the XNR and stored on the WNR. The thresholded coefficients are sent to the RLE block for compression and then forwarded to the communication controller for transmission to the XNR. The global controller permits four possible choices for the sampling rate per channel, 52 KS/s, 26 KS/s, 13 KS/s or 6.5 KS/s. The highest sampling rate of 52 KS/s can only be used in monitor modes whereas other rates can be used with all the modes. Upon reset, the system will sample channel one at 26 KS/s in MS mode. The XNR receives and processes the uncompressed data to compute appropriate thresholds and transmits the resulting values back to the WNR. Typically, the WNR then is configured to monitor the next channel until the thresholds for all the channels have been set and the WNR can be reconfigured for operation in CM mode where all channels can be processed simultaneously. 5.2. Power management The global controller also manages power for the WNR using two main techniques. First, dynamic frequency scaling (DFS) is employed whenever the WNR system is not required to function at its maximum capability; the clock frequency is scaled down, which proportionally reduces the power dissipation. A dedicated block in the global controller is used to generate clock signals for all the WNR blocks. Second, the controller disables any components not on the signal data path for a given mode of operation, reducing unnecessary transistor switching.

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Fig. 10. System performance as a function of threshold value for an example neural data set with 27 spikes.

Fig. 9. DWT block fabricated in 0.5 ␮m technology.

The analog, digital and RF modules were designed to work with separate minimum required supply voltages to conserve power. Although reducing supply voltage increases signal propagation delay, the WNR has a pipeline-based architecture where performance is not limited by the signal propagation delays. This allows for the use of Dynamic Voltage Scaling (DVS) in addition to DFS in future generations of the design.

where xn is the original signal, xˆ n is the reconstructed signal and N is the length of the signal. It has been shown that useful information other than neural noise exists in the spike intervals (Stein et al., 2005). Thus, the RMS error is calculated over the full signal instead of the spike window only. Shannon’s entropy is a measure of uncertainty associated with a random signal and can be interpreted as the average minimum length per data value, represented in bits, which must be transmitted for lossless communication. Entropy gives the theoretical limit to the achievable lossless data compression for a given data set. Mathematically, N 

H(X) = − 6. Results

p(xi )log2 p(xi )

(4)

i=1

6.1. Compression engine analysis In prior work (Kamboh et al., 2009), the DWT block of the compression engine was fabricated using a 0.5 ␮m CMOS process, and the resulting 3 mm × 3 mm chip is shown in Fig. 9. The 4-level 32-channel DWT module consumes only 3 mW of power while processing at 26 KS/s, or equivalently 95 ␮W per channel, and the active components occupy roughly 3.84 mm2 . To test the DWT chip, an FPGA was used to input experimentally obtained 10-bit neural data (Kamboh and Mason, 2013) to the DWT chip at 26 KS/s per channel. The output transform coefficients from the DWT chip were recorded by the FPGA and then transferred to a computer where the inverse-DWT was computed. The resulting signal was observed to be a bit-by-bit match compared to the original signal, verifying functionality of the DWT chip. To test the rest of the compression engine, output coefficients from the DWT chip were processed in Matlab for multi-channel thresholding and run length encoding. An analysis of spike reconstruction versus the compression obtained was performed for several different zeroing threshold values. For a fair comparison, the same threshold value was used for all channels and levels. Root mean squared (RMS) error and entropy are used as the primary measures to evaluate the performance of our system. RMS error is a measure of the average difference between the original and the reconstructed signal. This difference has two major components: the error resulting from quantization into a finite word length, and the error introduced by the thresholding operation. Mathematically,

  N 1 2 ErrRMS =  (xn − xˆ n ) N

n

(3)

where N is the total number of possible values and p(xi ) is the probability of occurrence of the ith value. For a given spike train, Fig. 10 plots the RMS error, the entropy of the transmitted sequence and the RLE compression achieved with respect to the threshold. The plots confirm the anticipated tradeoff between compression and RMS error. As expected, when thresholding is not employed (i.e. threshold is zero), the RLE does not result in any compression, entropy is at its maximum and RMS error at its minimum. The RMS error never goes to zero because of quantization noise. As the threshold value (and thus the number of zeros) increases, the RLE compression approaches the theoretical limit of entropy, which proves the effectiveness of this design. Increasing threshold also results in an increase in the RMS error. This region of operation removes noise from the signal while preserving all the neural spikes and their shapes. At very high threshold values, the system starts distorting neural spikes. Although a train of only 27 spikes was analyzed for Fig. 10, the compression ratio depends mostly on threshold and spike rate, and the number of spikes has little effect on the trends of RLE and RMS error. The optimal point of operation may vary from one application to another depending upon the quality of reconstruction desired. Because of this direct tradeoff between RMS error and compression ratio, the thresholds must be chosen to match application requirements; i.e. available bandwidth, quality of signal reconstruction required, and the power available for data transmission. The measure of quality of reconstruction also depends highly on application specific spike detection and classification algorithms employed by the neuroscientist. The degradation of spike shape due to different compression rates is demonstrated in Fig. 11, which shows the same spike at four different de-noising thresholds and compression ratios, as different settings of thresholds result in different compression ratios. Fig. 11(a) shows the original spike from the neural signal.

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Fig. 11. (a) Original signal. (b) 2 times compression. (c) 16 times compression. (d) 62 times compression. The amplitude in the y axis is a unitless 10 bit digital code.

Fig. 11(b) shows the reconstructed spike when a compression of two is achieved, i.e. the data is reduced to half. It can be noticed that spike does not undergo any noticeable deterioration whereas the surrounding noise is reduced. Fig. 11(c) shows the spike when a compression of 16 times is achieved. The noise is totally removed without any significant degradation in the noise shape. Fig. 11(d) shows the spike for a compression of 62 times. Here, the spike has been noticeable altered. This degradation may still be acceptable for certain applications since all spikes from this neuron will undergo the same changes. After a certain limit, further compression may result in lost spikes, i.e. the spike may be missed and remain undetected. As an example, using all channels of the prototype 32 channel design, a conservative threshold value of 80 resulted in an output data rate of less than 370 Kbps, providing a compression of more than 20 times compared to 8 Mbps for unprocessed data. The authors are not aware of any other publications where the spike shapes have been maintained, thus we are unable to compare results against other methods of neural signal compression.

The communication system can be seen as operating in two phases. In the beginning the WNR has data to send to the XNR and the XNR has configuration commands to send to WNR. During this phase the protocol efficiency is maximum and is given by (5)

Steady state is reached when the initial configuration is complete and the XNR has very few commands for the WNR. During this phase, the efficiency of protocol can be given by  = TD /TN2 ≈ 97%

(6)

and is valid when there are no errors during transmission. Let the probability of error because of a CRC failure or lost packet be denoted by Pe . If T is the amount of time taken to successfully transmit a packet and receive its acknowledgment in the presence of errors, then the average time it takes to successfully transmit a packet in presence of errors, E, is given by E[T ] = TN2 (1 + Pe /(1 − Pe ))

During steady state, in the absence of any errors, the data throughput of the compressed coefficients can be given as WNR throughput = No. of data bits/Total bits × Tx. rate = 800/(818 + 25) × 1 Mbps ≈ 950 Kbps

6.2. Communication protocol efficiency

 = (TD + TC )/TN2 ≈ 1

Fig. 12. Part of the 32 neural signals received and reconstructed by the XNR, at a compression ratio of 40, in comparison to the original signal acquired by the WNR. The amplitude in the y axis is a unitless 10 bit digital code.

(7)

(8)

Thus, a 1 Mbps channel can transfer data generated at rates less than 950 Kbps. However, as with other protocols, if successive packets result in failed CRCs or are lost, then multiple retransmissions may be required for each packet. If at the same time there is a burst of activity in the neurons, then this may result in data being generated at a higher rate than the throughput of the channel, raising the possibility of a buffer overflow and thus data loss at the WNR. To test the functionality and integrity of the communication block design, 32 channels of neural spike trains were simulated and sampled at 26 KS/s per channel. Each channel contained spikes at a high firing rate of 90 spikes/second which were multiplexed into a single stream and provided to the compression engine. The communication block was implemented in Matlab and tested in both the monitor and compression modes. The monitor mode resulted in an exact reconstruction of the original signal. For compression mode, Fig. 12 shows a comparison of the original signal with a signal reconstructed by keeping only 2.5% of the coefficients, where each bit of compressed data represents 40 bits of raw signal. Despite some apparent signal loss, spikes are easily discriminated by observation from Fig. 12. To quantitatively measure the degree of discrimination, spike sorting would need

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Fig. 13. Histogram of time taken in milliseconds by the compressed neural data to completely fill each data packet. Fig. 14. Layout of complete neural signal processor in 0.13 ␮m CMOS technology.

to be performed, introducing potential distortion of results from feature extraction and classification. No data loss due to overflows was recorded during the transmission. The same thresholds were used for consistency across channels, resulting in similar quality of reconstruction for all channels. A histogram of the time taken for incoming neural data to completely fill each frame during the experiment is shown in Fig. 13. It can be seen that, on average, each packet was filled in about 4 ms. Corresponding to the highest level of activity in the neurons, the minimum time taken to fill a packet was recorded as 2.6 ms, which is greater than the minimum time of 1.7 ms (see Section 3.2) required to avoid transmission errors. However, in experiments using very low threshold values, packets were observed to fill faster than they can be transmitted, which is expected and demonstrates the need for setting thresholds that result in the greater data compression. Our ongoing work aims at raising the thresholds to their highest possible value to enable spike sorting to simultaneously take place (Kamboh et al., 2007). 6.3. FPGA verification and ASIC design After the compression and communication algorithms were tested in Matlab, the hardware for the complete NSP including the Compression Engine, the Communication Controller, and the Global Controller was designed in HDL using Verilog. In addition, the design of the prototype DWT block (see Section 6.1) was modified to include channel selectivity and dynamic frequency scaling to further improve power consumption. To test the design of NSP without the analog frontend and RF transceiver, the system was mapped onto an Altera Cyclone III FPGA. The FPGA was interfaced with a custom printed circuit board containing an analog frontend composed of discrete components including an analog multiplexer and an A/D converter controlled by signals from the analog frontend controller block on the FPGA. The time-multiplexed outputs from the analog board were received by the FPGA and processed according to configuration settings. The final signals could be observed at the output of the communication controller. The RF interface was replaced with a wired connection between the WNR-FPGA and a host computer data acquisition system acting as the XNR. The XNR-computer completed the necessary processing and generated the command packets which were finally received by the WNR-FPGA. The functionality of the WNR was extensively tested using recorded neural input signals. Testing this system fully verified proper operation of the NSP on the FPGA, even for situations that were ignored or not represented accurately by simulations. To determine area and power specifications, the FPGA functionally verified design was synthesized to a 0.13 ␮m CMOS process using Synopsys Design Vision. The layout shown in Fig. 14 was

created using Cadence Encounter and Virtuoso. Low-Vt standard cell libraries and low-Vt SRAM generators were used to minimize power consumption. The core of the NSP occupies 1.1 mm × 1.1 mm, and overall chip is 1.9 mm × 1.9 mm = 3.69 mm2 including the I/O and power pads. Simulation results on the core show 800 ␮W of power consumption with a 1.2 V supply, resulting in average power of 25 ␮W per channel at 26 KS/s sampling rate. Thus, the overall power density of the chip is 800 ␮W/3.69 mm2 = 0.22 mW/mm2 . These results clearly confirm that the signal processing and compression goals can easily be completed within implantation constraints. Table 1 compares the capabilities of this system with other systems reported in the literature. The types of signal processing employed on-chip, the contents of transmitted signal, as well as data error detection capability are shown. The architectures in Sodagar et al. (2009), Nurmikko et al. (2010) use comparison with a threshold to determine the arrival of a spike. If a spike is present then a ‘1 is transmitted, otherwise a ‘0 is transmitted. As a result the transmitted data contains information regarding the spike arrival time in various channels. The systems presented in Gosselin et al. (2009), Rizk et al. (2009) maintain a high level of waveform integrity by storing the complete spike into data buffers whenever a spike is detected on a channel. The data in the buffer is then transmitted to the external units. This information is enough for spike sorting, however system performance is limited by the performance of the spike detector; any information in the neural signal between detected spikes would be lost. Furthermore, lowering the threshold to improve performance increases the chances of an overflow if the bandwidth is not sufficient, especially when the electrodes see a heightened neural spiking activity. The solutions presented in Roham et al. (2009), Song et al. (2009), Lee et al. (2010), Wattanapanitch and Sarpeshkar (2011), Gao et al. (2012), Lopez et al. (2012), Biederman et al. (2013), Yin et al. (2013) do not process the data at all; after multi-channel analog-to-digital conversion, the data is packed and transmitted without any compression. This sets bandwidth limitations for high number of channels and is not scalable with increasing electrode densities. Remarkably, the system in Moo-Sung et al. (2009) is reported to achieve 90 Mbps of data transfer between the implant and the external module, which is a magnitude greater than any other published approach. This permits the reported capture and transmission of uncompressed data from 128 channels simultaneously in a laboratory environment, although no in vivo tests have been reported. If the compression methods presented in this paper were adapted to the 90 Mbps link presented in Moo-Sung et al. (2009), it is estimated that up to 640 channels could be transmitted simultaneously based on system power and area budgets.

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Table 1 Comparison of reported multi channel neural recording systems. Waveform integrity for multi-channel recording

Transceiver data rate (Mbps)

In vivo tested

Spike reconstruct able

Transmitted signal

Type of processing

Data error detection

Sodagar et al. 64 (2009) Harrison et al. 100 (2009) Song et al. 16 (2009) Rizk et al. 96 (2009) Roham et al. 4 (2009) Gosselin et al. 16 (2009) Moo-Sung et al. 128 (2009)

Rudimentary

2

Yes

No

One or zero

Spike detection

No

Rudimentary

0.016

Yes

No

One or zero

Spike detection

No

Complete

NA

Yes

Yes

Raw data

No processing

No

High

1

Yes

Yes

Raw data

Spike detection

No

Complete

NA

Yes

Yes

Raw data

No processing

No

High

1.06

No

Yes

Raw data

Spike detection

No

Complete

90

No

Yes

Raw data, features

No

Karkare et al. (2011)

64

Rudimentary

1.02

No

No

Features

This work

32

Adjustable: rudimentary to complete

1

No

Yes

Compressed coefficients

No processing/feature extraction for 1 channel Spike detection + feature extraction Multi-channel DWT + RLE

References

No of channels

In contrast to reported approaches, our system allows an adjustable amount of waveform integrity by applying lossy compression in the form of multi-channel DWT, followed by lossless compression in the form of RLE. The thresholds for wavelet coefficients can be adjusted to change the quality of reconstruction achieved at the receiver. As shown in Table 1, none of current neural recording systems implement a communication protocol for error free data transmission. Our system accounts for data transmission error due to inductive power interference and data packet loss. This scalable architecture has the most complex on-chip signal processing of all the reported approaches, giving the highest level of application flexibility, signal compression and fidelity in multi-channel recordings, while still being suitable for realization within an implanted device. 7. Conclusion A custom neural signal processor was presented that enables compression and wireless communication of multi-channel neural data within the constraints of an implant. Detailed design and analysis were presented for the neural signal processor, which is composed of a neural compression engine, a global controller, and a communication controller. The compression engine realizes real-time DWT, programmable multi-level thresholding, and run length encoding to implement lossy and lossless compression that maintains spike shape information while minimizing transmission bandwidth. A packet structure and protocol tailored to error-free low-power communication in wireless neural implants was defined. The overall neural signal processor was shown to enable 32-channel data to be wirelessly transmitted through a 1 Mbps RF link, virtually error free, with highly configurable operation that permits many options for addressing, in real time, the tradeoff between signal fidelity, bandwidth, and power consumption. The design was thoroughly analyzed through a combination of simulations and testing of prototype CMOS implementations of critical blocks. A 32-channel prototype implementation of the neural signal processor fully verified on an FPGA and then mapped to 0.13 ␮m CMOS, where it occupies only 1.21 mm2 and consumes approximately 800 ␮W from a 1.2 V supply. This work demonstrates that high compression ratios for neural data can be obtained from a very area-power efficient implantable CMOS circuit that

No

Yes

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