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IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10. Published in final edited form as:
IEEE EMBS Int Conf Biomed Health Inform. 2016 February ; 2016: 616–619. doi:10.1109/BHI. 2016.7455974.
An Auditory Nerve Stimulation Chip with Integrated AFE, Sound Processing, and Power Management for Fully Implantable Cochlear Implants Nijad Anabtawi, Intel Corporation, Chandler, AZ and the Department of Electrical Engineering, Arizona State University, Tempe, AZ
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Sabrina Freeman, and Department of Biomedical Engineering, Arizona State University, Tempe, AZ Rony Ferzli [Senior Member, IEEE] Department of Electrical Engineering, Arizona State University, Tempe, AZ
Abstract
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This paper presents a system on chip for a fully implantable cochlear implant. It includes acoustic sensor front-end, 4-channel digital sound processing and auditory nerve stimulation circuitry. It also features a digital, switched mode, single inductor dual output power supply that generates two regulated voltages; 0.4 V used to supply on-chip digital blocks and 0.9 V to supply analog blocks and charge the battery when an external RF source is detected. All passives are integrated on-chip including the inductor. The system was implemented in 14nm CMOS and validated with post layout simulations.
I. Introduction
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According to latest estimates, over 5% of the world’s population suffers from disabling hearing loss [1]. While moderate loss can be remedied with a hearing aid, cochlear implants (CI) are necessary to restore hearing to individuals with severe (> 80 dB) loss. Commercially available CIs use a battery powered external unit housing a microphone, sound processor, and transmitter to pick, digitize, and wirelessly transmit sound and power to a passive implant surgically inserted in the skull. When powered by the external unit, the implant comprising a receiver, stimulator and electrode array connected to the cochlea sources electrical pulses that excite the auditory nerve leading to sound perception in the brain. Reliance on the external active unit for power and data limits the wearer’s activities and is socially stigmatizing. Hence a fully implantable (invisible) cochlear implant (FICI) is preferred. To realize FICIs, sensor front-end, processing, neural stimulation and power management need to be integrated on a single die that interfaces with an implantable acoustic sensor and battery (Fig. 1). Prior implantable acoustic sensors were accelerometer based with restrictive power requirements and limited sensitivity [2], piezoelectric transduction offers better integration and space saving potential [3]. Fig. 2 demonstrates the FEM generated transfer characteristics of a middle ear (umbo) mounted piezoelectric
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acoustic sensor connected to a charge amplifier. Output voltage (VPZ) shows flat response up to 7 kHz which is more than adequate for speech. This paper presents an SoC for a FICI. Combined with an off-chip middle ear acoustic sensor, the SoC processes the sensor’s output and stimulates the auditory nerve accordingly to restore hearing. It also includes an on-chip power management and charging unit to extend battery run-time before charging. The paper is organized as follows; section II describes the proposed architecture whereas implementation is provided in section III. Transistor level simulations are presented in section IV, and finally conclusions in section V.
II. SYSTEM LEVEL ARCHITECTURE
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A block diagram of the proposed system is shown in Fig. 3. The sensor front-end (PSFE) conditions the acoustic sensor’s output voltage (which is proportional to the sound pressure induced displacement of the umbo) and relays it to the ultra-low power 10 bit frequency discriminator based A/D. The A/D’s output is processed by the 4 channel digital, continuous interleaved sampling (CIS) sound processor which generates 6-bit output codes at a 1 kHz rate. These are used to control the neural stimulator which is composed of an H-bridge electrode switch matrix, a 6-bit, D/A based current source and channel selector. The current source is interleaved among the electrodes at a rate of 1 kHz. The DC-DC switch mode power supple (SMPS) is a single inductor dual output all-digital regulator. It generates 0.9 V analog and 0.4 V digital supplies with high conversion efficiency. The 0.9 V supply is also used to charge an implanted battery when an RF transmitter is detected. To facilitate integration, the inductor (L) is realized on chip using top metal windings.
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III. IMPLEMENTATION A. Sensor Front-End and A/D
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Detailed implementation of the PSFE is provided in Fig. 3. It is composed of a charge amplifier followed by a tunable gain stage and filter. 1st stage gain = CP/C1f, where CP is the sensor’s equivalent capacitance. To accommodate different sensor output voltage ranges (for different sensor sizes), variable passives are used. The output of the second stage is used to control a voltage controlled oscillator (VCO). A ΣΔ frequency Discriminators (ΣΔFDC) is used to implement the A/D. This 1st order, digital, none feedback modulator, process the frequency modulated (FM) signal from the VCO to produce a single bit output stream [4]. Compared to conventional Nyquist rate A/D architectures, ΣΔFDC has a simpler circuit, is more power efficient and inherently linear by virtue of using a single bit comparator. Schematic of the ΣΔFDC is shown in Fig. 4. It consists of a 0.9 V current-starved VCO, two D flip flops and one XOR gate. Decimation of ΣΔFDC output is implemented using cascaded-integrator-comb (CIC) filter to generate a 10 bit code word. B. Sound Processing Based on the finding from [5], it was shown that good speech recognition using CI improved substantially as the number of sound spectral channels increased from 1 – 4 with little difference above 7, hence 4 spectral channels were used in this proof of concept. Fig. 5 demonstrates a block diagram of the realized sound processor, it is an implementation of the IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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widely used CIS architecture [6]. To reduce area and power requirements, digital multi-rate processing is utilized. Log-spaced channels are implemented using FIR filters with cut-off frequencies derived from [5]. The filters spectrally decompose the incoming sound signal in a tonotopic fashion similar to natural hearing. The envelope of the output signal of the individual filters is extracted before being down-sampled and log- compressed so as to condition the separate channels’ signals to fall within the electric dynamic range of natural hearing of the human ear. C. Power Management
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Fig. 6 illustrates the power management unit used in this work. It is a switched mode single inductor, dual output regulator [7]. Two error signals VERR1 and VERR2 are generated from the regulated output voltages VOUT1 (digital) and VOUT2 (analog) respectively and are compared using the comparator (Comp). The higher of the two signals is then passed through (signal select) to the PID controller. Instead of using a conventional pulse width (PWM) or pulse code (PCM) modulator to drive the power stage, a 4th order ΣΔ modulator (Fig. 6) is used to suppress spurious noise. The comparator’s decision controls operation of S3 and S4. If VERR1 > VERR2, S3 is closed, S4 is open and vice versa. This allows the loop to regulate two output voltages by tracking two error signals and adjusting on/off times for S3 and S4. Blocks D1 and D2 digitize the output voltages VOUT1 and VOUT2 using 1st order ΣΔFDCs similar to the one used to digitize the sensor’s output. To generate the error signals VERR1 and VERR2, digital representation of VOUT1 and VOUT2 is subtracted from the digitized references VREF1 and VREF2. The dead time generator prevents shoot-through current in the power stage switchers. Fig. 7 illustrates the digital 4th order ΣΔ modulator digital implementation.
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IV. Simulation Results
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The proposed work was implemented in 14nm digital CMOS process and validated with post layout simulations. Fig. 8 demonstrates the gain of the sensor front end for different gain settings. Fig. 9a presents the simulated transient electrode voltage during switch matrix activity. The electrodes’ loading were modeled using an RC network (R = 3kΩ, C = 10nF). Fig. 9b presents the corresponding 4 channel interleaved electrode current pulses at a 1000 pulse/sec rate. Fig. 10a and Fig. 10b present the input signal and spectrogram of the test phrase (“testing one two three testing”). Fig. 10c and Fig. 10d present the simulated reconstructed output signal and spectrogram respectively. The sound pressure levels generated from the input test phrase as well as the piezoelectric acoustic sensor’s output voltage were extracted using a Matlab, Comsol FEM co-simulation. The generated output voltage was them ported to Cadence for post layout analysis. Although the output signals exhibits some non-idealities such as bandwidth limitation and amplitude reduction (attributed to the sound processor and PSFE frequency response limitations) it demonstrates that the system successfully preserves input speech signal characteristics and envelop. Finally, key system metrics are provided in Table 1. Layout of the proposed SoC is provided in Fig. 11.
IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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V. Conclusion A SoC for a fully implantable cochlear implant was presented. It includes acoustic sensor front-end, sound processing, nerve stimulation and power management circuitry. All passives are integrated on-chip including the inductor. The system was implemented in 14nm CMOS and validated with post layout simulations.
References
Author Manuscript
1. WHO global estimates on prevalence of hearing loss. 2012. [online]. http://www.who.int/pbd/ deafness/WHO_GE_HL.pdf 2. Young DJ, Zurcher MA, Semaan M, Megerian CA, Ko WH. MEMS capacitive accelerometer-based middle ear microphone. IEEE Trans Biomed Eng. Dec; 2012 59(12):3283–3292. [PubMed: 22542650] 3. Charthad, J., Weber, MJ., Chang, Ting Chia, Saadat, M., Arbabian, A. A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applications. Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the; 15–17 Sept. 2014; p. 1-4. 4. Wismar, U., Wisland, D., Andreani, P. A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS. Solid State Circuits Conference, 2007 ESSCIRC 2007 33rd European; 11–13 Sept. 2007; p. 206-209. 5. Faulkner A, Rosen S, Wilkinson L. Effects of the number of channels and speech-to-noise ratio on rate of connected discourse tracking through a simulated cochlear implant speech processor. Ear & Hearing. Oct; 2001 22(5):431–438. [PubMed: 11605950] 6. Wilson BS, Finley CC, Lawson DT, Wolford RD, Eddington DK, Rabinowitz WM. Better speech recognition with cochlear implants. Letters to Nature. Jul.1991 352:236–238. 7. Anabtawi, N., Ferzli, R. A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controller. Quality Electronic Design (ISQED), 2015 16th International Symposium on; 2–4 March 2015; p. 82-85.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript Fig 1.
Fully-implantable cochlear implant block diagram.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 2.
Transfer characteristics (a) from umbo velocity (vUMBO) to the charge amplifer output voltage (VPZ), and (b) from ear canal pressure (PEC) to VPZ.
Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript Fig 3.
System level architecture of the fully-implantable cochlear implant IC.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 4.
ΣΔ frequency discriminator analog to digital converter.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 5.
Continuous interleaved sampling sound processor block diagram.
Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 6.
System level diagram for the dual output switched mode power regulator.
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Fig 7.
4th Order digital sigma delta implementation.
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Fig 8.
Extracted layout gain of analog front end stages 1 and 2.
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Author Manuscript Author Manuscript Fig 9.
Electrode (a) voltage and (b) current waveforms.
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Fig 10.
Amplitude and spectrogram of (a,b) input and (c,d) output signals.
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Author Manuscript Author Manuscript Fig 11.
Layout of the SoC (base layers). Inductor windings (24nH) on top metal layers are not visible.
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Table 1
Author Manuscript
System Summary Process
14nm CMOS
Input Unregulated Supply (V)
1.0 – 3.3
Output Dual Supply Ranges (V)
0.2 – 1.0
Total Power Consumption (W)
Charging Enabled: 30m Charging Disabled (CI Only): 127μ - PSFE: 5.5μ - ΣΔFDC: 50n - 4 Channel Sound Processor: 120n - 4 Channel Stimulator:110μ - SMPS (Loop Controller): 11μ
SMPS Peak Efficiency (%)
92
Author Manuscript Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10. Published in final edited form as:
IEEE EMBS Int Conf Biomed Health Inform. 2016 February ; 2016: 616–619. doi:10.1109/BHI. 2016.7455974.
An Auditory Nerve Stimulation Chip with Integrated AFE, Sound Processing, and Power Management for Fully Implantable Cochlear Implants Nijad Anabtawi, Intel Corporation, Chandler, AZ and the Department of Electrical Engineering, Arizona State University, Tempe, AZ
Author Manuscript
Sabrina Freeman, and Department of Biomedical Engineering, Arizona State University, Tempe, AZ Rony Ferzli [Senior Member, IEEE] Department of Electrical Engineering, Arizona State University, Tempe, AZ
Abstract
Author Manuscript
This paper presents a system on chip for a fully implantable cochlear implant. It includes acoustic sensor front-end, 4-channel digital sound processing and auditory nerve stimulation circuitry. It also features a digital, switched mode, single inductor dual output power supply that generates two regulated voltages; 0.4 V used to supply on-chip digital blocks and 0.9 V to supply analog blocks and charge the battery when an external RF source is detected. All passives are integrated on-chip including the inductor. The system was implemented in 14nm CMOS and validated with post layout simulations.
I. Introduction
Author Manuscript
According to latest estimates, over 5% of the world’s population suffers from disabling hearing loss [1]. While moderate loss can be remedied with a hearing aid, cochlear implants (CI) are necessary to restore hearing to individuals with severe (> 80 dB) loss. Commercially available CIs use a battery powered external unit housing a microphone, sound processor, and transmitter to pick, digitize, and wirelessly transmit sound and power to a passive implant surgically inserted in the skull. When powered by the external unit, the implant comprising a receiver, stimulator and electrode array connected to the cochlea sources electrical pulses that excite the auditory nerve leading to sound perception in the brain. Reliance on the external active unit for power and data limits the wearer’s activities and is socially stigmatizing. Hence a fully implantable (invisible) cochlear implant (FICI) is preferred. To realize FICIs, sensor front-end, processing, neural stimulation and power management need to be integrated on a single die that interfaces with an implantable acoustic sensor and battery (Fig. 1). Prior implantable acoustic sensors were accelerometer based with restrictive power requirements and limited sensitivity [2], piezoelectric transduction offers better integration and space saving potential [3]. Fig. 2 demonstrates the FEM generated transfer characteristics of a middle ear (umbo) mounted piezoelectric
Anabtawi et al.
Page 2
Author Manuscript
acoustic sensor connected to a charge amplifier. Output voltage (VPZ) shows flat response up to 7 kHz which is more than adequate for speech. This paper presents an SoC for a FICI. Combined with an off-chip middle ear acoustic sensor, the SoC processes the sensor’s output and stimulates the auditory nerve accordingly to restore hearing. It also includes an on-chip power management and charging unit to extend battery run-time before charging. The paper is organized as follows; section II describes the proposed architecture whereas implementation is provided in section III. Transistor level simulations are presented in section IV, and finally conclusions in section V.
II. SYSTEM LEVEL ARCHITECTURE
Author Manuscript
A block diagram of the proposed system is shown in Fig. 3. The sensor front-end (PSFE) conditions the acoustic sensor’s output voltage (which is proportional to the sound pressure induced displacement of the umbo) and relays it to the ultra-low power 10 bit frequency discriminator based A/D. The A/D’s output is processed by the 4 channel digital, continuous interleaved sampling (CIS) sound processor which generates 6-bit output codes at a 1 kHz rate. These are used to control the neural stimulator which is composed of an H-bridge electrode switch matrix, a 6-bit, D/A based current source and channel selector. The current source is interleaved among the electrodes at a rate of 1 kHz. The DC-DC switch mode power supple (SMPS) is a single inductor dual output all-digital regulator. It generates 0.9 V analog and 0.4 V digital supplies with high conversion efficiency. The 0.9 V supply is also used to charge an implanted battery when an RF transmitter is detected. To facilitate integration, the inductor (L) is realized on chip using top metal windings.
Author Manuscript
III. IMPLEMENTATION A. Sensor Front-End and A/D
Author Manuscript
Detailed implementation of the PSFE is provided in Fig. 3. It is composed of a charge amplifier followed by a tunable gain stage and filter. 1st stage gain = CP/C1f, where CP is the sensor’s equivalent capacitance. To accommodate different sensor output voltage ranges (for different sensor sizes), variable passives are used. The output of the second stage is used to control a voltage controlled oscillator (VCO). A ΣΔ frequency Discriminators (ΣΔFDC) is used to implement the A/D. This 1st order, digital, none feedback modulator, process the frequency modulated (FM) signal from the VCO to produce a single bit output stream [4]. Compared to conventional Nyquist rate A/D architectures, ΣΔFDC has a simpler circuit, is more power efficient and inherently linear by virtue of using a single bit comparator. Schematic of the ΣΔFDC is shown in Fig. 4. It consists of a 0.9 V current-starved VCO, two D flip flops and one XOR gate. Decimation of ΣΔFDC output is implemented using cascaded-integrator-comb (CIC) filter to generate a 10 bit code word. B. Sound Processing Based on the finding from [5], it was shown that good speech recognition using CI improved substantially as the number of sound spectral channels increased from 1 – 4 with little difference above 7, hence 4 spectral channels were used in this proof of concept. Fig. 5 demonstrates a block diagram of the realized sound processor, it is an implementation of the IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
Page 3
Author Manuscript
widely used CIS architecture [6]. To reduce area and power requirements, digital multi-rate processing is utilized. Log-spaced channels are implemented using FIR filters with cut-off frequencies derived from [5]. The filters spectrally decompose the incoming sound signal in a tonotopic fashion similar to natural hearing. The envelope of the output signal of the individual filters is extracted before being down-sampled and log- compressed so as to condition the separate channels’ signals to fall within the electric dynamic range of natural hearing of the human ear. C. Power Management
Author Manuscript
Fig. 6 illustrates the power management unit used in this work. It is a switched mode single inductor, dual output regulator [7]. Two error signals VERR1 and VERR2 are generated from the regulated output voltages VOUT1 (digital) and VOUT2 (analog) respectively and are compared using the comparator (Comp). The higher of the two signals is then passed through (signal select) to the PID controller. Instead of using a conventional pulse width (PWM) or pulse code (PCM) modulator to drive the power stage, a 4th order ΣΔ modulator (Fig. 6) is used to suppress spurious noise. The comparator’s decision controls operation of S3 and S4. If VERR1 > VERR2, S3 is closed, S4 is open and vice versa. This allows the loop to regulate two output voltages by tracking two error signals and adjusting on/off times for S3 and S4. Blocks D1 and D2 digitize the output voltages VOUT1 and VOUT2 using 1st order ΣΔFDCs similar to the one used to digitize the sensor’s output. To generate the error signals VERR1 and VERR2, digital representation of VOUT1 and VOUT2 is subtracted from the digitized references VREF1 and VREF2. The dead time generator prevents shoot-through current in the power stage switchers. Fig. 7 illustrates the digital 4th order ΣΔ modulator digital implementation.
Author Manuscript
IV. Simulation Results
Author Manuscript
The proposed work was implemented in 14nm digital CMOS process and validated with post layout simulations. Fig. 8 demonstrates the gain of the sensor front end for different gain settings. Fig. 9a presents the simulated transient electrode voltage during switch matrix activity. The electrodes’ loading were modeled using an RC network (R = 3kΩ, C = 10nF). Fig. 9b presents the corresponding 4 channel interleaved electrode current pulses at a 1000 pulse/sec rate. Fig. 10a and Fig. 10b present the input signal and spectrogram of the test phrase (“testing one two three testing”). Fig. 10c and Fig. 10d present the simulated reconstructed output signal and spectrogram respectively. The sound pressure levels generated from the input test phrase as well as the piezoelectric acoustic sensor’s output voltage were extracted using a Matlab, Comsol FEM co-simulation. The generated output voltage was them ported to Cadence for post layout analysis. Although the output signals exhibits some non-idealities such as bandwidth limitation and amplitude reduction (attributed to the sound processor and PSFE frequency response limitations) it demonstrates that the system successfully preserves input speech signal characteristics and envelop. Finally, key system metrics are provided in Table 1. Layout of the proposed SoC is provided in Fig. 11.
IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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V. Conclusion A SoC for a fully implantable cochlear implant was presented. It includes acoustic sensor front-end, sound processing, nerve stimulation and power management circuitry. All passives are integrated on-chip including the inductor. The system was implemented in 14nm CMOS and validated with post layout simulations.
References
Author Manuscript
1. WHO global estimates on prevalence of hearing loss. 2012. [online]. http://www.who.int/pbd/ deafness/WHO_GE_HL.pdf 2. Young DJ, Zurcher MA, Semaan M, Megerian CA, Ko WH. MEMS capacitive accelerometer-based middle ear microphone. IEEE Trans Biomed Eng. Dec; 2012 59(12):3283–3292. [PubMed: 22542650] 3. Charthad, J., Weber, MJ., Chang, Ting Chia, Saadat, M., Arbabian, A. A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applications. Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the; 15–17 Sept. 2014; p. 1-4. 4. Wismar, U., Wisland, D., Andreani, P. A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS. Solid State Circuits Conference, 2007 ESSCIRC 2007 33rd European; 11–13 Sept. 2007; p. 206-209. 5. Faulkner A, Rosen S, Wilkinson L. Effects of the number of channels and speech-to-noise ratio on rate of connected discourse tracking through a simulated cochlear implant speech processor. Ear & Hearing. Oct; 2001 22(5):431–438. [PubMed: 11605950] 6. Wilson BS, Finley CC, Lawson DT, Wolford RD, Eddington DK, Rabinowitz WM. Better speech recognition with cochlear implants. Letters to Nature. Jul.1991 352:236–238. 7. Anabtawi, N., Ferzli, R. A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controller. Quality Electronic Design (ISQED), 2015 16th International Symposium on; 2–4 March 2015; p. 82-85.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript Fig 1.
Fully-implantable cochlear implant block diagram.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 2.
Transfer characteristics (a) from umbo velocity (vUMBO) to the charge amplifer output voltage (VPZ), and (b) from ear canal pressure (PEC) to VPZ.
Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript Fig 3.
System level architecture of the fully-implantable cochlear implant IC.
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Fig 4.
ΣΔ frequency discriminator analog to digital converter.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
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Fig 5.
Continuous interleaved sampling sound processor block diagram.
Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript
Fig 6.
System level diagram for the dual output switched mode power regulator.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Fig 7.
4th Order digital sigma delta implementation.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
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Author Manuscript Author Manuscript
Fig 8.
Extracted layout gain of analog front end stages 1 and 2.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
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Author Manuscript Author Manuscript Fig 9.
Electrode (a) voltage and (b) current waveforms.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
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Author Manuscript Author Manuscript Author Manuscript
Fig 10.
Amplitude and spectrogram of (a,b) input and (c,d) output signals.
Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
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Author Manuscript Author Manuscript Fig 11.
Layout of the SoC (base layers). Inductor windings (24nH) on top metal layers are not visible.
Author Manuscript Author Manuscript IEEE EMBS Int Conf Biomed Health Inform. Author manuscript; available in PMC 2017 July 10.
Anabtawi et al.
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Table 1
Author Manuscript
System Summary Process
14nm CMOS
Input Unregulated Supply (V)
1.0 – 3.3
Output Dual Supply Ranges (V)
0.2 – 1.0
Total Power Consumption (W)
Charging Enabled: 30m Charging Disabled (CI Only): 127μ - PSFE: 5.5μ - ΣΔFDC: 50n - 4 Channel Sound Processor: 120n - 4 Channel Stimulator:110μ - SMPS (Loop Controller): 11μ
SMPS Peak Efficiency (%)
92
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