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Critical Factors to Achieve Low Voltage- and CapacitanceBased Organic Field-Effect Transistors Mi Jang, Ji Hoon Park, Seongil Im,* Se Hyun Kim,* and Hoichang Yang*
Remarkable advances in organic field-effect transistors (OFETs) have achieved in both academia and industry, and OFETs are now being applied in emerging technologies, such as flexible displays, sensors, and radio frequency identification (RFID) tags.[1–3] However, OFETs, as components of commercial products, require a reliable operation at low voltages for prolonged periods of time. In general, many localized traps are present in organic semiconducting films and at the dielectric interface due to polycrystalline defects in the organic semiconductors and polar dielectric functionalities.[4,5] In this case, compensatory free carriers need to fill these traps, which cause high values of subthreshold swing (SS) and large deviations of the threshold voltage (Vth) from a zero gate bias during device operation.[6,7] Among the many efforts to reduce Vth and SS up to an acceptable level, many studies have focused on high capacitance (Ci) structures with high dielectric constant (k) or a thin dielectric film.[6,7] For example, high-k polymer or organic/inorganic hybrid dielectrics have enabled OFETs to be operated at potential biases 20 V). TES-ADT could be tuned intrinsically with better π-conjugated structures to transfer the charge-carriers, as determined by atomic force microscopy (AFM), X-ray diffraction, and in situ photo-excited charge-collection spectroscopy (PECCS). Figure 1a shows a schematic diagram of the top-contact electrode OFETs on 300 nm-thick SiO2 dielectrics pretreated with the uppermost polymeric layer. First, dimethylchlorosilaneterminated polystyrene (PS-Si(CH3)2Cl, bPS-) could be grafted directly to the UV-O3-treated SiO2 dielectrics by (1) solutioncasting, (2) subsequent annealing at 100 °C for 1 hour, and (3) rinsing with excess toluene.[12] In addition, the other two polymer layers were introduced to SiO2 dielectrics, as reported elsewhere.[7,8] All the polymer-assisted SiO2 layers with approximately Ci ∼ 10 nF cm−2 (at 1 kHz) showed hydrophobic and smooth surfaces that were comparable to the hydrophilic SiO2 surfaces with a surface roughness of ∼0.2 nm. Finally, 50 nmthick TES-ADT and pentacene films were fabricated on these polymer-assisted SiO2 bilayer dielectrics, respectively. At |V| ≤ 5 V, all the TES-ADT OFETs could be worked with a negligible VG-sweep hysteresis (see Figure 1b). On the bPS-SiO2 dielectrics, the TES-ADT OFETs showed successful operation at < ±2.5 V, and exhibited μFET, Vth, and SS values up to 1.3 cm2 V−1 s−1, −0.5V, and ∼0.2 V decade−1, respectively. The outstanding device performance was comparable to (or superior to) those of OFETs including high-Ci dielectrics >100 nFcm−2.[2,7,8,12] In contrast, the pentacene OFETs required much higher voltages to achieve on-current above 1 μA. I−V transfer measurements were performed under series of drain voltages (VD) indicating a saturation regime to determine the discernible device characteristics and reliability of the TES-ADT and pentacene OFETs on the bPS-SiO2 dielectrics. The TES-ADT OFETs showed good linearity between the root square of the source-drain current (-IDS)1/2 and VG within the entire operating voltage range, producing consistent μFET values, 1.3−1.6 cm2 V−1 s−1. In addition, the turn-on voltage (Vturn-on) and Vth, were 0.5 V and −0.5 V, respectively. In contrast, the non-linear (-IDS)1/2-VG relationship of pentacene OFETs, particularly below |V| = 20 V, revealed a large negative shift of Vth from zero gate bias, even though the devices turned on constantly at −2 V (see Figure 2c). In this case, the SS and Vth values were 2.2 Vdecade−1 and approximately −15 V, respectively.
© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, 26, 288–292
www.advmat.de www.MaterialsViews.com
bPS
-IDS (A)
10-6
VD = -2.5V
N RO
+
n
VD = -5.0V
10-11
n
N N
10-10
O
N
PMFA
10-12 O
PVP
PDMSS-PMFA 10-6
N
(c)
10-7
10-7
10-7
10-8
10-8
10-8
VD = -5.0V
10-9 10-10 10-12
10-11
10-11
10-11
10-13
-3 -2 -1 0 1 2 3
VG (V)
-6 -4 -2 0 2 4 6
VG (V)
10-11
VG (V)
Figure 1. (a) Schematic diagram of the TES-ADT and pentacene OFETs fabricated on various organic layer-coated SiO2 dielectrics; (b) IDS-VG transfer curves of TES-ADT OFETs on bPS-SiO2, PDMSS-PMFA/SiO2, and PVP-PMFA/SiO2 dielectrics, respectively.
The resulting μFET values of the pentacene OFETs increased up to 0.9 cm2 V−1 s−1 with increasing |V| (see Figure 2d). In most OFETs, the delayed generation in the charge transport channel is related mainly to the traps in the semiconductor localized near the dielectrics and/or semiconductor-dielectric interface (which intrinsically contains a range of defects and unwanted impurities).[4,12] As shown in Figure 2b and 2d, the μFET values of the TES-ADT OFETs on the bPS-SiO2 dielectrics tended to plateau with increasing |V| (> |Vth|, marked with a red line), whereas those of the pentacene-based devices on the same dielectrics increased monotonically with increasing |V| ranging from 5 V to 50 V. Clear evidence for the limited charge transport in pentacene OFETs is given by the fact that the electrical performance of each device is strongly dependent on the semiconductor film structures on the bPS-SiO2 dielectrics, such as crystallinity, grain boundaries (GBs), and π-conjugated molecular packing. As shown in Figure 3a–d, the pentacene and TES-ADT films showed significantly different crystal structures. When pentacene was evaporated onto a hydrophobic and flat substrate (surface roughness
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www.MaterialsViews.com
Critical Factors to Achieve Low Voltage- and CapacitanceBased Organic Field-Effect Transistors Mi Jang, Ji Hoon Park, Seongil Im,* Se Hyun Kim,* and Hoichang Yang*
Remarkable advances in organic field-effect transistors (OFETs) have achieved in both academia and industry, and OFETs are now being applied in emerging technologies, such as flexible displays, sensors, and radio frequency identification (RFID) tags.[1–3] However, OFETs, as components of commercial products, require a reliable operation at low voltages for prolonged periods of time. In general, many localized traps are present in organic semiconducting films and at the dielectric interface due to polycrystalline defects in the organic semiconductors and polar dielectric functionalities.[4,5] In this case, compensatory free carriers need to fill these traps, which cause high values of subthreshold swing (SS) and large deviations of the threshold voltage (Vth) from a zero gate bias during device operation.[6,7] Among the many efforts to reduce Vth and SS up to an acceptable level, many studies have focused on high capacitance (Ci) structures with high dielectric constant (k) or a thin dielectric film.[6,7] For example, high-k polymer or organic/inorganic hybrid dielectrics have enabled OFETs to be operated at potential biases 20 V). TES-ADT could be tuned intrinsically with better π-conjugated structures to transfer the charge-carriers, as determined by atomic force microscopy (AFM), X-ray diffraction, and in situ photo-excited charge-collection spectroscopy (PECCS). Figure 1a shows a schematic diagram of the top-contact electrode OFETs on 300 nm-thick SiO2 dielectrics pretreated with the uppermost polymeric layer. First, dimethylchlorosilaneterminated polystyrene (PS-Si(CH3)2Cl, bPS-) could be grafted directly to the UV-O3-treated SiO2 dielectrics by (1) solutioncasting, (2) subsequent annealing at 100 °C for 1 hour, and (3) rinsing with excess toluene.[12] In addition, the other two polymer layers were introduced to SiO2 dielectrics, as reported elsewhere.[7,8] All the polymer-assisted SiO2 layers with approximately Ci ∼ 10 nF cm−2 (at 1 kHz) showed hydrophobic and smooth surfaces that were comparable to the hydrophilic SiO2 surfaces with a surface roughness of ∼0.2 nm. Finally, 50 nmthick TES-ADT and pentacene films were fabricated on these polymer-assisted SiO2 bilayer dielectrics, respectively. At |V| ≤ 5 V, all the TES-ADT OFETs could be worked with a negligible VG-sweep hysteresis (see Figure 1b). On the bPS-SiO2 dielectrics, the TES-ADT OFETs showed successful operation at < ±2.5 V, and exhibited μFET, Vth, and SS values up to 1.3 cm2 V−1 s−1, −0.5V, and ∼0.2 V decade−1, respectively. The outstanding device performance was comparable to (or superior to) those of OFETs including high-Ci dielectrics >100 nFcm−2.[2,7,8,12] In contrast, the pentacene OFETs required much higher voltages to achieve on-current above 1 μA. I−V transfer measurements were performed under series of drain voltages (VD) indicating a saturation regime to determine the discernible device characteristics and reliability of the TES-ADT and pentacene OFETs on the bPS-SiO2 dielectrics. The TES-ADT OFETs showed good linearity between the root square of the source-drain current (-IDS)1/2 and VG within the entire operating voltage range, producing consistent μFET values, 1.3−1.6 cm2 V−1 s−1. In addition, the turn-on voltage (Vturn-on) and Vth, were 0.5 V and −0.5 V, respectively. In contrast, the non-linear (-IDS)1/2-VG relationship of pentacene OFETs, particularly below |V| = 20 V, revealed a large negative shift of Vth from zero gate bias, even though the devices turned on constantly at −2 V (see Figure 2c). In this case, the SS and Vth values were 2.2 Vdecade−1 and approximately −15 V, respectively.
© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, 26, 288–292
www.advmat.de www.MaterialsViews.com
bPS
-IDS (A)
10-6
VD = -2.5V
N RO
+
n
VD = -5.0V
10-11
n
N N
10-10
O
N
PMFA
10-12 O
PVP
PDMSS-PMFA 10-6
N
(c)
10-7
10-7
10-7
10-8
10-8
10-8
VD = -5.0V
10-9 10-10 10-12
10-11
10-11
10-11
10-13
-3 -2 -1 0 1 2 3
VG (V)
-6 -4 -2 0 2 4 6
VG (V)
10-11
VG (V)
Figure 1. (a) Schematic diagram of the TES-ADT and pentacene OFETs fabricated on various organic layer-coated SiO2 dielectrics; (b) IDS-VG transfer curves of TES-ADT OFETs on bPS-SiO2, PDMSS-PMFA/SiO2, and PVP-PMFA/SiO2 dielectrics, respectively.
The resulting μFET values of the pentacene OFETs increased up to 0.9 cm2 V−1 s−1 with increasing |V| (see Figure 2d). In most OFETs, the delayed generation in the charge transport channel is related mainly to the traps in the semiconductor localized near the dielectrics and/or semiconductor-dielectric interface (which intrinsically contains a range of defects and unwanted impurities).[4,12] As shown in Figure 2b and 2d, the μFET values of the TES-ADT OFETs on the bPS-SiO2 dielectrics tended to plateau with increasing |V| (> |Vth|, marked with a red line), whereas those of the pentacene-based devices on the same dielectrics increased monotonically with increasing |V| ranging from 5 V to 50 V. Clear evidence for the limited charge transport in pentacene OFETs is given by the fact that the electrical performance of each device is strongly dependent on the semiconductor film structures on the bPS-SiO2 dielectrics, such as crystallinity, grain boundaries (GBs), and π-conjugated molecular packing. As shown in Figure 3a–d, the pentacene and TES-ADT films showed significantly different crystal structures. When pentacene was evaporated onto a hydrophobic and flat substrate (surface roughness
