full papers Stretchable CNTs
Fabrication of Stretchable Single-Walled Carbon Nanotube Logic Devices Jangyeol Yoon, Gunchul Shin, Joonsung Kim, Young Sun Moon, Seung-Jung Lee, Goangseup Zi, and Jeong Sook Ha*
The
fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics.
1. Introduction There have been extentive research on the realization of electronic devices which are flexible, foldable, and stretchable but with performance comparable to that of conventional rigid electronics, due to the growing potential applications of future wearable systems to personal smart devices and
J. Yoon, G. Shin, J. Kim, Y. S. Moon, Prof. J. S. Ha Department of Chemical and Biological Engineering Korea University Seoul 136-701, Korea E-mail: [email protected] Prof. J. S. Ha KU-KIST Graduate School of Converging Science and Technology Korea University Seoul 136-701, Korea S.-J. Lee, Prof. G. Zi Department of Civil Environmental and Architectural Engineering Korea University Seoul 136-701, Korea DOI: 10.1002/smll.201303779
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bio-implantable electronics. Various kinds of stretchable logic devices using inorganic nano-ribbons as channel materials have been demonstrated.[1–4] Most of the previous stretchable electronics adopted the design concepts of mechanical neutral plane and curved/serpentine interconnects to reduce the strain applied to the active device area.[5–10] Using the same design concepts, stretchable logic device arrays of metal oxide nanowires were also reported.[11,12] In addition, alignd array of Si nanoribbon based devices on ultrathin elastomeric PDMS substrate, in multilayer mechanical neutral plane design and wavy structural layouts, showed stable device performance upon deformations including folding and stretching up to ∼10%,[13] which demonstrated a simple route to high performance, stretchable, and foldable integrated circuits. In the fabrication of electronic devices, amorphous silicon, poly-silicon, organic materials, metal-oxide nanowires, and single-walled carbon nanotubes (SWCNTs) have been explored as active channel materials.[14–23] Among them, SWCNTs exhibited excellent mechanical, thermal, chemical, optically transparent, and electronic properties.[24–26] In particular, SWCNT based electronic devices on rigid substrates have shown outstanding device performance even exceeding that of conventional devices using amorphous silicon, poly-silicon, or organic materials.[27–29] It is also
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Figure 1. Schematics of fabricating a stretchable CMOS inverter array consisting of CVD grown pristine p-SWCNTs and NADH- coated n-SWCNTs FETs.
advantageous that SWCNT based electronic devices can be fabricated at low temperatures. Owing to these superior properties of SWCNTs, complicated flexible logic circuits including inverter, NAND, NOR, and ring oscillator have been demonstrated so far.[22,30] However, semiconducting SWCNTs grown via chemical vapor deposition (CVD) generally exhibit p-type transfer properties. Thus, the type conversion of pristine SWCNTs into n-type has been one of the key challenges for the fabrication of various logic devices.[31] Coating of electron-donating poly(ethylenimine) onto the pristine SWCNTs was observed to induce n-type properties,[32] but it was not stable under humid ambient so that it recovered the intrinsic p-type properties within a few days.[33] In our previous work,[34] we could successfully fabricate the stable intra-tube junction diode via type-conversion of pristine SWCNTs by partial coating with β-nicotinamide adenine dinucleotide, reduced dipotassium salt (NADH), and subsequent annealing. Compared to the tremendous works on SWCNT based electronic devices, there have only been a few reports on SWCNT based stretchable devices. Even though an artificial electronic-skin using SWCNT thin film transistor active matrix was demonstrated,[35] most of the research on SWCNT based stretchable electronics showed the change of resistance with stretching in the highly conductive interconnections of randomly networked SWCNTs.[36–39] Recently, it was reported that SWCNT FETs were stable over the stretching between 5 and 20% by introducing the wrinkled Al2O3 gate dielectric layer.[40] However, it will be more useful to have higher mechanical stability of SWCNT based electronics with simpler fabrication process than that previously reported, considering such superior electronic properties and the flexibility of SWCNTs. In this paper, we report on the simple fabrication of stretchable logic devices consisting of p-type and n-type SWCNTs as channel materials on ultrathin PDMS substrate. Via utilizing flexible SWCNTs with very thin PDMS substrate which can relieve the strain by forming wavy configuration, stable device performance of SWCNT based logic devices is achieved under 30% strain which is much higher than the previously reported Si nano-ribbon devices.[13] In particular, there is no additional encapsulation process for fabricating such a highly stretchable device unlike the other previously reported ones.[5–13] small 2014, 10, No. 14, 2910–2917
Both the channel and electrode regions of the fabricated CMOS inverter arrays showed excellent stretchable behavior during the repeated stretching and the releasing cycles up to 103 times via forming wavy configurations. By using the classical lamination theory, we estimated the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions under the pre-strain up to 30%. Without extra fabrication processes of positioning the devices in mechanical neutral plane and encapsulating the whole device with a thin polymer film, device performance was maintained over stretching up to 30% and even over rolling the whole device arrays. The excellent mechanical stability of SWCNT CMOS inverter arrays is attributed to the combined application of highly flexible SWCNTs to the ultrathin PDMS substrates with wavy configuration. This work demonstrates that SWCNT devices can be exploited in soft systems and are well suited for use in implantable electronics and wearable computer applications.
2. Results and Discussion The key fabrication steps of the stretchable CMOS inverter are shown in Figure 1. The polyimide (PI) films (ca. 1 μm) are prepared by spin-coating onto SiO2 substrates and the patterned Ti/ Au (5/ 50 nm) gate electrodes are evaporated by e-beam evaporation. The 400 nm thick PVP layer is then spin coated for the gate dielectric layer. SWCNTs synthesized by chemical vapor deposition (CVD) are transferred onto a substrate by thermal release tape transfer method.[41] Source and drain electrodes of Pd (50 nm) are deposited by e-beam evaporation. For partial doping of the pristine SWCNT channel, NADH solution (10 mM diluted in DI-water) is drop-coated in the desired area of the channel, dried at 60 °C to evaporate the DI-water, and annealed at 150 °C for 10 min for electron donation from NADH to the SWCNTs. The Cr/SiO2 (30/ 20 nm) layer is deposited by e-beam evaporation for better adhesion between the PDMS and the PI film. The fabricated SWCNT CMOS inverters are detached using hollow rectangle-shaped magic tape which is attached onto the corner of the device.[12] The entire device array on the PI film is then transferred onto the 300 μm thick PDMS substrate. Prior to the transfer of the device array onto PDMS film, the PDMS film is stretched by using the home-made 1-D
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Figure 2. (a) (Left) Cross-sectional view of the fabricated CMOS inverter. (Right) optical microscope image of an inverter (top) and SEM image of channel area showing SWCNTs (bottom). (b) Transfer curves (Ids – Vg) of the pristine SWCNT FET (filled squares, left y-axis) and the NADH-coated SWCNT FET (open squares, right y-axis) with the variation of the drain voltage (Vds). (c) Transfer curves (Ids – Vg) of the pristine (filled squares) and NADH-coated (open squares) SWCNTs FETs at a drain voltage of +1 V in log-scale. (d) Measured transfer characteristics of CMOS inverters. Left y-axis is the change of the Vout and right-axis of the calculated gain value with respect to the change of Vin between -2 and 8 V, respectively. Vdd of 5 V was applied.
stretchable stage and then exposed to ultra-violet/ozone for 5 min for better adhesion of the device array. The left scheme of Figure 2(a) shows the cross-sectional view of the SWCNT inverter. The total thickness of the device is about 2.5 μm. The right figure shows the optical microscope image of an inverter where half of the SWCNT channel is covered with NADH solution. The zoomed SEM image shows the randomly networked SWCNTs in the channel area. The SEM image of the SWCNT channel was taken from the device after stretching the whole device from the originally released wavy one in order to confirm that the channel area was not deformed on the releasing-stretching cycle. Figure 2(b) shows the Ids-Vg curves of the pristine- (filled sqaures, left y-axis) and NADH-coated and annealed at 150 °C (open squares, right y-axis) SWCNT FETs with variation of Vds from −1 to 1 V, respectively. Hysteresis behavior of pristine SWCNT FET is shown in Figure S1. The hysteresis window was 5 V, which was the difference between threshold voltages measured in forward and reverse scanning of the gate bias. As expected, the pristine SWCNT FET shows a typical p-type transfer behavior while the NADH treated SWCNT FET shows n-type characteristics. This demonstrates that the thermal annealing of NADH induces the donation of electrons via detachment of a hydrogen atom from NADH, resulting in n-doping of SWCNTs. In our previous work,[34] it was reported that the device performance of SWCNT homo-junction diode fabricated via n-doping by NADH was deteriorated in air ambient, but its instantaneous recovery was achieved by simple annealing at 150 °C for 5 min. Since water molecules
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adsorbed on NADH take electrons from SWCNTs, annealing can induce the desorption of water to keep the n-type property of NADH-coated SWCNTs. In this work, we did the annealing prior to the measurement of device performance. The field effect mobility (µfe) of the p- and n-type SWCNTs FET was estimated to be 32 and 14 cm2/Vs at Vds = 1 V using Equation (1), respectively, in the linear region of the transfer curve,
μ fe = Lg m d / ε WVds
(1)
where W and L are the channel's width and length, respectively, gm is the transconductance (gm = dIds/dVg), and ε and d are the permittivity and the thickness of PVP, respectively. Equation (1) is suitable for film-type devices such as the randomly networked SWCNTs FET fabricated here.[42] Figure 2(c) shows the transfer curves in logarithmic scale measured at Vds = 1 V. Both pristine (p-type, filled sqaures) and NADH-coated (n-type, open sqaures) SWCNT FETs exhibit uni-polar transfer behavior and the on/off current ratios are estimated to be higher than 103. With n-type conversion, the threshold voltage (Vth) was shifted toward the negative bias region. By combining the p-type and the n-type FETs, the CMOS inverter was fabricated as shown in the inset of Figure 2(d). The CMOS inverter exhibits well-defined static voltage transfer characteristics with a maximum voltage gain of 8.9 at a supply voltage (Vdd) of 5 V. Figure S2 shows the static characteristics of the CMOS inverter with the
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Figure 3. (a) Optical microscope images of the CMOS inverter array on pre-strained (εpre = 30%) PDMS substrate (left) and that after release of the strain (right). (b) Normalized on/off current ratio (Ion/Ioff) of pristine (left) and NADH-coated (right) SWCNT FETs with variation of pre-strain. (c) Change of gain value of CMOS inverter with respect to the pre-strain (left) and inverter gain value (G) under pre-strain of 30% normalized to that of fully relaxed (G0) with repetition of stretching/ releasing cycles (right).
consistent change of Vout-Vin curves with increase of Vdd from 2 to 5 V. In addition, the dynamic characteristics are analyzed by examining the change of the output waveform as a function of the input frequency from 200 to 1000 Hz with amplitude of 1 V as shown in Figure S3. As the input frequency is increased, the output waveform became more distorted, which is attributed to the delay time of the inverter contributing to the discharging/charging time of the load capacitance at the output.[43] Figure 3(a) shows the optical microscope images of CMOS inverter array on PDMS film under pre-strain of 30% (left) and 0% (right), respectively. Here, 0% pre-strain means the fully released state of the stretched device array. The CMOS inverter array on PI film was successfully peeled off from the SiO2 substrate using hollow rectangle-shape magic tape and Cr/SiO2 was deposited onto the bottom of the PI film. Transfer of the CMOS inverter array on Cr/SiO2 deposited PI film was performed by mild contact with the small 2014, 10, No. 14, 2910–2917
pre-strained (up to 30%) PDMS substrate which had been exposed to UV-ozone for the formation of surface –OH groups. When the pre-strained PDMS film was fully released, some wavy patterns were observed as shown in the right image of Figure 3(a). Accordingly, SWCNTs and NADHcoated SWCNTs in the channel region could experience the deformation due to the applied strain, which can be estimated by using a simple modeling in Figure 6. Figure 3(b) shows the change of device performance with applied uni-axial pre-strain; current on/off ratio normalized to that without strain for pristine SWCNT FET (left) and NADH-coated SWCNT FET (right), respectively. Under the pre-strain of up to 30%, two different devices showed very stable performance. In particular, the high stability of the NADH-coated FET is attributed to the presence of bulky ADP and ribose in NADH, acting as a passivation layer and maintaining the excellent adhesion between the SWCNTs and the NADH. The gain value (G) with applied uni-axial
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Figure 4. (a) Optical microscope images taken from the CMOS inverter array on i) pre-strained (εpre = 30%) PDMS, ii) released (εpre = 0) PDMS, iii) and iv) rolled PDMS upon release of pre-strain, in a clock-wise direction. Here, the thickness of PDMS film is less than 100 µm. (b) (Left y-axis) Change of current on/off ratio (Ion/Ioff) of NADH-coated SWCNT FET with sequential deformation of pre-strain, release, and rolling. (Right y-axis) Change of the gain value of inverter normalized to that of initial pre-strained device upon sequential deformation of pre-strain, release, and rolling. Here, the inverter performance was measured at Vdd of 3 V.
pre-strain of up to 30% and the normalized gain value G/G0 of the CMOS inverter at Vdd of 3 V were kept nearly constant even after 1000 repetitions of stretching (30%) and releasing cycles, as shown in Figure 3(c). It should be noted that the channel materials and the dielectric layer seemed to keep their initial properties under applied pre-strain, which is attributed to the minimization of the local strain. Since we used a thin PDMS substrate, both the PDMS and the device arrays on PDMS seemed to form a wavy pattern with a small curvature when the pre-strained device arrays on PDMS were released as shown in Figure 3(a). Later, we will estimate the local strain applied to the SWCNT channels and Pd electrodes to understand the strain-relieving mechanism by using the classical lamination theory (Figure 6). When the thickness of the PDMS was reduced to ∼100 μm, the release of the pre-strained PDMS film with inverter arrays induced the rolling of the entire assembly. Optical microscope images show such a serial deformation in a clock-wise direction in Figure 4(a); i) pre-strained (εpre = 30%) inverter array, ii) fully released (εpre = 0%), iii) rolled and iv) fully rolled device array, respectively. Upon the release of the pre-strain, the entire film started to roll (ii→iii). Then finally, the CMOS inverter/ PDMS film was fully rolled like a roll of paper (iv). We can recover the originally pre-strained state via stretching the rolled assembly in uni-directional stretching stage. With such deformation, electronic device performance was measured for the NADHcoated SWCNT FETs and CMOS inverters. In Figure 4(b), the on and off current ratio (Ion/Ioff) of the NADH coated SWCNT FET and the normalized gain (G/G0) of the CMOS inverter are shown under the conditions of pre-strain (εpre = 30%) (i), release of the strain (εpre = 0%) (ii), and roll-up (iv). Here, G0 is the gain value of the pre-strained CMOS inverter. Both the n-type SWCNT FET and CMOS inverter showed very stable device performance under such deformations. Next, the flexibility of the fabricated inverter array was investigated. Figure 5(a) shows the optical microscope images taken from the CMOS inverter arrays with variation of the bending radius from flat to 0.3 cm. The CMOS inverter array was attached onto a magic tape. It is clearly shown that the inverter array can be freely bent. The device performance of the CMOS inverter was measured under the various bending conditions. As shown in Figure 5(b), the normalized gain of
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inverter G/G0, where G0 is the gain of inverter without bending, was not changed with a decrease of the bending radius. In addition, 1000 times repetitive bending of the inverter array at a bending radius of 0.7 cm did not deteriorate the device performance. Such a stable device performance implies a robustness of the inverter array, particularly that of SWCNTs and NADHcoated SWCNTs under harsh bending deformation. In order to estimate the local strain of the SWCNT channel in the CMOS inverter, a simplified cross-sectional sheme consisting of four different materials, i.e. PDMS, PI, PVP, and SWCNT was used as shown in Figure 6(a). Then, we can calculate the position of neutral plane of such cross-section. With the classical lamination theory, the behavior of this composite material can be predicted.[44] Based on the classical lamination theory, the force-strain relations are calculated considering non-mechanical effect such as hygrothermal effect or pre-strain effect as follows by using Equations (2) – (8); ⎧ N′ ⎫ ⎧ N ⎫ ⎡ AB ⎤ 0 ⎥ {ε κ } − ⎨ ⎬ ⎨ ⎬= ⎢ BD M ⎥⎦ ⎩ M′ ⎭ ⎩ ⎭ ⎢⎣
(2)
A = ∑ k =1 Q kij ( h k − h k −1 )
(3)
n
B=
1 n Q k h 2 − h 2k-1 ) 2 ∑ k =1 ij ( k
(4)
D=
1 n Q k h 3 − h 3k −1 ) 3 ∑ k =1 ij ( k
(5)
⎡ Ek ⎢ 1−υ2 k ⎢ ⎢ υ kE k k Q ij = ⎢ 1 − υ k2 ⎢ ⎢ 0 ⎢ ⎣
υ kE k 1 − υ k2
0
Ek 1 − υ k2
0
0
Ek 2 (1 + υ k )
⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦
(6)
N ′ = ∑ k =1 Q ikj t k e k
(7)
M ′ = ∑ k =1 Q ikj t k z k e k
(8)
n
n
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to maintain the electrical property of the SWCNT channel upon mechanical deformation of pre-strain and roll-up.[48,49] In a similar manner, the local strain applied to the Pd electrodes was also estimated to be ∼0.22% which is also small enough to keep the stable electrical performances under the pre-strain and releasing deformation.[50] By a serial connection of three SWCNT CMOS inverters, a ring oscillator can be fabricated and a stable device Figure 5. (a) Optical microscope images of the CMOS inverter arrays on PDMS substrate with performance is expected only with the variation of bending radius from flat to 0.3 cm. (b) Normalized gain value of inverter (G/G0) reproducible performance of the indiwith variation of bending radiusfrom flat to 0.3 cm (left y-axis). Normalized gain value (G/G0) vidual inverter. Optical microscope images under bending with a bending radius of 0.7 cm as a function of bending cycles (right y-axis). of ring-oscillator array on SiO2 substrate prior to the transfer onto PDMS, and where N, M are force and moment resultants, A, B, D are those on PDMS substrate under different pre-strains are stiffness matrices, N′, M′ are nonmechanical force and shown in Figure 7(a). Here, the ring-oscillator array on SiO2 moment resultants, and ε0,κ are strain at neutral plane which substrate was transferred onto a pre-strained (εpre = 10%) is defined by ε x0 = ∂u 0 / ∂x and curvature κ x = − ∂ 2 w / ∂x 2 as PDMS and then released up to the pre-strain of 0%. Optical shown in Figure 6(b), respectively. n is the total number of microscope images distinguish the wavy patterns on the layers, and k indicates kth layer, Q kij is stiffness matrix of kth SWCNT channel and the electrodes region upon the release layer, hk,Ek,υk are height, elastic moduli, Poisson’s ratio of the of pre-strain. Figure 7(b) shows a scheme (top) and SEM kth layer, respectively. The elastic moduli and the Poisson’s image (bottom) of a ring-oscillator taken under the pre-strain ratio of PDMS, PI, PVP, and CNT are 0.615, 2500, 1900, and of 10%. The waveforms of the 3-stage ring oscillator under 1 000 000 MPa and 0.5, 0.33, 0.34, and 0.43, respectively.[45,46] pre-strained (εpre = 10%, open sqaures) and released condiSince the elastic modulus of CNT was reported to be ranging tions (εpre = 0%, filled sqaures) are presented in Figure 7(c). from 0.6 to 1.5 Tpa,[47] we took the medium value of 1.0 TPa The electrical measurement demonstrates a stable oscillator for the calculation here. tk, ek, zk are thickness, nonmechanical frequency of ∼3.5 kHz at a supply voltage of 10 V and the strain such as hygrothermal strain or pre-strain, and z-coor- oscillating waveforms are maintained without any distortion dinate to the neutral plane of the kth layer, respectively. The under such deformation of pre-strain and release. non-mechanical strain is given as ek = { ε pre 0 0} T for PDMS layer, but the others should be zero. We assume that there is no external axial force, N = 0. The curvature can be obtained 3. Conclusion from the Figure 3(a), i.e., κ = 1/3.2 mm when the pre-strain εpre is equal to 30%. The longitudinal strain at neutral plane In this study, we demonstrate simple routes to fabricate the can be calculated as follows by using Equation (9); stretchable SWCNT based CMOS inverter arrays and ring oscillators on ultrathin PDMS substrate with stable electrical (9) and mechanical performance under maximum strain of 30% ε 0 = A −1 ( N ′ − Bκ 0 ) via forming wavy configuration. By using the classical lamination theory, we estimated the local strain of less than 0.6% The strain at each layer in the laminate can be calculated in the SWCNT channel and Pd electrode regions under the as follows by using Equation (10); pre-strain up to 30%. This simple fabrication process can be
ε k = ε 0 + z kκ
(10)
Finally, the strain of SWCNT channel is estimated to be around 0.51%. If we include the whole range of elastic modulus of CNTs between 0.6 and 1.5 Tpa,[47] the strain applied to SWCNT channel is estimated in the range of 0.56 and 0.46%, which is less than 0.6%. We also estimate the local strain of the SWCNT channel in fully rolled case already described in Figure 5, to be about 0.56%. It is of note that the local strain is sufficiently small small 2014, 10, No. 14, 2910–2917
Figure 6. (a) Cross-sectional view of the fabricated CMOS inverter, and (b) laminate section before and after deformation, where u0 is the reference plane displacements in x-direction, w is the out-of-plane displacement in z-direction, αx is the rotation of x-axis which is defined by αx = ∂w/∂x, respectively.[44]
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Figure 7. (a) Optical microscope images of ring-oscillator array on SiO2 substrate prior to the transfer onto PDMS, and those on PDMS substrate under different pre-strains in a counter-clockwise direction. (b) A scheme (top) and SEM image (bottom) of a ring-oscillator taken under the prestrain of 10%. (c) Waveforms of the 3-stage ring oscillator under pre-strained (εpre = 10%, open squares) and released conditions (εpre = 0, filled sqaures).
potentially combined with wearable computer technologies for future stretchable electronics.
4. Experimental Details Growth of SWCNTs: SWCNTs were grown on a thermally grown SiO2 substrate by chemical vapor deposition (CVD). Prior to the growth, DI-water diluted (1:6000) aqueous ferritin (Sigma Aldrich) was coated and annealed at 900 °C to form about 1 nm sized Fe2O3 nanoparticles. A continuous flow of 300 sccm H2 was maintained inside the CVD tube, while the temperature was increased to 925 °C. Under flows of 60 sccm H2, 26 sccm Ar, and 30 sccm methane with an ethanol/methanol bubbler, SWCNTs were grown at 925 °C for 15 min. After growth, the SiO2 substrate was rapidly cooled to room temperature under 80 sccm Ar flow. In our previous work,[51] we reported that the on/off current ratio of SWCNT FETs could be controlled via variation of the concentration of ferritin catalyst used for the growth of SWCNTs by CVD. Furthermore, we can increase the on/off ratio up to 103 via patterning of SWCNT channel by reactive ion etching, which reduces the electronic transport through metallic SWCNT path as shown in Figure S4. Device Fabrication: Polyamic acid solution (Aldrich) was spin-coated onto a SiO2/Si substrate in a two-step process of 1000 rpm for 10 s and 3000 rpm for 45 s, and annealed to make about 1 μm thick polyimide film as a supporting layer following a three-step curing process of 95 °C for 3 min, 150 °C for 10 min, and 250 °C for 2 h in Ar atmosphere. Patterned Ti/Au (5/ 50 nm) film as a gate electrode was deposited via e-beam evaporation before the spin coating of 400 nm PVP layer on top of the PI film for the gate dielectric layer. The spin-coated PVP dielectric layer showed a good insulating property with a very small leakage current under the gate bias voltage between -10 and +10 V as shown in the Figure S5. The CVD-grown SWCNTs were transferred onto a substrate via previously reported thermal release tape transfer method.[41] Source and drain electrodes of Pd (50 nm) were
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deposited by e-beam evaporation. To confine the channel area, residual SWCNTs were removed by reactive ion etching (O2, 10 mTorr, 100 W, 20 sccm, 30 sec). For partial doping of pristine SWCNT channel, NADH solution (10 mM diluted in DI-water) was dropped onto the desired area of the channel by drop coating, dried at 60 °C to evaporate the DI-water, and annealed at 150 °C for 10 min for electron donation from NADH to the SWCNTs. The fabricated SWCNT CMOS inverters were detached by using hollow rectangle-shaped magic tape which was attached to the corner of the device.[12] On the back side of the device arrays on PI film, a Cr/SiO2 (30/20 nm) layer was deposited by e-beam evaporation for better adhesion between the PDMS and the PI film. The entire device array on the PI film was then transferred and mild-pressed onto the 300 μm thick PDMS substrate. Device Performance under Deformation: Prior to the transfer of the device array onto PDMS film, the PDMS film was stretched by more than 30% by using the home-made 1-D stretchable stage and then exposed to ultra-violet/ozone for 5 min for better adhesion of the device array. Under the strain applied between 0 and 30%, measurements of both pand n-type FET, CMOS inverter, and 3-stage ring oscillator were performed using a B1500A semiconducting device analyzer (Agilent technologies).
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements This work was supported by the National ResearchFoundation of Korea(NRF) grant funded by the Korea government (MEST) (Grant No. 2013R1A2A1A01016165). It was partially supported by IT R&D
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program of MKE/KEIT (Grant No. 10041416, the core technology development of light and space adaptable new mode display for energy saving on 7 inch and 2 W). We also thank the KU-KIST Graduate School Program of Korea University, Korea.
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Received: December 9, 2013 Revised: March 12, 2014 Published online: April 2, 2014
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Fabrication of Stretchable Single-Walled Carbon Nanotube Logic Devices Jangyeol Yoon, Gunchul Shin, Joonsung Kim, Young Sun Moon, Seung-Jung Lee, Goangseup Zi, and Jeong Sook Ha*
The
fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics.
1. Introduction There have been extentive research on the realization of electronic devices which are flexible, foldable, and stretchable but with performance comparable to that of conventional rigid electronics, due to the growing potential applications of future wearable systems to personal smart devices and
J. Yoon, G. Shin, J. Kim, Y. S. Moon, Prof. J. S. Ha Department of Chemical and Biological Engineering Korea University Seoul 136-701, Korea E-mail: [email protected] Prof. J. S. Ha KU-KIST Graduate School of Converging Science and Technology Korea University Seoul 136-701, Korea S.-J. Lee, Prof. G. Zi Department of Civil Environmental and Architectural Engineering Korea University Seoul 136-701, Korea DOI: 10.1002/smll.201303779
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bio-implantable electronics. Various kinds of stretchable logic devices using inorganic nano-ribbons as channel materials have been demonstrated.[1–4] Most of the previous stretchable electronics adopted the design concepts of mechanical neutral plane and curved/serpentine interconnects to reduce the strain applied to the active device area.[5–10] Using the same design concepts, stretchable logic device arrays of metal oxide nanowires were also reported.[11,12] In addition, alignd array of Si nanoribbon based devices on ultrathin elastomeric PDMS substrate, in multilayer mechanical neutral plane design and wavy structural layouts, showed stable device performance upon deformations including folding and stretching up to ∼10%,[13] which demonstrated a simple route to high performance, stretchable, and foldable integrated circuits. In the fabrication of electronic devices, amorphous silicon, poly-silicon, organic materials, metal-oxide nanowires, and single-walled carbon nanotubes (SWCNTs) have been explored as active channel materials.[14–23] Among them, SWCNTs exhibited excellent mechanical, thermal, chemical, optically transparent, and electronic properties.[24–26] In particular, SWCNT based electronic devices on rigid substrates have shown outstanding device performance even exceeding that of conventional devices using amorphous silicon, poly-silicon, or organic materials.[27–29] It is also
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Fabrication of Stretchable Single-Walled Carbon Nanotube Logic Devices
Figure 1. Schematics of fabricating a stretchable CMOS inverter array consisting of CVD grown pristine p-SWCNTs and NADH- coated n-SWCNTs FETs.
advantageous that SWCNT based electronic devices can be fabricated at low temperatures. Owing to these superior properties of SWCNTs, complicated flexible logic circuits including inverter, NAND, NOR, and ring oscillator have been demonstrated so far.[22,30] However, semiconducting SWCNTs grown via chemical vapor deposition (CVD) generally exhibit p-type transfer properties. Thus, the type conversion of pristine SWCNTs into n-type has been one of the key challenges for the fabrication of various logic devices.[31] Coating of electron-donating poly(ethylenimine) onto the pristine SWCNTs was observed to induce n-type properties,[32] but it was not stable under humid ambient so that it recovered the intrinsic p-type properties within a few days.[33] In our previous work,[34] we could successfully fabricate the stable intra-tube junction diode via type-conversion of pristine SWCNTs by partial coating with β-nicotinamide adenine dinucleotide, reduced dipotassium salt (NADH), and subsequent annealing. Compared to the tremendous works on SWCNT based electronic devices, there have only been a few reports on SWCNT based stretchable devices. Even though an artificial electronic-skin using SWCNT thin film transistor active matrix was demonstrated,[35] most of the research on SWCNT based stretchable electronics showed the change of resistance with stretching in the highly conductive interconnections of randomly networked SWCNTs.[36–39] Recently, it was reported that SWCNT FETs were stable over the stretching between 5 and 20% by introducing the wrinkled Al2O3 gate dielectric layer.[40] However, it will be more useful to have higher mechanical stability of SWCNT based electronics with simpler fabrication process than that previously reported, considering such superior electronic properties and the flexibility of SWCNTs. In this paper, we report on the simple fabrication of stretchable logic devices consisting of p-type and n-type SWCNTs as channel materials on ultrathin PDMS substrate. Via utilizing flexible SWCNTs with very thin PDMS substrate which can relieve the strain by forming wavy configuration, stable device performance of SWCNT based logic devices is achieved under 30% strain which is much higher than the previously reported Si nano-ribbon devices.[13] In particular, there is no additional encapsulation process for fabricating such a highly stretchable device unlike the other previously reported ones.[5–13] small 2014, 10, No. 14, 2910–2917
Both the channel and electrode regions of the fabricated CMOS inverter arrays showed excellent stretchable behavior during the repeated stretching and the releasing cycles up to 103 times via forming wavy configurations. By using the classical lamination theory, we estimated the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions under the pre-strain up to 30%. Without extra fabrication processes of positioning the devices in mechanical neutral plane and encapsulating the whole device with a thin polymer film, device performance was maintained over stretching up to 30% and even over rolling the whole device arrays. The excellent mechanical stability of SWCNT CMOS inverter arrays is attributed to the combined application of highly flexible SWCNTs to the ultrathin PDMS substrates with wavy configuration. This work demonstrates that SWCNT devices can be exploited in soft systems and are well suited for use in implantable electronics and wearable computer applications.
2. Results and Discussion The key fabrication steps of the stretchable CMOS inverter are shown in Figure 1. The polyimide (PI) films (ca. 1 μm) are prepared by spin-coating onto SiO2 substrates and the patterned Ti/ Au (5/ 50 nm) gate electrodes are evaporated by e-beam evaporation. The 400 nm thick PVP layer is then spin coated for the gate dielectric layer. SWCNTs synthesized by chemical vapor deposition (CVD) are transferred onto a substrate by thermal release tape transfer method.[41] Source and drain electrodes of Pd (50 nm) are deposited by e-beam evaporation. For partial doping of the pristine SWCNT channel, NADH solution (10 mM diluted in DI-water) is drop-coated in the desired area of the channel, dried at 60 °C to evaporate the DI-water, and annealed at 150 °C for 10 min for electron donation from NADH to the SWCNTs. The Cr/SiO2 (30/ 20 nm) layer is deposited by e-beam evaporation for better adhesion between the PDMS and the PI film. The fabricated SWCNT CMOS inverters are detached using hollow rectangle-shaped magic tape which is attached onto the corner of the device.[12] The entire device array on the PI film is then transferred onto the 300 μm thick PDMS substrate. Prior to the transfer of the device array onto PDMS film, the PDMS film is stretched by using the home-made 1-D
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Figure 2. (a) (Left) Cross-sectional view of the fabricated CMOS inverter. (Right) optical microscope image of an inverter (top) and SEM image of channel area showing SWCNTs (bottom). (b) Transfer curves (Ids – Vg) of the pristine SWCNT FET (filled squares, left y-axis) and the NADH-coated SWCNT FET (open squares, right y-axis) with the variation of the drain voltage (Vds). (c) Transfer curves (Ids – Vg) of the pristine (filled squares) and NADH-coated (open squares) SWCNTs FETs at a drain voltage of +1 V in log-scale. (d) Measured transfer characteristics of CMOS inverters. Left y-axis is the change of the Vout and right-axis of the calculated gain value with respect to the change of Vin between -2 and 8 V, respectively. Vdd of 5 V was applied.
stretchable stage and then exposed to ultra-violet/ozone for 5 min for better adhesion of the device array. The left scheme of Figure 2(a) shows the cross-sectional view of the SWCNT inverter. The total thickness of the device is about 2.5 μm. The right figure shows the optical microscope image of an inverter where half of the SWCNT channel is covered with NADH solution. The zoomed SEM image shows the randomly networked SWCNTs in the channel area. The SEM image of the SWCNT channel was taken from the device after stretching the whole device from the originally released wavy one in order to confirm that the channel area was not deformed on the releasing-stretching cycle. Figure 2(b) shows the Ids-Vg curves of the pristine- (filled sqaures, left y-axis) and NADH-coated and annealed at 150 °C (open squares, right y-axis) SWCNT FETs with variation of Vds from −1 to 1 V, respectively. Hysteresis behavior of pristine SWCNT FET is shown in Figure S1. The hysteresis window was 5 V, which was the difference between threshold voltages measured in forward and reverse scanning of the gate bias. As expected, the pristine SWCNT FET shows a typical p-type transfer behavior while the NADH treated SWCNT FET shows n-type characteristics. This demonstrates that the thermal annealing of NADH induces the donation of electrons via detachment of a hydrogen atom from NADH, resulting in n-doping of SWCNTs. In our previous work,[34] it was reported that the device performance of SWCNT homo-junction diode fabricated via n-doping by NADH was deteriorated in air ambient, but its instantaneous recovery was achieved by simple annealing at 150 °C for 5 min. Since water molecules
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adsorbed on NADH take electrons from SWCNTs, annealing can induce the desorption of water to keep the n-type property of NADH-coated SWCNTs. In this work, we did the annealing prior to the measurement of device performance. The field effect mobility (µfe) of the p- and n-type SWCNTs FET was estimated to be 32 and 14 cm2/Vs at Vds = 1 V using Equation (1), respectively, in the linear region of the transfer curve,
μ fe = Lg m d / ε WVds
(1)
where W and L are the channel's width and length, respectively, gm is the transconductance (gm = dIds/dVg), and ε and d are the permittivity and the thickness of PVP, respectively. Equation (1) is suitable for film-type devices such as the randomly networked SWCNTs FET fabricated here.[42] Figure 2(c) shows the transfer curves in logarithmic scale measured at Vds = 1 V. Both pristine (p-type, filled sqaures) and NADH-coated (n-type, open sqaures) SWCNT FETs exhibit uni-polar transfer behavior and the on/off current ratios are estimated to be higher than 103. With n-type conversion, the threshold voltage (Vth) was shifted toward the negative bias region. By combining the p-type and the n-type FETs, the CMOS inverter was fabricated as shown in the inset of Figure 2(d). The CMOS inverter exhibits well-defined static voltage transfer characteristics with a maximum voltage gain of 8.9 at a supply voltage (Vdd) of 5 V. Figure S2 shows the static characteristics of the CMOS inverter with the
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Figure 3. (a) Optical microscope images of the CMOS inverter array on pre-strained (εpre = 30%) PDMS substrate (left) and that after release of the strain (right). (b) Normalized on/off current ratio (Ion/Ioff) of pristine (left) and NADH-coated (right) SWCNT FETs with variation of pre-strain. (c) Change of gain value of CMOS inverter with respect to the pre-strain (left) and inverter gain value (G) under pre-strain of 30% normalized to that of fully relaxed (G0) with repetition of stretching/ releasing cycles (right).
consistent change of Vout-Vin curves with increase of Vdd from 2 to 5 V. In addition, the dynamic characteristics are analyzed by examining the change of the output waveform as a function of the input frequency from 200 to 1000 Hz with amplitude of 1 V as shown in Figure S3. As the input frequency is increased, the output waveform became more distorted, which is attributed to the delay time of the inverter contributing to the discharging/charging time of the load capacitance at the output.[43] Figure 3(a) shows the optical microscope images of CMOS inverter array on PDMS film under pre-strain of 30% (left) and 0% (right), respectively. Here, 0% pre-strain means the fully released state of the stretched device array. The CMOS inverter array on PI film was successfully peeled off from the SiO2 substrate using hollow rectangle-shape magic tape and Cr/SiO2 was deposited onto the bottom of the PI film. Transfer of the CMOS inverter array on Cr/SiO2 deposited PI film was performed by mild contact with the small 2014, 10, No. 14, 2910–2917
pre-strained (up to 30%) PDMS substrate which had been exposed to UV-ozone for the formation of surface –OH groups. When the pre-strained PDMS film was fully released, some wavy patterns were observed as shown in the right image of Figure 3(a). Accordingly, SWCNTs and NADHcoated SWCNTs in the channel region could experience the deformation due to the applied strain, which can be estimated by using a simple modeling in Figure 6. Figure 3(b) shows the change of device performance with applied uni-axial pre-strain; current on/off ratio normalized to that without strain for pristine SWCNT FET (left) and NADH-coated SWCNT FET (right), respectively. Under the pre-strain of up to 30%, two different devices showed very stable performance. In particular, the high stability of the NADH-coated FET is attributed to the presence of bulky ADP and ribose in NADH, acting as a passivation layer and maintaining the excellent adhesion between the SWCNTs and the NADH. The gain value (G) with applied uni-axial
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Figure 4. (a) Optical microscope images taken from the CMOS inverter array on i) pre-strained (εpre = 30%) PDMS, ii) released (εpre = 0) PDMS, iii) and iv) rolled PDMS upon release of pre-strain, in a clock-wise direction. Here, the thickness of PDMS film is less than 100 µm. (b) (Left y-axis) Change of current on/off ratio (Ion/Ioff) of NADH-coated SWCNT FET with sequential deformation of pre-strain, release, and rolling. (Right y-axis) Change of the gain value of inverter normalized to that of initial pre-strained device upon sequential deformation of pre-strain, release, and rolling. Here, the inverter performance was measured at Vdd of 3 V.
pre-strain of up to 30% and the normalized gain value G/G0 of the CMOS inverter at Vdd of 3 V were kept nearly constant even after 1000 repetitions of stretching (30%) and releasing cycles, as shown in Figure 3(c). It should be noted that the channel materials and the dielectric layer seemed to keep their initial properties under applied pre-strain, which is attributed to the minimization of the local strain. Since we used a thin PDMS substrate, both the PDMS and the device arrays on PDMS seemed to form a wavy pattern with a small curvature when the pre-strained device arrays on PDMS were released as shown in Figure 3(a). Later, we will estimate the local strain applied to the SWCNT channels and Pd electrodes to understand the strain-relieving mechanism by using the classical lamination theory (Figure 6). When the thickness of the PDMS was reduced to ∼100 μm, the release of the pre-strained PDMS film with inverter arrays induced the rolling of the entire assembly. Optical microscope images show such a serial deformation in a clock-wise direction in Figure 4(a); i) pre-strained (εpre = 30%) inverter array, ii) fully released (εpre = 0%), iii) rolled and iv) fully rolled device array, respectively. Upon the release of the pre-strain, the entire film started to roll (ii→iii). Then finally, the CMOS inverter/ PDMS film was fully rolled like a roll of paper (iv). We can recover the originally pre-strained state via stretching the rolled assembly in uni-directional stretching stage. With such deformation, electronic device performance was measured for the NADHcoated SWCNT FETs and CMOS inverters. In Figure 4(b), the on and off current ratio (Ion/Ioff) of the NADH coated SWCNT FET and the normalized gain (G/G0) of the CMOS inverter are shown under the conditions of pre-strain (εpre = 30%) (i), release of the strain (εpre = 0%) (ii), and roll-up (iv). Here, G0 is the gain value of the pre-strained CMOS inverter. Both the n-type SWCNT FET and CMOS inverter showed very stable device performance under such deformations. Next, the flexibility of the fabricated inverter array was investigated. Figure 5(a) shows the optical microscope images taken from the CMOS inverter arrays with variation of the bending radius from flat to 0.3 cm. The CMOS inverter array was attached onto a magic tape. It is clearly shown that the inverter array can be freely bent. The device performance of the CMOS inverter was measured under the various bending conditions. As shown in Figure 5(b), the normalized gain of
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inverter G/G0, where G0 is the gain of inverter without bending, was not changed with a decrease of the bending radius. In addition, 1000 times repetitive bending of the inverter array at a bending radius of 0.7 cm did not deteriorate the device performance. Such a stable device performance implies a robustness of the inverter array, particularly that of SWCNTs and NADHcoated SWCNTs under harsh bending deformation. In order to estimate the local strain of the SWCNT channel in the CMOS inverter, a simplified cross-sectional sheme consisting of four different materials, i.e. PDMS, PI, PVP, and SWCNT was used as shown in Figure 6(a). Then, we can calculate the position of neutral plane of such cross-section. With the classical lamination theory, the behavior of this composite material can be predicted.[44] Based on the classical lamination theory, the force-strain relations are calculated considering non-mechanical effect such as hygrothermal effect or pre-strain effect as follows by using Equations (2) – (8); ⎧ N′ ⎫ ⎧ N ⎫ ⎡ AB ⎤ 0 ⎥ {ε κ } − ⎨ ⎬ ⎨ ⎬= ⎢ BD M ⎥⎦ ⎩ M′ ⎭ ⎩ ⎭ ⎢⎣
(2)
A = ∑ k =1 Q kij ( h k − h k −1 )
(3)
n
B=
1 n Q k h 2 − h 2k-1 ) 2 ∑ k =1 ij ( k
(4)
D=
1 n Q k h 3 − h 3k −1 ) 3 ∑ k =1 ij ( k
(5)
⎡ Ek ⎢ 1−υ2 k ⎢ ⎢ υ kE k k Q ij = ⎢ 1 − υ k2 ⎢ ⎢ 0 ⎢ ⎣
υ kE k 1 − υ k2
0
Ek 1 − υ k2
0
0
Ek 2 (1 + υ k )
⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦
(6)
N ′ = ∑ k =1 Q ikj t k e k
(7)
M ′ = ∑ k =1 Q ikj t k z k e k
(8)
n
n
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to maintain the electrical property of the SWCNT channel upon mechanical deformation of pre-strain and roll-up.[48,49] In a similar manner, the local strain applied to the Pd electrodes was also estimated to be ∼0.22% which is also small enough to keep the stable electrical performances under the pre-strain and releasing deformation.[50] By a serial connection of three SWCNT CMOS inverters, a ring oscillator can be fabricated and a stable device Figure 5. (a) Optical microscope images of the CMOS inverter arrays on PDMS substrate with performance is expected only with the variation of bending radius from flat to 0.3 cm. (b) Normalized gain value of inverter (G/G0) reproducible performance of the indiwith variation of bending radiusfrom flat to 0.3 cm (left y-axis). Normalized gain value (G/G0) vidual inverter. Optical microscope images under bending with a bending radius of 0.7 cm as a function of bending cycles (right y-axis). of ring-oscillator array on SiO2 substrate prior to the transfer onto PDMS, and where N, M are force and moment resultants, A, B, D are those on PDMS substrate under different pre-strains are stiffness matrices, N′, M′ are nonmechanical force and shown in Figure 7(a). Here, the ring-oscillator array on SiO2 moment resultants, and ε0,κ are strain at neutral plane which substrate was transferred onto a pre-strained (εpre = 10%) is defined by ε x0 = ∂u 0 / ∂x and curvature κ x = − ∂ 2 w / ∂x 2 as PDMS and then released up to the pre-strain of 0%. Optical shown in Figure 6(b), respectively. n is the total number of microscope images distinguish the wavy patterns on the layers, and k indicates kth layer, Q kij is stiffness matrix of kth SWCNT channel and the electrodes region upon the release layer, hk,Ek,υk are height, elastic moduli, Poisson’s ratio of the of pre-strain. Figure 7(b) shows a scheme (top) and SEM kth layer, respectively. The elastic moduli and the Poisson’s image (bottom) of a ring-oscillator taken under the pre-strain ratio of PDMS, PI, PVP, and CNT are 0.615, 2500, 1900, and of 10%. The waveforms of the 3-stage ring oscillator under 1 000 000 MPa and 0.5, 0.33, 0.34, and 0.43, respectively.[45,46] pre-strained (εpre = 10%, open sqaures) and released condiSince the elastic modulus of CNT was reported to be ranging tions (εpre = 0%, filled sqaures) are presented in Figure 7(c). from 0.6 to 1.5 Tpa,[47] we took the medium value of 1.0 TPa The electrical measurement demonstrates a stable oscillator for the calculation here. tk, ek, zk are thickness, nonmechanical frequency of ∼3.5 kHz at a supply voltage of 10 V and the strain such as hygrothermal strain or pre-strain, and z-coor- oscillating waveforms are maintained without any distortion dinate to the neutral plane of the kth layer, respectively. The under such deformation of pre-strain and release. non-mechanical strain is given as ek = { ε pre 0 0} T for PDMS layer, but the others should be zero. We assume that there is no external axial force, N = 0. The curvature can be obtained 3. Conclusion from the Figure 3(a), i.e., κ = 1/3.2 mm when the pre-strain εpre is equal to 30%. The longitudinal strain at neutral plane In this study, we demonstrate simple routes to fabricate the can be calculated as follows by using Equation (9); stretchable SWCNT based CMOS inverter arrays and ring oscillators on ultrathin PDMS substrate with stable electrical (9) and mechanical performance under maximum strain of 30% ε 0 = A −1 ( N ′ − Bκ 0 ) via forming wavy configuration. By using the classical lamination theory, we estimated the local strain of less than 0.6% The strain at each layer in the laminate can be calculated in the SWCNT channel and Pd electrode regions under the as follows by using Equation (10); pre-strain up to 30%. This simple fabrication process can be
ε k = ε 0 + z kκ
(10)
Finally, the strain of SWCNT channel is estimated to be around 0.51%. If we include the whole range of elastic modulus of CNTs between 0.6 and 1.5 Tpa,[47] the strain applied to SWCNT channel is estimated in the range of 0.56 and 0.46%, which is less than 0.6%. We also estimate the local strain of the SWCNT channel in fully rolled case already described in Figure 5, to be about 0.56%. It is of note that the local strain is sufficiently small small 2014, 10, No. 14, 2910–2917
Figure 6. (a) Cross-sectional view of the fabricated CMOS inverter, and (b) laminate section before and after deformation, where u0 is the reference plane displacements in x-direction, w is the out-of-plane displacement in z-direction, αx is the rotation of x-axis which is defined by αx = ∂w/∂x, respectively.[44]
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Figure 7. (a) Optical microscope images of ring-oscillator array on SiO2 substrate prior to the transfer onto PDMS, and those on PDMS substrate under different pre-strains in a counter-clockwise direction. (b) A scheme (top) and SEM image (bottom) of a ring-oscillator taken under the prestrain of 10%. (c) Waveforms of the 3-stage ring oscillator under pre-strained (εpre = 10%, open squares) and released conditions (εpre = 0, filled sqaures).
potentially combined with wearable computer technologies for future stretchable electronics.
4. Experimental Details Growth of SWCNTs: SWCNTs were grown on a thermally grown SiO2 substrate by chemical vapor deposition (CVD). Prior to the growth, DI-water diluted (1:6000) aqueous ferritin (Sigma Aldrich) was coated and annealed at 900 °C to form about 1 nm sized Fe2O3 nanoparticles. A continuous flow of 300 sccm H2 was maintained inside the CVD tube, while the temperature was increased to 925 °C. Under flows of 60 sccm H2, 26 sccm Ar, and 30 sccm methane with an ethanol/methanol bubbler, SWCNTs were grown at 925 °C for 15 min. After growth, the SiO2 substrate was rapidly cooled to room temperature under 80 sccm Ar flow. In our previous work,[51] we reported that the on/off current ratio of SWCNT FETs could be controlled via variation of the concentration of ferritin catalyst used for the growth of SWCNTs by CVD. Furthermore, we can increase the on/off ratio up to 103 via patterning of SWCNT channel by reactive ion etching, which reduces the electronic transport through metallic SWCNT path as shown in Figure S4. Device Fabrication: Polyamic acid solution (Aldrich) was spin-coated onto a SiO2/Si substrate in a two-step process of 1000 rpm for 10 s and 3000 rpm for 45 s, and annealed to make about 1 μm thick polyimide film as a supporting layer following a three-step curing process of 95 °C for 3 min, 150 °C for 10 min, and 250 °C for 2 h in Ar atmosphere. Patterned Ti/Au (5/ 50 nm) film as a gate electrode was deposited via e-beam evaporation before the spin coating of 400 nm PVP layer on top of the PI film for the gate dielectric layer. The spin-coated PVP dielectric layer showed a good insulating property with a very small leakage current under the gate bias voltage between -10 and +10 V as shown in the Figure S5. The CVD-grown SWCNTs were transferred onto a substrate via previously reported thermal release tape transfer method.[41] Source and drain electrodes of Pd (50 nm) were
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deposited by e-beam evaporation. To confine the channel area, residual SWCNTs were removed by reactive ion etching (O2, 10 mTorr, 100 W, 20 sccm, 30 sec). For partial doping of pristine SWCNT channel, NADH solution (10 mM diluted in DI-water) was dropped onto the desired area of the channel by drop coating, dried at 60 °C to evaporate the DI-water, and annealed at 150 °C for 10 min for electron donation from NADH to the SWCNTs. The fabricated SWCNT CMOS inverters were detached by using hollow rectangle-shaped magic tape which was attached to the corner of the device.[12] On the back side of the device arrays on PI film, a Cr/SiO2 (30/20 nm) layer was deposited by e-beam evaporation for better adhesion between the PDMS and the PI film. The entire device array on the PI film was then transferred and mild-pressed onto the 300 μm thick PDMS substrate. Device Performance under Deformation: Prior to the transfer of the device array onto PDMS film, the PDMS film was stretched by more than 30% by using the home-made 1-D stretchable stage and then exposed to ultra-violet/ozone for 5 min for better adhesion of the device array. Under the strain applied between 0 and 30%, measurements of both pand n-type FET, CMOS inverter, and 3-stage ring oscillator were performed using a B1500A semiconducting device analyzer (Agilent technologies).
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements This work was supported by the National ResearchFoundation of Korea(NRF) grant funded by the Korea government (MEST) (Grant No. 2013R1A2A1A01016165). It was partially supported by IT R&D
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program of MKE/KEIT (Grant No. 10041416, the core technology development of light and space adaptable new mode display for energy saving on 7 inch and 2 W). We also thank the KU-KIST Graduate School Program of Korea University, Korea.
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Received: December 9, 2013 Revised: March 12, 2014 Published online: April 2, 2014
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