sensors Article

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide–Semiconductor Image Sensors Kuo-Tsai Wu 1 , Sheng-Jye Hwang 1, * and Huei-Huang Lee 2 1 2

*

Department of Mechanical Engineering, National Cheng Kung University, No. 1, University Road, Tainan 701, Taiwan; [email protected] Department of Engineering Science, National Cheng Kung University, No. 1, University Road, Tainan 701, Taiwan; [email protected] Correspondence: [email protected]; Tel.: +886-6-275-7575 (ext. 62184)

Academic Editor: Mustafa Yavuz Received: 20 February 2017; Accepted: 28 April 2017; Published: 2 May 2017

Abstract: Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components. Keywords: CMOS image sensor (CIS); layered structures; finite element analysis (FEA)

1. Introduction Traditional charge-coupled devices (CCDs) have been replaced by CMOS image sensors (CIS), which operate at lower voltage and consume less power than their predecessors. CIS are produced by the CMOS logic process in a system-on-chip (SOC) design environment. CISs are used in consumer electronics, such as digital cameras, optical mice, and mobile phones. However, the CMOS logic process reduces the effectiveness of CIS; a high-element driving current increases the CIS dark current, triggering white pixel noise [1]. Therefore, the performance of the elements, and the adverse effect of leakage currents, must be monitored during the actual process. By considering thermodynamics, the interfacial stress of the material interface, and its effect on semiconductor films, Cammarata [2] investigated the physical mechanism of surface stress on these films. Spaepe [3] studied athe intrinsic stress at the film’s interface, and Nix and Clement [4] identified the evolution mechanism of the intrinsic tensile stress in the film, namely, crystallite coalescence. Nix and Doerner [5] developed a method for measuring the film stress, described the mechanical properties of film, and modeled the origin of film stress. They also discussed the effect of the film’s microstructure on the deformation process of the film–substrate interface [6]. Wang et al. [7] studied the effect of uniaxial stress on the CIS leakage current by the four-point bending technique (4-PBT). They reported that increasing the tensile stress might further reduce

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the leakage current of N-type metal-oxide semiconductor (NMOS) image sensors, but renders the leakage current gain at the juncture very sensitive to microstrain. On the other hand, increasing the compressive stress outside the P-type metal-oxide semiconductor (PMOS) increases the leakage current in PMOS image sensors. In other words, increasing the tensile stress enhances the performance of the NMOS image sensor without reducing the leakage current at the juncture. However, for PMOS image sensors under uniaxial compressive stress, the performance of the elements and the effect of leakage current on the elements must be measured. Rueda [8] also indicated that CIS current flow is reduced under tensile stress, but significantly increased under compressive stress. When the compressive and tensile stresses applied to a CIS are equal, the compressive stress determines the characteristics of the elements. However, as the stress level affects the reverse bias current, the element performance at different leakage currents must be predetermined. Microminiaturization creates a short channel effect in semiconductors, reducing the critical voltage and increasing the subcritical leakage current. In particular, as the gate oxide layer thins, electrons can more easily penetrate the gate [9,10], generating a gate leakage current. The channel effect can be inhibited by an annular arrangement of the thin films. Although this arrangement effectively reduces the subcritical leakage current, it increases the band-to-band-tunneling (BTBT) leakage current [10,11]. In experiments, a tensile or compressive stress imposed on a semiconductor component affected the electrical performance and the leakage current generated in the off-state of the component [12–14]. In general, the relationship between film stress and leakage current significantly affects the characteristics of CIS. Watanabe et al. [15] evaluated the dark current defects of CIS and multiple stress-and-anneal cycles have been found to cause hardening, which was similar to the walk-out in the drain avalanche. Shcherback et al. [16] presented an empirical dark current model for CMOS active pixel sensors. The second part of the model deals with the stress-induced leakage current. The formation of interface traps in these stress regions enhances the generation velocity at the interface and, therefore, causes an increased surface leakage current. In assessing stress, Kim et al. [17] simulated mechanical stress in various backside deep trench isolation (BDTI) structures under a displacement using the FEM. Comparing the final shapes of various BDTIs revealed that it was possible to achieve low-stress structures by decreasing the interfacial curvature between the HfOX and the oxide. Therefore, the present study discusses the relationship between stress and leakage current in a thin film structure through finite element simulations. We simplified the simulation model (2D structure) to reduce the number of meshes and thereby increase the efficiency of the calculation. We also corrected the material parameters through the single-layer film annealing process experiment and applied the special elements method to simulate the actual stacking sequence process to increase accuracy. The finite element method not only removes the high cost of equivalent experimental analyses, but also establishes a material properties’ database of stacked materials for specification modification (such as changes in film thickness, stacking order, and stacked materials). The present study provides a computer simulation for semiconductor manufacturers, which can accelerate their technological developments while reducing the experimental cost and increasing the yield of their finished products. 2. Analysis Method 2.1. Finite Element Analysis The finite element analysis was performed by ANSYS software (ANSYS, Inc., Canonsburg, PA, USA). The flow was analyzed by a simplified model with set boundary conditions. The material parameters were obtained and the results were simulated. Since the color filters are stacked in the backend process of the wafer bonding, we first established the material parameters database. At this stage, the different properties of the materials stacked on the wafer, and the different heating and annealing temperatures, impose mechanical structural forces and

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stacked on the wafer, and the different heating and annealing temperatures, impose mechanical stacked on the wafer, and the different heating and annealing temperatures, impose mechanical structural forces and heat stresses that change the original properties of the elements. By applying structural forces and heat stresses that change the original properties of the elements. By applying finite element analysis, we can accurately observe the stress distributions in the various layers of the finite element analysis, we can accurately observe the stress distributions in the various layers of the material. Sensors 2017, 17, 1004 3 of 15 material. Figures 1 and 2 are schematics of the film stack architecture in the present study. This architecture Figures 1 and 2 are schematics of the film stack architecture in the present study. This architecture was provided by the cooperative manufacturer, Taiwan Semiconductor Manufacturing Company was stresses provided by the cooperative manufacturer, Taiwan Semiconductor Manufacturing Company heat original properties theinelements. By applying finite element analysis, Limited. The that lightchange sourcethe is received by the cell of area the CIS stack architecture, and obscured by Limited. The light source is received by the cell area in the CIS stack architecture, and obscured by we can accurately observe the stress distributions in the various layers of the material. the back-light compensation (BLC) area. The films are annealed, then stacked from bottom to top. As the back-light compensation (BLC)of area. The are annealed,inthen stacked study. from bottom to top. As and 2 are schematics the film films stack architecture present Thistemperature. architecture each Figures film is 1made from a different material, each requires a the different annealing each film is made from a different material, each requires a different annealing temperature. was providedare bymade the cooperative manufacturer, Taiwan Semiconductor Manufacturing Company Observations at the epitaxial layer, the measuring point in the leakage current measurement Observations are made atisthe epitaxial layer, thearea measuring point in the leakage current measurement Limited. The light source received by the cell in the CIS stack architecture, and obscured by the area, and the main leakage-current measurement point on the epitaxial layer surface. area, and the main leakage-current measurement point on the epitaxial layer surface. back-light compensation area. Thepoints films 1are annealed, then stacked bottom of to top. As each As shown in Figure(BLC) 2, measuring and 3 are located close tofrom the middle the cell area Asmade shown in aFigure 2, measuring points 1 and a3 different are located close totemperature. the middle ofObservations the cell area film is from different material, each requires annealing (approximately 300 μm from the centerline) and the middle of the BLC area (approximately 640 μm (approximately 300 μm from centerline) and theinmiddle of thecurrent BLC area (approximately and 640 μm are made at the epitaxial layer,the theand measuring point the leakage measurement the from the centerline, respectively, measurement point 2 is located near the junction area, between the from leakage-current the centerline, respectively, and measurement pointlayer 2 is located near the junction between the main measurement point on the epitaxial surface. cell and BLC areas (approximately 600 μm from the centerline). cell and BLC areas (approximately 600 μm from the centerline).

Figure 1. Top Top view (x-z (x-z plane) of of the stacked-film stacked-film architecture. It It is aa symmetrical symmetrical structure divided divided Figure Figure 1. 1. Topview view (x-zplane) plane) ofthe the stacked-film architecture. architecture. It is is a symmetrical structure structure divided into a cell area, a BLC area, and a peripheral area. into into aa cell cell area, area, aa BLC BLC area, area, and and aaperipheral peripheralarea. area.

Figure 2. Side view (x-y plane) of Structure A showing a section of the stacked-film architecture along Figure 2. Side view (x-y plane) of Structure A showing a section of the stacked-film architecture along Figure Side view (x-y plane) of Structure A showing a section of the stacked-film architecture along the line2.A–A. the line A–A. the line A–A.

As shown in Figure 2, measuring points 1 and 3 are located close to the middle of the cell area (approximately 300 µm from the centerline) and the middle of the BLC area (approximately 640 µm from the centerline, respectively, and measurement point 2 is located near the junction between the cell and BLC areas (approximately 600 µm from the centerline).

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2.1.1. Mesh and Convergence 2.1.1. Mesh and Convergence As shown in Figures 1 and 2, because the structure is symmetrical and the model has a defined As shown Figures 1 and 2, because structure is symmetrical and the model has a defined vertical depth, in it can be simplified as a 2D the symmetry model. Since the thickness of each layer is very vertical depth, it can be simplified as a 2D symmetry model. Since the thickness of each layer is very different, we use the thinnest oxide layer as a reference to mesh the element size. In such a 2D plane different, use thewe thinnest oxide layer as a reference to the element such a 2D plane structure we analysis, use the element “PLANE183” inmesh the software. Leesize. [18]Insuggests that, by structure we use the element the software. Leemeshed [18] suggests that, by applying applyinganalysis, the “PLANE183” element,“PLANE183” the model in elements can be to quadrilaterals and, the “PLANE183” the results model elements be meshed to quadrilaterals and, subsequently, the subsequently, theelement, simulation will havecan greater accuracy. simulation results will have greater accuracy. 2.1.2. Boundary Conditions 2.1.2. Boundary Conditions We set frictionless support on the left side of the model (center axis) to limit the movement of We set frictionless on the left side of the model (center to limitit the of thea the selected boundarysupport in the x-direction; as the y-direction is freeaxis) to move, canmovement be considered selected boundary in theAs x-direction; as the y-direction is free move, it can be consistent, considered as a symmetric symmetric condition. the peripheral area structure is to continuous and shown in condition. As the peripheral area structure is continuous and consistent, as shown in Figures and 2, Figures 1 and 2, the right side of the model is also set to frictionless support. The temperature1 load is ◦C the rightto side thein model is also set to frictionless The temperature load is heated heated 350of °C accordance with the actual support. manufacturing conditions, then cooledtoto350 room in accordance with the actual manufacturing conditions, then cooled to room temperature. temperature. 2.1.3. Simplification of the Simulation 2.1.3. Simplification of the Simulation As the film is very thin (thickness = 100 Å at most, versus 7,300,000 Å for the wafer base), the As the film is very thin (thickness = 100 Å at most, versus 7,300,000 Å for the wafer base), the aspect ratio of the finite element model is very large. Thus, the long cell area in the consistent and aspect ratio of the finite element model is very large. Thus, the long cell area in the consistent and smooth structure can be shortened by Saint-Venant’s principle, while the film thickness remains smooth structure can be shortened by Saint-Venant’s principle, while the film thickness remains unchanged. In this way, the finite element model can be simplified to increase its analytical efficiency. unchanged. In this way, the finite element model can be simplified to increase its analytical efficiency. Figure 3 shows the stress distribution of a thin member modeled by Saint-Venant’s principle, Figure 3 shows the stress distribution of a thin member modeled by Saint-Venant’s principle, The member is stretched by the pulling force P received at its end. Consequently, the transverse The member is stretched by the pulling force P received at its end. Consequently, the transverse crosscross-section plane near the action location becomes a curved surface (segment 3). However, the section plane near the action location becomes a curved surface (segment 3). However, the crosscross- section slightly offset from the action spot can be regarded as a plane (segment 2), even under section slightly offset from the action spot can be regarded as a plane (segment 2), even under deformation. Since the stress distribution in the cross-section of the member is centrally concentrated deformation. Since the stress distribution in the cross-section of the member is centrally concentrated near the action location, it is almost uniform away from the action location (segment 1). near the action location, it is almost uniform away from the action location (segment 1).

Figure 3. 3. Saint-Venant’s Saint-Venant’s principle principleshowing showingthe thestress stressdistribution distributionof ofaaslim slimmember memberunder undertension tensionP.P. Figure

2.1.4. Simulating Simulatingthe theThin ThinFilm FilmStack StackProcess Process 2.1.4. As the the films films are arestacked stackedfrom fromthe thebottom bottomup, up,the thefilm filmisisannealed annealedbefore beforestacking. stacking. The The film film As stacking process is shown in Figure 4. To accurately simulate the stacking sequence, we apply the stacking process is shown in Figure 4. To accurately simulate the stacking sequence, we apply the special elements method [19]. special elements method [19]. Thespecial specialelements elements method implements the function of an element by modifying the The method [20][20] implements the function of an element by modifying the element element stiffness. When the first load sub-step of an element in the loading step is dormant or stiffness. When the first load sub-step of an element in the loading step is dormant or activated, the activated, the stateinisthe maintained in thestep. overall loadingthe step. Therefore, the dormant elements are state is maintained overall loading Therefore, dormant elements are invalidated rather invalidated rather than removed. than removed.

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Figure 4. Schematic of the film-stacking process. Each film is annealed before stacking and films are stacked from the bottom up.

Figure 4. Schematic of the film-stacking process. Each film is annealed before stacking and films are Figure 4. Schematic of the film-stacking process. Each film is annealed before stacking and films are stiffness of a dormant element is multiplied by a very small reduction factor. The element stackedThe from the bottom up. stacked bottom up. loadfrom (e.g., the pressure and temperature) related to the dormant element is set to zero in the load vector. The mass, damping, strain, and stress stiffening of the dormant element are also set to zero. The The stiffness of a dormant element is multiplied by a very small reduction factor. The element dormant elements are not included inisthe model, but by areamerely reactivated. When reactivated, the The stiffness of and a dormant element multiplied very small reduction factor. The element load (e.g., pressure temperature) related to the recover dormant element isvalues. set toAs zero in the load vector. stiffness, mass, damping, and load of the element their original the reactivated load (e.g., pressure and temperature) related to the dormant element is set to zero in the load The mass, damping, strain, and stress stiffening of the dormant element are also set to zero. The elements have no strain history, continuous assembly, and annealing can be simulated. vector. The mass, damping, strain, and stress stiffening of the dormant element are also set to zero. dormant elements are not the model, but arelayer merely reactivated. When reactivated, the Figure 5 shows theincluded simulationinresults in the epitaxial (leakage current measurement layer) The dormant are model. not inobserved the model, but merely reactivated. When reactivated, of mass, theelements scaled-down It can that the are stress trend in thevalues. scaled-down model stiffness, damping, andincluded load of be the element recover their original As the reactivated the stiffness, mass, damping, and load of the element recover their original As the reactivated maintains a similar elements have no strain distribution. history, continuous assembly, and annealing can values. be simulated. Table showshistory, the totalcontinuous number of elements when theannealing model is reduced to 1/10 of the original elements have no 1strain assembly, and can be simulated. Figure 5 shows the simulation results in the epitaxial layer (leakage current measurement layer) length. When the the element number is reduced, the computation time is likely to be measurement faster. Without layer) Figure 5 shows simulation results in the epitaxial layer (leakage current of the compromising scaled-downstress model. It can be observed that the stress trend in the scaled-down model trends, this method enhances the computational efficiency of the finite element ofmaintains the scaled-down model. It can be observed that the stress trend in the scaled-down model maintains a similar distribution. simulation. a similar distribution. Table 1 shows the total number of elements when the model is reduced to 1/10 of the original

length. When the element number is reduced, the computation time is likely to be faster. Without compromising stress trends, this method enhances the computational efficiency of the finite element simulation.

Figure 5. Stress distribution in the BLC area computed by the scaled down model.

Figure 5. Stress distribution in the BLC area computed by the scaled down model.

Table 1 shows the total number of elements when the model is reduced to 1/10 of the original length. When the element number is reduced, the computation time is likely to be faster. Without compromising stress trends, this method enhances the computational efficiency of the finite element simulation. Figure 5. Stress distribution in the BLC area computed by the scaled down model.

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Table 1. Number of elements of different model length. Model Length

Number of Elements

Original 1/5 1/10

207,605 108,962 57,754

2.1.5. Discussion on the Stress Singularity Elasticity theory is included in the finite element model if there is a geometric structure problem that will cause stress concentration (i.e., the stress is extremely large) at the corresponding position, called the stress singularity point. This is particularly common at the corners. Hence, we will determine if the peak stress in the simulation results in Figure 5 is a stress singularity point. To do this, we mesh the epitaxial layer elements to a smaller size; if the stress subsequently converges (i.e., the stress becomes smaller), it can be judged as a stress singularity. The results of this evaluation are shown in Table 2: when the epitaxial layer element size was changed from 0.2 µm to 0.05 µm, the peak stress distribution was almost exactly the same. Therefore, we can confirm that these peak stresses are not stress singularity points. Table 2. List of peak stress under different element sizes. Element Size (µm)

Stress Peak 1 Peak 2 Peak 3

0.2

0.15

0.1

0.05

225.2 MPa 182.3 MPa 154.7 MPa

225.2 MPa 182.3 MPa 154.7 MPa

225.1 MPa 182.3 MPa 154.6 MPa

225.1 MPa 182.2 MPa 154.6 MPa

2.2. Correction of Material Parameters In the CIS-stack manufacturing process, each material layer is heated and annealed at different temperatures. Therefore, residual stress after the stack process changes the thin-film material properties. To increase the simulation accuracy, the material parameters were corrected by a single-layer stack. In actual manufacturing conditions, a silicon-based wafer is heated, and the film layers are formed at high temperature (165, 220, and 350 ◦ C, from bottom to top), then cooled to room temperature. Next, the wafer is warped and its curvature radius is measured by an ASET SFx100 (KLA-Tencor, Milpitas, CA, USA) measurement instrument. Finally, the film stress is calculated by the Stoney formula [21]. The adjusted parameters of the thin film material parameters shown in Table 3. The Poisson’s ratio, Young’s modulus, and thermal expansion coefficient are corrected by fitting the stress-material parameter correlation curve, and substituting the measured film stress in the curve. Figure 6 is a flow chart of the correction process of the material parameters. Table 3. List of thin film material properties. Materials

E (GPa)

Poisson Ratio

CTE (ppm/◦ C)

Oxide SiN Epitaxial silicon Silicon chip Inter metal dielectric (IMD)

73 130 190 160 11.7

0.17 0.3 0.28 0.28 10.1

0.55 10 2.33 3 1.16

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Figure 6. Flowchart for correction of the material parameters. Figure Figure 6. 6. Flowchart Flowchart for for correction correction of of the the material material parameters.

3. Simulation Analysis and Experimental Measurements 3. 3. Simulation Simulation Analysis Analysis and and Experimental Experimental Measurements Measurements Figure presentsthe thesimulation simulation and experimental flow of optimization. the optimization. optimization. There were three Figure presents the simulation and experimental flow of the There Figure 777 presents and experimental flow of the There were were three three types types of film structures: structures: A (Figure (Figure 2), B B8), (Figure 8), and C C (Figure (Figure 9). The Thebetween difference between these types film A 2), (Figure and 9). difference between of filmof structures: A (Figure 2), B (Figure and C 8), (Figure 9). The difference these types isthese that types is that structures B and C have a larger groove (15 μm) in the BLC region compared to structure types is that structures B and C have a larger groove (15 μm) in the BLC region compared to structure structures B and C have a larger groove (15 µm) in the BLC region compared to structure A; in addition, A; in addition, the thickness of the the top SiNoflayer layer at the theCtop top of structure structure C is is decreased decreased from 500 500 A Å and (as in in A; addition, the SiN at of C from Å (as thein thickness ofthe the thickness SiN layer of at structure is decreased from 500 Å (as in structures B) structures A and B) to 350 Å. The stress was observed and the leakage current was measured. Figures structures A and B) to 350 Å. The stress was observed and the leakage current was measured. Figures to 350 Å. The stress was observed and the leakage current was measured. Figures 10 and 11 show the 10 and 11 11 stress showresults the simulated simulated stress results results of of in thethe thin-film structures in the cell cell and and BLC areas, 10 and show the stress the thin-film the areas, simulated of the thin-film structures cell and structures BLC areas, in respectively. TheBLC measured respectively. The measured leakage currents, provided by Taiwan Semiconductor Manufacturing respectively. The measured leakage currents, providedManufacturing by Taiwan Semiconductor Manufacturing leakage currents, provided by Taiwan Semiconductor Co., Ltd. (Hsinchu, Taiwan), Co., Ltd. (Hsinchu, Taiwan), are listed in Table 4. Co., Ltd. (Hsinchu, Taiwan), are listed in Table 4. are listed in Table 4.

Figure 7. 7. Flowchart Flowchart of of the the simulation simulation process. process. Figure Figure 7. Flowchart of the simulation process. Table 4. 4. Leakage Leakage current current data data measured measured by by Taiwan Taiwan Semiconductor Semiconductor Manufacturing Manufacturing Co., Co., Ltd. Ltd. Table Table 4. Leakage current data measured by Taiwan Semiconductor Manufacturing Co., Ltd.

/s) Electrical Data Data (e (e−−/s) Electrical − /s) Electrical Data (e Point 11 Point 22 Point 33 Point Point Point Structure A 74.8 9 8.31 Point 1 Point 2 Structure A 74.8 9 8.31 Structure B B 74.8 14.9 1.8 Structure 14.9 88 9 1.8 Structure C 11.7 10.1 1.16 14.9 8 Structure C 11.7 10.1 1.16

Film Structure Structure Film Film Structure Structure A Structure B Structure C

11.7

10.1

Point 3 8.31 1.8 1.16

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Figure 8. Side view (x-y plane) of Structure B showing the section of the stacked-film architecture Figure 8. Side view (x-y plane) of Structure B showing the section of the stacked-film architecture alongFigure the line A–A.view Figure 8. Side view (x-y plane) of Structure B showing the section of the stacked-film architecture along 8. line Side along the A–A. (x-y plane) of Structure B showing the section of the stacked-film architecture the line A–A. along the line A–A.

Figure 9. Side view (x-y plane) of Structure C showing the section of the stacked-film architecture Figurethe 9. line SideA–A. view (x-y plane) of Structure C showing the section of the stacked-film architecture along Figure 9.9. Side view (x-y Figure Side view (x-y plane) plane) of of Structure Structure C C showing showing the the section section of of the the stacked-film stacked-film architecture architecture along the line A–A.

along alongthe theline lineA–A. A–A.

Figure 10. Simulated stress distributions in the cell areas. Figure 10. Simulated stress distributions in the cell areas.

Figure 10. 10. Simulated Simulated stress stress distributions distributions in in the the cell cellareas. areas. Figure

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Figure 11. Simulated stress distributions in the BLC areas.

Figure 11. Simulated stress distributions in the BLC areas.

In both experimental and simulated results, the stress is related to leakage current in the BLC area. Low stress induces a small total leakage at the three measurement points (Figure 2). Inarea. In both experimental and simulated results,current the stress is related to leakage current in the BLC the cell area, as the structure is smooth and slightly changed, the stress distributions are smooth Low stress induces a small total leakage current at the three measurement points (Figure 2). Inand the cell almost invariant, is sosmooth the stress–leakage-current relationship cannot be judged. are smooth and almost area, as the structure and slightly changed, the stress distributions It can be observed from the simulation results that both the stress and the leakage current of invariant, so the stress–leakage-current relationship cannot be judged. structures B and C are lower than those in structure A, perhaps because the increased groove in the It can be observed from the simulation results that both the stress and the leakage current of BLC region allows the stress to dissipate. The minor stress differences between structures B and C structures B and Cdifferent are lower than those in structure perhaps the increased groove in the are due to the thicknesses of the SiN layers A, at the top of because each structure.

BLC region allows the stress to dissipate. The minor stress differences between structures B and C are due to4.the different thicknesses of the SiN layers at the top of each structure. Results and Discussion

The simulation results were well correlated with the experimental measurements; when the stress was low, the measured leakage current was also low. We now investigate this trend. The simulation performs a were static well structural analysis, and material properties are assumed. The The simulation results correlated with thelinear experimental measurements; when the stress behavior during processing, example, concentration of doped semiconductor material the was low, the measured leakage for current wasthe also low. We now investigate this trend. The and simulation applied stress, is not considered. distribution in the entireare film structureThe is evaluated performs a static structural analysis,The andstress linear material properties assumed. behaviorafter during its temperature has decreased to room temperature. processing, for example, the concentration of doped semiconductor material and the applied stress, Many studies [22–24] have applied 4-PBT or forced wafer bending, in which the electronic is not considered. The stress distribution in the entire film structure is evaluated after its temperature characteristics of the elements are altered by an external mechanical stress. However, the applied has decreased to room temperature. stress is typically estimated over a wide range. These approaches cannot obtain the actual stress Many studies have 4-PBT or forced wafer in which the electronic distribution on [22–24] a small area or aapplied thin layer of a multilayered film onbending, a thick substrate. Therefore, the characteristics the present elements are is altered external mechanical stress. However, applied stress structure of in the study based by on an backside illumination (BSI) technology. We the measured the is typically estimated a wide range.transistor These approaches cannot obtain the actual stress distribution leakage current ofover the silicon-based at the end rather than at the transistor channel (as in previous explain the correlation stress and leakage current, we focus on a small areastudies). or a thinTherefore, layer of atomultilayered film on a between thick substrate. Therefore, the structure in the on fundamental solid-state quantum theory and the stress-induced defects. present study is based on backside illumination (BSI) technology. We measured the leakage current

4. Results and Discussion

of the silicon-based transistor at the end rather than at the transistor channel (as in previous studies). 4.1. Solid-State Quantum Theory Therefore, to explain the correlation between stress and leakage current, we focus on fundamental solid-statetheory module comprises tens of thousands of atomic systems. During atomic interactions, solid-stateAquantum and the stress-induced defects. the original division of the electrons’ energies becomes a banded higher-energy distribution (i.e., an energy band). In the cut-off region of an element, current is still generated by weak reversal 4.1. Solid-State Quantum Theory development. In addition, the energy of the carriers follows a Boltzmann distribution. The highAenergy solid-state module tens of thousands of atomic systems. During atomic interactions, carriers jump comprises into the conduction band, generating current. Tensile stress increases the the original division of the energies banded higher-energy distribution (i.e., an interatomic distance andelectrons’ reduces the bindingbecomes energy ofathe electrons to their atoms. Consequently, energy In the cut-off and region of an element, generated by weak reversal theband). energy gap is narrowed the electrons are easilycurrent released is as still free electrons. Conclusively, stress pure siliconfollows crystal changes the interatomic distance and the development. In addition, theapplied energyto ofathe carriers a Boltzmann distribution. The high-energy atomic binding force on the electrons. effects decrease energystress gap inincreases the siliconthe crystal, and carriers jump into the conduction band,These generating current.the Tensile interatomic increase the probability of electrons transiting from the valence to the conduction band room gap distance and reduces the binding energy of the electrons to theirband atoms. Consequently, the at energy temperature. On the contrary, when the interatomic distance is shortened under compressive stress,

is narrowed and the electrons are easily released as free electrons. Conclusively, stress applied to a pure silicon crystal changes the interatomic distance and the atomic binding force on the electrons. These effects decrease the energy gap in the silicon crystal, and increase the probability of electrons transiting from the valence band to the conduction band at room

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temperature. the contrary, when the interatomic distance is shortened under compressive Sensors 2017,On 17, 1004 10 of 15stress, the energy gap increases with the increasing atomic binding force on the electrons, and the electrons the likely energytogap increases the increasing are less jump to thewith conduction band.atomic binding force on the electrons, and the electrons are less likely to jump to the conduction band. The energy band gap is shown in Figure 12. As the atoms approach each other, the energy levels of The energy band gap is shown in Figure 12. As the atoms approach each other, the energy levels the 3s and 3p states initially split into energy bands. In closer proximity, the 3s and 3p electrons interact of the 3s and 3p states initially split into energy bands. In closer proximity, the 3s and 3p electrons and ainteract mixed and band is formed. the interatomic distance narrows further, the energy a mixed bandAs is formed. As the interatomic distance narrows further, the band energyagain bandsplits into two energy bands. Finally, at distance a (defined as the interatomic distance at equilibrium), 0 at distance a0 (defined as the interatomic distance at the again splits into two energy bands. Finally, upper and lower the energy levels are separated by the band gapenergy (Eg ). band gap (Eg). equilibrium), upper and lower energy levels are energy separated by the

Figure 12. Atomic band structures of silicon [25].

Figure 12. Atomic band structures of silicon [25].

4.2. Defects Caused by High Stress

4.2. Defects Caused by High Stress

The continued miniaturization of semiconductor device dimensions presents various challenges;

for instance, reducing the high gate-pole leakage current induced by a very thin dielectric layer, The continued miniaturization of semiconductor device dimensions presents various challenges; maintaining high rate of the turn-on and -off currents, and overcoming the short channel effects andlayer, for instance, reducing the high gate-pole leakage current induced by a very thin dielectric high power dissipation. maintaining high rate of the turn-on and -off currents, and overcoming the short channel effects and These problems have been solved by innovative technologies such as strain engineering, shallow high power dissipation. junction engineering, low contact resistance, and multilayered interconnections. Strain engineering These problems have been solved by innovative technologies such as strain engineering, shallow can improve the channel carrier mobility. junction engineering, low contact resistance, and multilayered interconnections. Strain engineering The contact etch-stop layer (CESL) is a popular type of local strained silicon technique. The can improve the channel carrier strained silicon technique, usedmobility. to cover different materials, causes lattice mismatch. The consequent The contact etch-stop layer (CESL) a popular type of local strained silicon technique. different stresses in the channel change theis component characteristics. The strained silicon technique, used to cover different materials, causes lattice This mismatch. The stress imposed by local strained silicon forms strain channels in a component. process The is exploited in shallow trench isolation, silicon germanium (SiGe), source and consequent different stresses in the channelsilicidation, change theCESL, component characteristics. drainstress (S/D) imposed processes,by and other related silicon structures. The local strained forms strain channels in a component. This process is CESL above the isolation, gate generates stress in CESL, the channel, which increases(SiGe), the carrier mobility. exploitedThe in shallow trench silicidation, silicon germanium source and drain However, it also damages the elements to some extent, and defects may occur in the gate oxide and (S/D) processes, and other related structures. at the silicon/substrate interface. The CESL above the gate generates stress in the channel, which increases the carrier mobility. The effect of CESL on the components was investigated through a series of experiments [12–14]. However, also damagessize thewas elements to some extent, and defects may occur in the gate and at Here, it the component set to W/L = 10 μm/10 μm, and the CESL layer conditions wereoxide varied the silicon/substrate interface. as low tensile 380 Å, high tensile 700 Å, and high compressive 700 Å. The silicon on insulator (SOI) The effectwas of CESL on theeach components was investigated through series of experiments thickness fixed under CESL condition. The SOI thickness was athen varied as 500 Å, 700 [12–14]. Å, Here,and the900 component W/L = 10 µm/10 µm, and the conditions Å, and the size ID–VDwas and set ID–Vto G diagrams were plotted. To obtain theCESL currentlayer and voltage data, were weas employed a semiconductor an inductive–capacitive analyzer and varied low tensile 380 Å, high parametric tensile 700analyzer, Å, and high compressive 700impedance Å. The silicon on insulator a low leakage current matrix converter. From the curves, we observed the changes in the device (SOI) thickness was fixed under each CESL condition. The SOI thickness was then varied as 500 Å, characteristics. 700 Å, and 900 Å, and the ID –VD and ID –VG diagrams were plotted. To obtain the current and Figures 13 and 14 clarify the effect of strained silicon on the electrical properties of the elements. voltage data, we employed a semiconductor parametric analyzer, an inductive–capacitive impedance Figure 13a shows ID–VD diagrams of NMOS. The device with a high tensile force effectively analyzer and a low leakage current matrix converter. From the curves, we observed the changes in the increased the element driving current. The PMOS produced comparable results, as shown in Figure device characteristics. 13b. For NMOS, a slightly higher gate leakage was found in the device with a high tensile force; this Figures 13 and 14 clarify the effect of strained silicon on the electrical properties of the elements.

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Figure 13a shows ID –VD diagrams of NMOS. The device with a high tensile force effectively increased the element driving current. The PMOS produced comparable results, as shown in Figure 13b. For NMOS, a slightly this Sensors 2017, 17, 1004 higher gate leakage was found in the device with a high tensile force;11 of 15is due to the factSensors that, 2017, under high tensile stress, the leakage current increases and defects are generated 17, 1004 11both of 15 Sensors 2017, 17, 1004 11 of 15 due to the that, under2 interface, high tensile leakage14b. current increases and defects are in theischannel andfact at the Si/SiO as stress, shownthe in Figure generated in channel and at the Si/SiO 2 interface, asthe shown in Figure is dueboth tothe thethe fact that, under high tensile stress, the leakage current increases and defects are However, in component leakage current, difference in14b. the gate current is due to the fact PMOS that, under high tensile stress, the leakage current increases and leakage defects are However, in thein PMOS component leakage current, the difference inin the gate leakage current is generated both the channel and at the Si/SiO 2 interface, as shown Figure 14b. is notgenerated discernible; due toand theatuse a traditional device with a14b. low tensile force in this both this in theischannel theof Si/SiO 2 interface, SiN as shown in Figure not discernible; this in is the duePMOS to thecomponent use of a traditional SiN device with a low tensile force in current this However, leakage current, the difference in the gate leakage is experiment rather than compressive ascurrent, shownthe in Figure 15.in the gate leakage However, in thelow PMOS componentforce, leakage difference current is experiment rather than low force, shown in Figure 15. not discernible; this is compressive due to the use of as a traditional SiN device with a low tensile force in this not discernible; this is due to the use of a traditional SiN device with a low tensile force in this experiment rather than low compressive force, as shown in Figure 15. experiment rather than low compressive force, as shown in Figure 15.

Figure 13. Comparison of ID - VD diagrams in conducting elements subjected to different layer strains:

Figure 13. Comparison of ID - VD diagrams in conducting elements subjected to different layer strains: (a) NMOS and PMOS [12].of ID - VD diagrams in conducting elements subjected to different layer strains: Figure 13.(b) Comparison Figureand 13. Comparison of ID - VD diagrams in conducting elements subjected to different layer strains: (a) NMOS (b) PMOS [12]. (a) NMOS and (b) PMOS [12]. (a) NMOS and (b) PMOS [12].

Figure 14. Comparison of ID and IG in NMOS non-conducting elements subjected to different layer diagram (b)IDIGand –VGNMOS [12].non-conducting strains: (a) ID–V 14.G Comparison of Idiagram G in NMOS elements subjectedtotodifferent different layer layer Figure 14.Figure Comparison of IDand and in non-conducting elements subjected Figure 14. Comparison of ID andGIG in NMOS non-conducting elements subjected to different layer D –V G diagram and (b) I G –V G diagram [12]. strains: (a) I strains: (a) I –V diagram and (b) I –V diagram [12]. D G G G strains: (a) ID–VG diagram and (b) IG–VG diagram [12].

Figure 15. Comparison of ID and IG in PMOS non-conducting elements subjected to different layer diagram andof (b)IDIGand –VG diagram [12].non-conducting elements subjected to different layer strains: (a) ID–V Figure 15.G Comparison IG in PMOS Figure 15. Comparison of ID and IG in PMOS non-conducting elements subjected to different layer Figure 15.strains: Comparison ID andand IG in non-conducting elements subjected to different layer (b)PMOS IG–VG diagram [12]. (a) ID–VGofdiagram strains: (a) ID–VG diagram and (b) IG–VG diagram [12].

For(a) understanding theand defect by CESL[12]. which was observed in these devices, studies on strains: ID –VG diagram (b)induced IG –VG diagram the densities of oxide-trapped charges and interface traps in transistors haveinbeen and on For understanding the defect induced by CESL which was observed theseconducted devices, studies For understanding the defect induced by CESL which was observed in these devices, studies on the densities of oxide-trapped charges and interface traps in transistors have been conducted and the densities of oxide-trapped charges and interface traps in transistors have been conducted and

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reported in [13,14]. These investigations were made by two measurement methods: charge pumping and flicker noise. Sensors 2017, 17, 1004 12 of 15 In this case, low-frequency noise was inspected, as shown in Figure 16. Results indicate higher levels of oxide and interface defects, especially in the high-tensile device with a larger induced stress. Higher and interface defectsinduced were found withwhich low-frequency noise, in the high For oxide understanding the defect by CESL was observed in especially these devices, studies compressive PMOS. on the densities of oxide-trapped charges and interface traps in transistors have been conducted and Sensors 2017, 17, 1004 12 of 15 The in charge-pumping measurementwere was amade useful to confirm the CESL-induced interface reported [13,14]. These investigations bymethod two measurement methods: charge pumping defect. For noise. NMOS, a higher nit was observed in higher stress devices (especially in the compression and flicker reported in [13,14]. These investigations were made by two measurement methods: charge pumping devices), ascase, shown in Figure 17a. This effect was also identified by charge-pumping current (Icp) in In this and flicker noise.low-frequency noise was inspected, as shown in Figure 16. Results indicate higher NMOS, which revealed a higher Icp,especially especiallyininthe higher-stress tensile and compressive devices, as levels oxide and interface defects, a largerindicate induced stress. Inofthis case, low-frequency noise was inspected,high-tensile as shown indevice Figurewith 16. Results higher shown in Figure 17b. The results confirm that high stress/strain mechanisms cause defects inhigh the Higher oxide and interface defects were found with low-frequency noise, especially in the levels of oxide and interface defects, especially in the high-tensile device with a larger induced stress. elements. compressive Higher oxidePMOS. and interface defects were found with low-frequency noise, especially in the high compressive PMOS. The charge-pumping measurement was a useful method to confirm the CESL-induced interface defect. For NMOS, a higher nit was observed in higher stress devices (especially in the compression devices), as shown in Figure 17a. This effect was also identified by charge-pumping current (Icp) in NMOS, which revealed a higher Icp, especially in higher-stress tensile and compressive devices, as shown in Figure 17b. The results confirm that high stress/strain mechanisms cause defects in the elements.

Figure 16. 16. Influence Influence of of strain strain on on flicker flicker noise. noise. Comparison Comparison of of the the effects effects of of highhigh- and and low-tensile low-tensile and and Figure high-compressive CESL on defects in (a) NMOS elements and (b) PMOS elements [13]. high-compressive CESL on defects in (a) NMOS elements and (b) PMOS elements [13].

The charge-pumping measurement was a useful method to confirm the CESL-induced interface defect. For NMOS, a higher nit was observed in higher stress devices (especially in the compression devices), as shown in Figure 17a. This effect was also identified by charge-pumping current (Icp) in NMOS, which revealed a higher Icp, especially in higher-stress tensile and compressive devices, as shown 17b. The results confirm that high stress/strain mechanisms cause defects Figurein16.Figure Influence of strain on flicker noise. Comparison of the effects of high- and low-tensile and in the elements. high-compressive CESL on defects in (a) NMOS elements and (b) PMOS elements [13].

Figure 17. Influence of layer strain on defects in the charge pumping experiment. (a) Icp currents and (b) charge density at the interface (converted from the Icp currents), in NMOS devices subjected to different stresses [13].

5. Verification of the Relation According to the previous simulation results and the experimental data, both the film structure and the material affect the stress distribution more significantly in the BLC area than in the cell area. Lowering the stress in the BLC reduced thepumping measured leakage (a) current; this and result is Figure 17. Influence of layer strain on region defects in the charge experiment. Icp currents Figure 17. Influence of layer strain on defects in the charge pumping experiment. (a) Icp currents and supported by theory theinterface literature. (b) charge densityand at the (converted from the Icp currents), in NMOS devices subjected to (b) charge density at the interface (converted from the Icp currents), in NMOS devices subjected to Here we verify this trend by simulation and an experiment. The simulation is based on structure different stresses [13]. different stresses [13]. C with passivation layer thicknesses of 2T and 4T, where T is the thickness of the original passivation 5. Verification layer 500 Å. of the Relation According to the previous simulation results and the experimental data, both the film structure and the material affect the stress distribution more significantly in the BLC area than in the cell area. Lowering the stress in the BLC region reduced the measured leakage current; this result is supported by theory and the literature. Here we verify this trend by simulation and an experiment. The simulation is based on structure C with passivation layer thicknesses of 2T and 4T, where T is the thickness of the original passivation

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5. Verification of the Relation According to the previous simulation results and the experimental data, both the film structure and the material affect the stress distribution more significantly in the BLC area than in the cell area. Lowering the stress in the BLC region reduced the measured leakage current; this result is supported by theory and the literature. Sensors 2017,we 17, verify 1004 this trend by simulation and an experiment. The simulation is based on structure 13 of 15 Here C with passivation layer thicknesses of 2T and 4T, where T is the thickness of the original passivation layer Figure 500 Å. 18 shows the simulation result in the BLC area. The stress and the measured leakage current clearly increased with increasing thickness the The passivation layer. 5 shows the Figure 18 shows the simulation result in the BLCofarea. stress and the Table measured leakage measured leakage currents in structure C with different passivation layer thicknesses. From the current clearly increased with increasing thickness of the passivation layer. Table 5 shows the measured previous results, it shows Cthat groove can makelayer thethicknesses. stress drop, the the leakage current at leakage currents in structure withthe different passivation From previous results, measurement point 3 has an inverse trend, which may be as the increase in the thickness of the it shows that the groove can make the stress drop, the leakage current at measurement point 3 has passivation layerwhich but width ofas the (15inμm) remains constant cause thelayer stressbut around an inverse trend, may be thegroove increase the thickness of the passivation width the of groove has(15 different changesconstant and measurement point around 3 being located closer the groove. However, the groove µm) remains cause the stress the groove hastodifferent changes and from the total leakage point of view, these results are consistent theleakage previously-observed measurement point 3 being located closer to the groove. However, from with the total point of view, simulation and experimental trends. these results are consistent with the previously-observed simulation and experimental trends.

Figure18. 18.Simulated Simulatedstress stressdistributions distributionsin instructures structureswith withdifferent differentpassivation passivationlayer layerthicknesses. thicknesses. Figure Table 5. Measured leakage current data in Structure C with different passivation layer thicknesses. Table 5. Measured leakage current data in Structure C with different passivation layer thicknesses.

Film Structure Structure C Structure 2T Structure 4T

Film Structure StructurePoint C 1 11.7 Structure 2T 14.6 Structure 4T 15.8

Electrical Data (e−/s) − Point 1 Electrical PointData 2 (e /s) Point 3 Point 2 11.7 10.1 1.16 14.6 1310.1 0.9 13 15.8 18.7 0.84 18.7

Point 3 1.16 0.9 0.84

6. Conclusions 6. Conclusions We applied finite element analysis to the CMOS film-stacking process. The global and local We applied finite analysis to the CMOS film-stacking The globalof and stress distributions in element the CIS thin-film structures were simulated process. during the cooling thelocal filmsstress from distributions in the CIS thin-film structures were simulated during the cooling of the films from high high temperature to room temperature. Additionally, the finite element model was simplified to temperature room temperature. Additionally, finite element model was corrected simplified and to increase the increase thetoefficiency of the calculation; the the material parameters were the actual efficiency of the calculation; the material parameters corrected and the actual stacking sequence stacking sequence process was simulated to increasewere accuracy. process was simulated to increase accuracy. The simulation results confirmed different stress magnitudes and distributions in film stacks simulation results confirmed stress and distributions in film stacks withThe different architectures. Low stressdifferent in the BLC areamagnitudes induces a small leakage current; conversely, with different architectures. Low stress in the BLC area induces a small leakage current; conversely, high stress causes a high leakage current. As the cell area structure is smooth and robust, the stress high stress causes a high leakage Asdiscern the cellany arearelationship structure isbetween smooth and robust, theleakage stress distributions are smooth and toocurrent. similar to structure and distributions are smooth and toodata similar to cell discern between structure andcoupling. leakage current. To obtain more precise in the area,any we relationship must simulate the electro–thermal The observed trends in the BLC area were related to solid-state quantum theory and the influence of high stress was attributed to defects generated in the stressed materials. Both discussions are consistent. Simulations of the BLC area or CESL can improve the stack architecture, thus reducing the leakage current and improving the electronic characteristics of the elements. In industrial practice,

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current. To obtain more precise data in the cell area, we must simulate the electro–thermal coupling. The observed trends in the BLC area were related to solid-state quantum theory and the influence of high stress was attributed to defects generated in the stressed materials. Both discussions are consistent. Simulations of the BLC area or CESL can improve the stack architecture, thus reducing the leakage current and improving the electronic characteristics of the elements. In industrial practice, simulation studies can shorten the technological development time, reduce the experimental cost outlay, and increase the yield of the finished products. Acknowledgments: The work is supported by Taiwan Semiconductor Manufacturing Company Limited “TSMC JDP Application” and the project title is “Simulation Analysis of BSI/Image Sensor Technology”. Author Contributions: Kuo-Tsai Wu researched the literature, conceived the study concepts, designed the simlation method, carried out the simulation, analyzed the simulation results, and took charge of the entire manuscript. Sheng-Jye Hwang and Huei-Huang Lee assisted with the integrity of the entire study, provided the crucial intellectual support, and revised the manuscript. Conflicts of Interest: The authors declare no conflict of interest.

References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

12. 13.

14. 15. 16. 17.

18.

Hsu, T.H. The Study of Advanced Technologies and Novel Structures for High Performance Deep Submicron CMOS Image Sensors. Ph.D. Thesis, National Cheng Kung University, Tainan, Taiwan, 2005. Cammarata, R.C. Surface and interface stress effects in thin films. Prog. Surf. Sci. 1994, 46, 1–38. [CrossRef] Spaepen, F. Interfaces and stresses in thin films. Acta Mater. 2000, 48, 31–42. [CrossRef] Nix, W.D.; Clement, B.M. A mechanism for intrinsic tensile stresses in the thin films. J. Mater. Res. 1999, 14, 3467–3473. [CrossRef] Nix, W.D.; Doerner, M.F. Stresses and deformation processes in thin films on substrates. Crit. Rev. Solid State 1998, 14, 225–268. Nix, W.D. Mechanical properties of thin films. Metall. Mater. Trans. A 1999, 20, 2217–2245. [CrossRef] Wang, T.J.; Ko, C.H.; Chang, S.J.; Wu, S.L.; Kuan, T.M.; Lee, W.C. The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs. IEEE Trans. Electron Devices 2008, 55, 572–577. [CrossRef] Rueda, H.A. Modeling of Mechanical Stress in Silicon Isolation Technology and It’s Influence on Device Characteristics. Ph.D. Thesis, University of Florida, Gainesville, FL, USA, 1999. Lo, G.Q.; Kwong, D.L.; Lee, S. Reliability characteristics of metal-oxide-semiconductor capacitors with chemical vapor deposited Ta2 O5 gate dielectrics. Appl. Phys. Lett. 1993, 62, 973–975. [CrossRef] Tsuchiya, T.; Sato, Y.; Tomizawa, M. Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs. IEEE Trans. Electron Devices 1998, 45, 1116–1121. [CrossRef] Lai, C.M.; Fang, Y.K.; Yeh, W.K.; Lin, C.T.; Chou, T.H. The Investigation of post-annealing-Induced Defects Behavior on 90-nm In-Halo nMOSFETs with Low-Frequency Noise and Charge-Pumping Measuring. IEEE Electron Device Lett. 2007, 28, 142–144. [CrossRef] Wang, C.A. The Investigation of Characteristic and Reliability for 90 nm SOI CMOSFETs with Strain Technology. Master’s Thesis, National University of Kaohsiung, Kaohsiung, Taiwan, 2007. Chen, J.Y.; Wang, C.A.; Yeh, W.K. The impact of strain technology on device performance and reliability for sub-90 nm FUSI SOI MOSFETs. In Proceedings of the IEEE Conference on Electron Devices and Solid-State Circuits, Tainan, Taiwan, 20–22 December 2007. Chang, W.T.; Wang, C.C.; Lin, J.A.; Yeh, W.K. External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs. IEEE Trans. Electron Devices 2010, 57, 8. [CrossRef] Watanabe, T.; Park, J.H.; Aoyama, S.; Isobe, K.; Kawahito, S. Effects of Negative-Bias Operation and Optical Stress on Dark Current in CMOS Image Sensors. IEEE Trans. Electron Devices 2010, 57, 1512–1518. [CrossRef] Shcherback, I.; Belenky, A.; Yadid-Pecht, O. Empirical dark current modeling for complementary metal oxide semiconductor active pixel sensor. Opt. Eng. 2002, 41, 1216–1219. [CrossRef] Kim, D.H.; Park, S.; Jung, D.; Park, E.; Mhin, S.W.; Lee, C.W. Analysis of structural effect on mechanical stress at backside deep trench isolation using finite element method. Microelectron. Eng. 2016, 154, 42–47. [CrossRef] Lee, H.H. Meshing. In Finite Element Simulations with ANSYS Workbench 16; Schroff Development Corporation: Mission, KS, USA, 2015; pp. 350–361.

Sensors 2017, 17, 1004

19. 20. 21. 22. 23. 24.

25.

15 of 15

Chuang, W.C.; Lin, D.T.W.; Hu, Y.C.; Lee, H.L.; Cheng, C.H.; Chang, P.Z.; Quyen, N.B. A Method Integrating Optimal Algorithmand FEM on CMOS Residual Stress. J. Mech. 2014, 30, 123–128. [CrossRef] ANSYS Inc. Chapter 13: Element Birth and death, ANSYS Engineering Data Help for Workbench. In ANSYS Release15.0; ANSYS Inc.: Canonsburg, PA, USA, 2013. Stoney, G.G. The tension of metallic films deposited by electrolysis. Proc. R. Soc. A 1909, 82, 172–175. [CrossRef] Gallon, C.; Reimbold, G.; Ghibaudo, G.; Bianchi, R.A.; Gwoziecki, R. Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon. Solid State Electron. 2004, 48, 561–566. [CrossRef] Dong, J.W. Investigation of Strain-Temperature Stress on Rapid Thermal Ultra-Thin Gate Oxides. Master’s Thesis, National Taiwan University, Taipei, Taiwan, 2005. Wang, T.J.; Chen, H.W.; Yeh, P.C.; Ko, C.H.; Chang, S.J.; Yeh, J.; Wu, S.L.; Lee, C.Y.; Lee, W.C.; Tang, D.D. Effects of mechanical uniaxial stress on SiGe HBT characteristics. J. Electrochem. Soc. 2007, 154, 105–108. [CrossRef] Lee, W.I. Physics II, National Chiao Tung University OpenCourseWare. Available online: http://ocw.nctu. edu.tw/course_detail.php?bgid=1&gid=3&nid=383#.WCqUlS195pg (accessed on 29 April 2017). © 2017 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).