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Low-Voltage Organic Electronics Based on a Gate#Tunable Injection Barrier in Vertical Graphene–Organic Semiconductor Heterostructures Htay Hlaing, Chang-Hyun Kim, Fabio Carta, Chang-Yong Nam, Rob Barton, Nicholas Petrone, James Hone, and Ioannis Kymissis Nano Lett., Just Accepted Manuscript • DOI: 10.1021/nl5029599 • Publication Date (Web): 17 Dec 2014 Downloaded from http://pubs.acs.org on December 23, 2014
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Low-Voltage Organic Electronics Based on a Gate‒ Tunable Injection Barrier in Vertical Graphene– Organic Semiconductor Heterostructures Htay Hlaing,*,†,‡ Chang-Hyun Kim,ǁ Fabio Carta,‡ Chang-Yong Nam,┴ Rob Barton,†,‡ Nicholas Petrone,§ James Hone,†,§ and Ioannis Kymissis*,†,‡
†
DOE Energy Frontier Research Center, ‡Department of Electrical Engineering, §Department of Mechanical Engineering, Columbia University, New York, New York 10027, United States ǁ
LPICM, Ecole Polytechnique, CNRS, 91128 Palaiseau, France
┴
Center for functional Nanomaterials, Brookhaven National Laboratory, Upton, New York 1197, United States
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KEYWORDS: Graphene, organic semiconductors, thin film transistors, low-voltage electronics
ABSTRACT: The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly-emerging layered materials has recently been demonstrated as a promising route towards novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices current modulation is accomplished by tuning the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. Nchannel devices fabricated with a thin layer of C60 show a room temperature on/off ratio > 104 and current density of up to 44 mAcm-2. Due to the ultra-short channel intrinsic to the vertical structure the device is fully operational at a driving voltage of 200 mV. A complementary pchannel device is also investigated and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.
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Novel device architectures based on heterostructures of graphene with semiconductor layers have recently attracted considerable interest due to their potential in a wide range of electronic and photonic applications.1-6 The key concept in these devices is to exploit the work function tunability of graphene via an external gate field to modulate the current flow across the graphene-semiconductor junction by adjusting the Schottky barrier height.7, 8 Transistor devices based on a vertical heterojunction of graphene with an inorganic semiconductor (n- and p-type Silicon),1 oxide semiconductor (n-type indium gallium zinc oxide)2, 3 and flakes of 2D layered materials (hexagonal boron nitride, molybdenum disulfide and tungsten disulfide)4-6 have been successfully fabricated with high on/off ratios, overcoming one of the limitations of planar graphene field-effect devices. Organic thin film transistors (OTFTs) with high current output at low driving voltage are highly desirable for many applications such as logic circuits and active matrix displays.9-11 However, the traditional planar field effect transistor (OFET) architecture requires high mobility organic semiconductors (µ >> 1 cm2V-1s-1) or implementation of short-channel length devices for low mobility organic semiconductors (µ < 1 cm2V-1s-1). This is especially problematic for n-type organic semiconductors which exhibit lower mobility compared to their p-type counterparts, introducing more complexity to fabricate complimentary circuits for low power applications. In order to address the transconductance and power limitation of planar OFETs, vertical organic thin film transistors (VOTFTs), where the channel length is determined by the active layer thickness, have been actively investigated.12-16 However, VOTFTs require high resolution patterning of source electrodes for gate-field penetration and therefore demand complex fabrication techniques. Transistors based on heterojunctions of graphene with organic semiconductors have fundamental advantages allowing them to be integrated in vertical
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architectures. Earlier efforts show promising but limited device performance.17,
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Aristizabal et al. have demonstrated a device based on pentacene, an archetypical p-type organic semiconductor, demonstrating an on/off ratio of ~ 4 with a gate bias of ± 50 V.18 Lemaitre, et al. demonstrated further device performance improvement using a higher mobility p-type semiconductor, dinaphtho-[2,3-b:2´,3´-f]thieno[3,2-b]thiophene, attaining an on/off ratio of ~103 with gate bias of ± 40 V and on-current density of ~2 mA/cm2 at a drain voltage of – 5V.17 Lemaitre delivered an additional improvement in device performance by introducing pores in the graphene, similar to the perforated source electrodes of other VOTFT concepts. Although these results are promising, development of both p- and n-type VOTFTs with enhanced device performance is essential for VOTFTs to be successfully employed in active matrix displays and low-power logic applications. Here, we demonstrate low-voltage complementary p- and n- channel vertical organic thin film transistors (VOTFTs) based on graphene-organic semiconductor heterojunctions with a simple, scalable and low-temperature fabrication process. Figure 1 (a) shows the schematic illustrations of the three-dimensional and cross-sectional view of the VOTFT device structure. The fabrication process starts with the deposition of a dielectric Al2O3 film (20 nm) on a pre-patterned ITO gate electrode on a glass substrate via atomic layer deposition. The monolayer graphene is grown by chemical vapor deposition and is patterned and transferred on top of the dielectric as a source electrode using well-established procedures.19, 20 The p- or n- type organic semiconductor layer is deposited at a base pressure of 10-6 Torr by thermal evaporation at 1 Ǻ/s, followed by the deposition of a gold (for the p-type device) or aluminium (for the n-type device) drain electrode via a shadow mask to create an ohmic contact to their respective semiconductors. The samples are kept at room temperature
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during the deposition. The device area is defined by the overlapping region between graphene and top metal electrode. The large-area fabrication of VOTFTs on a 50 x 50 mm2 transparent glass substrate is shown in the optical top-view image (Figure 1 (b)) with the inset showing the zoomed in image of individual device. The cross-sectional scanning electron microscope image (Figure 1 (c)) illustrates the vertical heterostructure of the graphene-organic semiconductor-metal stack in which the position of the graphene layer is indicated by a dashed line.
Figure 1. Vertical field-effect transistors based on graphene-organic semiconductor-metal heterojunctions. (a) Schematic illustration of the three-dimensional and cross-sectional view of the vertically stacked graphene-organic semiconductor-metal VOTFT. (b) Optical top view image of VOTFT devices fabricated on a 50 x 50 mm2 transparent glass substrate. Inset shows the zoomed-in image of an individual device. The device area (600µm x 800 µm) is defined by the overlap between the graphene and top Al electrode. (c) Cross-sectional scanning electron microscope image of the vertical heterostructure of graphene-organic semiconductor-metal stack. Graphene layer is indicated by dash line.
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Electrical transport studies of the VOTFTs based on the heterojunction of graphene and a 140 nm thick layer of C60 show that high on-current density can be achieved with a supply voltage of less than two volts using this archetypical n- type organic semiconductor. The electrical measurements are performed with the source electrode held at the ground potential while the drain and gate electrodes are biased with respect to the ground (see Figure 1 (a)). The transistor operation is demonstrated in Figure 2 (a), which shows the large modulation of the drain-source current (ID) by the gate voltage (VGS). The device can be fully turned on and off using a VGS of ± 6 V, with an on-off current ratio exceeding 104. The gate leakage current (IG) is also confined to the nano-ampere range. Due to the vertical structure with a thin semiconducting layer (corresponding to a lateral channel length of 140 nm), the VOTFT is operational even at the ultralow source-drain voltage (VDS) of 200 mV. In comparison, state of the art short-channel OFETs generally require a driving voltage around 1.5 V.21, 22 Another unique signature of this VOTFT is that ID can be tuned over an order of magnitude by varying VDS while maintaining a large on-to-off current ratio as shown in Figure 2 (b). Here, the on-state current density (Jon) and off-state current density (Joff) were calculated from the ID values on the transfer curves at VGS = 6 V and -6 V, respectively. Jon up to 44 mA/cm2 can be obtained at a low VDS of 2 V providing sufficient current density to drive OLEDs.23 Moreover, the VOTFT reaches a transconductance ( = ⁄ ) up to 25 µS (Figure 2(c)), ensuring a narrow gate-window switching capability. Our transconductance is among the highest reported values for solid-dielectric-gated organic transistors.24 The performance of VOTFTs can be improved further by optimizing the thickness of the gate dielectric as well as by perforating the graphene electrode.17
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Figure 2. (a) Semilogarithmic ID–VGS transfer characteristics of an n-type VOTFT measured at VDS of 0.2 and 0.5 V. IG is indicated by the dashed line. (b) On- and off-current density and (c) transconductance at various drain voltages measured at fixed gate voltage of 3V. The active area (A) of the transistor measured for this figure is 600 µm × 500 µm (3 × 10-3 cm2).
The underlying mechanism of our VOTFT operation can be described based on the gatetunable injection barrier at the bottom graphene/organic interface within a source-to-drain rectifying diode. In our device configuration, the diode is reverse biased when a positive voltage is applied at the aluminium electrode (the drain) while the graphene (the source) is grounded as indicated in Figure 3 (a). The strong rectification of diode current in the reverse bias regime (VDS > 0) is clearly observed for zero and negative gate voltages (VGS 0). Since the top aluminium electrode provides an ohmic (injecting) contact to C60, rectification at zero gate bias is mainly due to the electron injection barrier resulting from the energy level mismatch between the graphene workfunction (~ 4.6 eV)8 and the LUMO of C60 (~ 4.2 eV)25 at the bottom interface (see inset, Figure 4 (c)). When the negative gate voltage is applied, the work function of the 7 ACS Paragon Plus Environment
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graphene increases8 creating a larger injection barrier at the interface. Hence, the reverse current becomes negligibly small at VGS = - 6 V and a high current rectification is obtained. On the other hand, the work function of the graphene decreases as the gate is positively biased lowering the electron injection barrier height from the source into the organic layer. Consequently, the reverse current increases dramatically when VGS 0 as shown in Figure 3, explaining the n-type fieldeffect behavior in Figure 2 (a). A significant current modulation with VGS is also observed in the injection-limited forward bias region where the applied voltage is still smaller than the barrier height.
Figure 3. (a) Linear-scale ID–VDS output curves of an n-type VOTFT at various VGS values. VGS increases from -6 V to +6 V with a 2 V step in the direction indicated by the arrow. (b)
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Semilogarithmic plot of ID–VDS with the dashed line indicating the fit to obtain the diode ideality factor (n) at the injection-limited (exponential) regime. Because the electrostatics at a metal/semiconductor interface and associated charge-injection properties are temperature scaled, the response of the electrical behavior to a range of temperatures provides a direct access to such interface physics. Figure 4 (a) shows the variation of the output curves (diode characteristics) for the absolute temperature T from 180 to 320 K at a fixed VGS = -4 V. The observed overall enhancement of current with increasing T has two possible components; temperature activated mobility and a change in interface energetics. As the current in the high forward-bias regime is limited by the conductivity of the semiconducting bulk, the significant enhancement of |ID| at VDS < -1 V in Figure 4 (a) results from the T-activated mobility that is characteristic of disordered organic semiconductors.26 In contrast, the modulation of the reverse-bias current (0 < VDS) originates from the T-affected interface energetics because the current in this regime is injection- or diffusion-limited. We characterized each output curve by the diode saturation current Is extracted as the zero-VDS extrapolation value of the low-voltage exponential forward-regime ID. For systematic extraction, a voltage range with an apparently exponential ID vs. VDS relationship was first determined close to VDS = 0 V. A linear fit, such as one drawn in Figure 3 (b) for ideality factor (n), was conducted over this voltage range. Extrapolation was used where necessary to assign the value of Is on each output curve, which corresponds to the ID value where the fit line crosses VDS = 0 V. Recent studies have observed that, due to the low density of thermal carriers in an unintentionally-doped organic semiconductor, the metal-insulator-metal type diode model could better describe the conduction mechanism of organic diodes than the conventional depletion-modulation (Schottkytype) model.27, 28 However, in the results in Figure 4, due to the rather thick C60 film (140 nm), 9 ACS Paragon Plus Environment
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and an expected low and VGS-dependent built-in potential, it is not straightforward to identify a single valid model. We therefore use the conventional thermionic-emission based model as an approximate description for barrier extraction. The corresponding saturation current is written as 29
qφ I s = AA *T 2 exp − B , kT
(1)
where A is the diode active area, A* the effective Richardson constant, q the elementary charge, k the Boltzmann constant, and φB the potential barrier for electron injection from graphene to C60, as illustrated in Figure 4 (c). Equation (1) dictates an Arrhenius dependence between T and IS/T2 with the activation energy equivalent to the charge injection barrier. In order to fully address of the validity of Equation (1), we conducted a linear regression of the experimental log(Is/T2) vs. T curves with a VGS-independent prefactor.30 The results in Figure 4 (b) show good overall agreement between the experiments and theory. It is worth pointing out that the pronounced deviation from the linear fits in the data with VGS = -6 and -4 V at low T is mainly attributed to the measurement noise as the reduced current approaches the detection limit of the electrical system (pA range). Figure 4 (c) traces the modulation of the graphene-to-C60 electron injection barrier by VGS, extracted from the analyses in Figure 4 (b). The reduction of qφB is as large as approximately 0.3 eV, which exceeds that reported for the graphene/Si junction.1 We infer that the van der Waals nature of organic crystals allows more conformable interface formation on graphene as compared to the inorganic (covalent) crystals, thus leading to low density of interface defects and highly efficient work function modulation of the graphene contact.
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Figure 4. (a) Semi-log scale output curves measured at different temperature with a fixed VGS of -4 V. (b) Temperature dependence of the diode saturation current to examine the validity of an Arrhenius type relationship. The symbols are measured data and the solid lines are linear regressions with a fixed prefactor corresponding to the convergence point at 1/T → 0. Data with VGS = -6 and -4 V at low T are visibly affected by the measurement noise as the reduced current approaches the detection limit of the electrical system. (c) Gate-modulated electron injection barrier extracted from the slopes in (b). The inset illustrates the energetics at the graphene/C60 junction. The extracted barrier height (principal vertical axis) translates into the estimated 11 ACS Paragon Plus Environment
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graphene work function (second vertical axis) under the assumption of C60 electron affinity as 4.2 eV. VOTFTs with desirable characteristics can be obtained by selecting the appropriate organic semiconductor in the vertical heterostructure with graphene. Pentacene layer with a film thickness of ~150 nm was used in conjunction with an Au top electrode for ohmic contact to fabricate the complementary p-channel devices necessary for logic operation. Figure 5 (a) exhibits typical p-channel characteristics where ID decreases with increasing VGS, yielding an on/off ratio ~ 5. At zero and negative gate voltages (VGS 0), no significant injection barrier exists at the pentancene/graphene interface due to the close proximity of graphene workfunction with highest occupied molecular orbital (HOMO) of pentacene (~5 eV) resulting in almost linear I-V characteristics. At VGS >0, an increase in the barrier height results in a modest reduction of the reverse bias current as shown in Figure 5 (b). However, the off-current density of p-channel VOTFTs is an order of magnitude higher than that of its n-channel counterpart, significantly reducing the on/off ratio. The relatively large leakage current can be attributed to the inhomogeneous island growth of pentacene on graphene forming pinholes and shorting paths (SI Figure S2), increasing the off-current. The deposition of a thicker semiconducting layer could eliminate the creation of pinholes but will result in a reduced current negating the desired lowvoltage operation (SI Figure S3). We are currently investigating the growth and thin film formation of various p-type organic semiconductors on graphene in order to improve the performance of p-channel devices. It might also be possible to increase the on/off ratio of the pchannel device by introducing an organic semiconductor with a deeper HOMO level and/or employing n-doped graphene creating a larger initial injection barrier at zero gate voltage.
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Figure 5. (a) Semilogarithmic ID–VDS output characteristics of a p-type VOTFT at various gate from 8 V to -8 V with -4 V step. (b) Semilogarithmic ID–VGS transfer characteristics of the same device measured at VDS of -0.5, -1 and -2 V. The active area (A) of the transistor measured for this figure is 600 µm × 800 µm (4.8 × 10-3 cm2). (c) The optical image and schematic of an inverter obtained by integrating p- and n- channel VOTFTs. The active area (A) of both transistors is 600 µm × 980 µm (5.9 × 10-3 cm2). (d) Output behavior of the inverter as a function of input voltage measured at VDD = 2V. Using complementary p- and n-channel VOTFTs, the first low-voltage organic complementary circuit based on a vertical architecture has been realized. Since the normal transistor operation is achieved in the reverse bias regime (VSD > 0 for n-type and VSD < 0 for p-type), source and drain connections in the inverter configuration are not interchangeable, in contrast with an inverter based on traditional OFETs. An optical image and schematic of our inverter configuration is shown in Figure 5 (c). The supply voltage is applied to the bottom graphene contact of p-type 13 ACS Paragon Plus Environment
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VOTFT while the bottom graphene contact of the n-type VOTFT is connected to ground. The output voltage is measured at the joint between the two top metal contacts as a function of the input voltage applied to the combined ITO gate electrodes. Figure 5 (d) shows the Vin versus Vout characteristics of a fabricated inverter at a drain bias voltage (VDD) of 2 V. Since ID at VDS ~ 2 V is comparable for both p- and n-type devices, a logic converter combining two complementary VOTFTs device is able to invert the low input signal Vin to high Vout and vice versa. However, due to the poor performance of the p-type device, signal gain is below the unity in the entire range of the applied Vin. We believe that the performance of our inverter can be improved further with enhanced performance of the p-type VOTFT. In conclusion, we have shown that high performance VOTFTs can be realized based on a gatetunable injection barrier in a vertical heterostructure of graphene and an organic semiconductor. N-channel VOTFTs based on C60 show a room temperature on/off ratio exceeding 4 orders of magnitude, high current density of up to 44 mAcm-2 and operating voltages as low as 200 mV, satisfying critical requirements for application in logic circuits as well as active matrix displays. VOTFTs can also be vertically integrated as a built-in switch for a wide range of electronic and optoelectronic applications. A complementary p-channel device based on pentacene, and an inverter based on the two complementary transistors was further demonstrated. The simple, scalable, and low-temperature deposition of organic semiconductors combined with the optical transparency and mechanical flexibility of graphene make VOTFTs promising elements for future transparent, flexible, and low-power organic electronics.
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ASSOCIATED CONTENT Supporting Information. Scanning electron microscope image of Pentacene film deposited on graphene/Silicon substrate. This material is available free of charge via the Internet at http://pubs.acs.org.
AUTHOR INFORMATION Corresponding Author *Email: [email protected] (H.H.). *Email: [email protected] (I.K.).
ACKNOWLEDGMENT I. Kymissis, H. Hlaing, and overall project coordination as well as sample growth and characterization were supported as part of the Center for Re-Defining Photovoltaic Efficiency Through Molecular-Scale Control, an Energy Frontier Research Center funded by the U.S. Department of Energy (DOE), Office of Science, Office of Basic Energy Sciences under Award DE-SC0001085. C.-H. Kim acknowledges financial and administrative support from Ecole Polytechnique and Alliance Program. Research carried out at the Center for Functional Nanomaterials, Brookhaven National Laboratory, is supported by the U.S. Department of Energy, Office of Basic Energy Sciences, under Contract No. DE-AC02-98CH10886.
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20. Petrone, N.; Dean, C. R.; Meric, I.; van der Zande, A. M.; Huang, P. Y.; Wang, L.; Muller, D.; Shepard, K. L.; Hone, J. Nano letters 2012, 12, (6), 2751-2756. 21. Klauk, H.; Zschieschang, U.; Pflaum, J.; Halik, M. Nature 2007, 445, (7129), 745-748. 22. Yoon, M.-H.; Yan, H.; Facchetti, A.; Marks, T. J. Journal of the American Chemical Society 2005, 127, (29), 10388-10395. 23. Gu, G.; Forrest, S. R. IEEE Journal of Selected Topics in Quantum Electronics 1998, 4, (1), 83-99. 24. Khodagholy, D.; Rivnay, J.; Sessolo, M.; Gurfinkel, M.; Leleux, P.; Jimison, L. H.; Stavrinidou, E.; Herve, T.; Sanaur, S.; Owens, R. M.; Malliaras, G. G. Nature Communications 2013, 4, 2133. 25. Chen, G.; Yokoyama, D.; Sasabe, H.; Hong, Z.; Yang, Y.; Kido, J. Applied Physics Letters 2012, 101, (8), 083904. 26. Coehoorn, R.; Pasveer, W. F.; Bobbert, P. A.; Michels, M. A. J. Phys Rev B 2005, 72, (15), 155206. 27. Kim, C. H.; Yaghmazadeh, O.; Bonnassieux, Y.; Horowitz, G. J Appl Phys 2011, 110, (9), 093722. 28. de Bruyn, P.; van Rest, A. H. P.; Wetzelaer, G. A. H.; de Leeuw, D. M.; Blom, P. W. M. Phys Rev Lett 2013, 111, (18), 186801. 29. Arcari, M.; Scarpa, G.; Lugli, P.; Tallarida, G.; Huby, N.; Guziewicz, E.; Krajewski, T. A.; Godlewski, M. Electron Devices, IEEE Transactions on 2012, 59, (10), 2762-2766.
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30. Craciun, N. I.; Wildeman, J.; Blom, P. W. M. Phys Rev Lett 2008, 100, (5), 056601. 31. Regan, W.; Byrnes, S.; Gannett, W.; Ergen, O.; Vazquez-Mena, O.; Wang, F.; Zettl, A. Nano letters 2012, 12, (8), 4300-4304. 32. Chen, W.; Rinzler, A.; Guo, J. Journal of Applied Physics 2013, 113, (9), 094507. 33. Ben-Sasson, A. J.; Tessler, N. Journal of Applied Physics 2011, 110, (4), 044501. 34. Goncalves, A. M. B.; Malachias, A.; Mazzoni, M. S.; Lacerda, R. G.; MagalhãesPaniago, R. Nanotechnology 2012, 23, (17), 175603. 35. Nemes-Incze, P.; Osváth, Z.; Kamarás, K.; Biró, L. P. Carbon 2008, 46, (11), 1435-1442.
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Communication
Low-Voltage Organic Electronics Based on a Gate#Tunable Injection Barrier in Vertical Graphene–Organic Semiconductor Heterostructures Htay Hlaing, Chang-Hyun Kim, Fabio Carta, Chang-Yong Nam, Rob Barton, Nicholas Petrone, James Hone, and Ioannis Kymissis Nano Lett., Just Accepted Manuscript • DOI: 10.1021/nl5029599 • Publication Date (Web): 17 Dec 2014 Downloaded from http://pubs.acs.org on December 23, 2014
Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.
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Low-Voltage Organic Electronics Based on a Gate‒ Tunable Injection Barrier in Vertical Graphene– Organic Semiconductor Heterostructures Htay Hlaing,*,†,‡ Chang-Hyun Kim,ǁ Fabio Carta,‡ Chang-Yong Nam,┴ Rob Barton,†,‡ Nicholas Petrone,§ James Hone,†,§ and Ioannis Kymissis*,†,‡
†
DOE Energy Frontier Research Center, ‡Department of Electrical Engineering, §Department of Mechanical Engineering, Columbia University, New York, New York 10027, United States ǁ
LPICM, Ecole Polytechnique, CNRS, 91128 Palaiseau, France
┴
Center for functional Nanomaterials, Brookhaven National Laboratory, Upton, New York 1197, United States
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KEYWORDS: Graphene, organic semiconductors, thin film transistors, low-voltage electronics
ABSTRACT: The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly-emerging layered materials has recently been demonstrated as a promising route towards novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices current modulation is accomplished by tuning the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. Nchannel devices fabricated with a thin layer of C60 show a room temperature on/off ratio > 104 and current density of up to 44 mAcm-2. Due to the ultra-short channel intrinsic to the vertical structure the device is fully operational at a driving voltage of 200 mV. A complementary pchannel device is also investigated and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.
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Novel device architectures based on heterostructures of graphene with semiconductor layers have recently attracted considerable interest due to their potential in a wide range of electronic and photonic applications.1-6 The key concept in these devices is to exploit the work function tunability of graphene via an external gate field to modulate the current flow across the graphene-semiconductor junction by adjusting the Schottky barrier height.7, 8 Transistor devices based on a vertical heterojunction of graphene with an inorganic semiconductor (n- and p-type Silicon),1 oxide semiconductor (n-type indium gallium zinc oxide)2, 3 and flakes of 2D layered materials (hexagonal boron nitride, molybdenum disulfide and tungsten disulfide)4-6 have been successfully fabricated with high on/off ratios, overcoming one of the limitations of planar graphene field-effect devices. Organic thin film transistors (OTFTs) with high current output at low driving voltage are highly desirable for many applications such as logic circuits and active matrix displays.9-11 However, the traditional planar field effect transistor (OFET) architecture requires high mobility organic semiconductors (µ >> 1 cm2V-1s-1) or implementation of short-channel length devices for low mobility organic semiconductors (µ < 1 cm2V-1s-1). This is especially problematic for n-type organic semiconductors which exhibit lower mobility compared to their p-type counterparts, introducing more complexity to fabricate complimentary circuits for low power applications. In order to address the transconductance and power limitation of planar OFETs, vertical organic thin film transistors (VOTFTs), where the channel length is determined by the active layer thickness, have been actively investigated.12-16 However, VOTFTs require high resolution patterning of source electrodes for gate-field penetration and therefore demand complex fabrication techniques. Transistors based on heterojunctions of graphene with organic semiconductors have fundamental advantages allowing them to be integrated in vertical
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architectures. Earlier efforts show promising but limited device performance.17,
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Aristizabal et al. have demonstrated a device based on pentacene, an archetypical p-type organic semiconductor, demonstrating an on/off ratio of ~ 4 with a gate bias of ± 50 V.18 Lemaitre, et al. demonstrated further device performance improvement using a higher mobility p-type semiconductor, dinaphtho-[2,3-b:2´,3´-f]thieno[3,2-b]thiophene, attaining an on/off ratio of ~103 with gate bias of ± 40 V and on-current density of ~2 mA/cm2 at a drain voltage of – 5V.17 Lemaitre delivered an additional improvement in device performance by introducing pores in the graphene, similar to the perforated source electrodes of other VOTFT concepts. Although these results are promising, development of both p- and n-type VOTFTs with enhanced device performance is essential for VOTFTs to be successfully employed in active matrix displays and low-power logic applications. Here, we demonstrate low-voltage complementary p- and n- channel vertical organic thin film transistors (VOTFTs) based on graphene-organic semiconductor heterojunctions with a simple, scalable and low-temperature fabrication process. Figure 1 (a) shows the schematic illustrations of the three-dimensional and cross-sectional view of the VOTFT device structure. The fabrication process starts with the deposition of a dielectric Al2O3 film (20 nm) on a pre-patterned ITO gate electrode on a glass substrate via atomic layer deposition. The monolayer graphene is grown by chemical vapor deposition and is patterned and transferred on top of the dielectric as a source electrode using well-established procedures.19, 20 The p- or n- type organic semiconductor layer is deposited at a base pressure of 10-6 Torr by thermal evaporation at 1 Ǻ/s, followed by the deposition of a gold (for the p-type device) or aluminium (for the n-type device) drain electrode via a shadow mask to create an ohmic contact to their respective semiconductors. The samples are kept at room temperature
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during the deposition. The device area is defined by the overlapping region between graphene and top metal electrode. The large-area fabrication of VOTFTs on a 50 x 50 mm2 transparent glass substrate is shown in the optical top-view image (Figure 1 (b)) with the inset showing the zoomed in image of individual device. The cross-sectional scanning electron microscope image (Figure 1 (c)) illustrates the vertical heterostructure of the graphene-organic semiconductor-metal stack in which the position of the graphene layer is indicated by a dashed line.
Figure 1. Vertical field-effect transistors based on graphene-organic semiconductor-metal heterojunctions. (a) Schematic illustration of the three-dimensional and cross-sectional view of the vertically stacked graphene-organic semiconductor-metal VOTFT. (b) Optical top view image of VOTFT devices fabricated on a 50 x 50 mm2 transparent glass substrate. Inset shows the zoomed-in image of an individual device. The device area (600µm x 800 µm) is defined by the overlap between the graphene and top Al electrode. (c) Cross-sectional scanning electron microscope image of the vertical heterostructure of graphene-organic semiconductor-metal stack. Graphene layer is indicated by dash line.
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Electrical transport studies of the VOTFTs based on the heterojunction of graphene and a 140 nm thick layer of C60 show that high on-current density can be achieved with a supply voltage of less than two volts using this archetypical n- type organic semiconductor. The electrical measurements are performed with the source electrode held at the ground potential while the drain and gate electrodes are biased with respect to the ground (see Figure 1 (a)). The transistor operation is demonstrated in Figure 2 (a), which shows the large modulation of the drain-source current (ID) by the gate voltage (VGS). The device can be fully turned on and off using a VGS of ± 6 V, with an on-off current ratio exceeding 104. The gate leakage current (IG) is also confined to the nano-ampere range. Due to the vertical structure with a thin semiconducting layer (corresponding to a lateral channel length of 140 nm), the VOTFT is operational even at the ultralow source-drain voltage (VDS) of 200 mV. In comparison, state of the art short-channel OFETs generally require a driving voltage around 1.5 V.21, 22 Another unique signature of this VOTFT is that ID can be tuned over an order of magnitude by varying VDS while maintaining a large on-to-off current ratio as shown in Figure 2 (b). Here, the on-state current density (Jon) and off-state current density (Joff) were calculated from the ID values on the transfer curves at VGS = 6 V and -6 V, respectively. Jon up to 44 mA/cm2 can be obtained at a low VDS of 2 V providing sufficient current density to drive OLEDs.23 Moreover, the VOTFT reaches a transconductance ( = ⁄ ) up to 25 µS (Figure 2(c)), ensuring a narrow gate-window switching capability. Our transconductance is among the highest reported values for solid-dielectric-gated organic transistors.24 The performance of VOTFTs can be improved further by optimizing the thickness of the gate dielectric as well as by perforating the graphene electrode.17
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Figure 2. (a) Semilogarithmic ID–VGS transfer characteristics of an n-type VOTFT measured at VDS of 0.2 and 0.5 V. IG is indicated by the dashed line. (b) On- and off-current density and (c) transconductance at various drain voltages measured at fixed gate voltage of 3V. The active area (A) of the transistor measured for this figure is 600 µm × 500 µm (3 × 10-3 cm2).
The underlying mechanism of our VOTFT operation can be described based on the gatetunable injection barrier at the bottom graphene/organic interface within a source-to-drain rectifying diode. In our device configuration, the diode is reverse biased when a positive voltage is applied at the aluminium electrode (the drain) while the graphene (the source) is grounded as indicated in Figure 3 (a). The strong rectification of diode current in the reverse bias regime (VDS > 0) is clearly observed for zero and negative gate voltages (VGS 0). Since the top aluminium electrode provides an ohmic (injecting) contact to C60, rectification at zero gate bias is mainly due to the electron injection barrier resulting from the energy level mismatch between the graphene workfunction (~ 4.6 eV)8 and the LUMO of C60 (~ 4.2 eV)25 at the bottom interface (see inset, Figure 4 (c)). When the negative gate voltage is applied, the work function of the 7 ACS Paragon Plus Environment
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graphene increases8 creating a larger injection barrier at the interface. Hence, the reverse current becomes negligibly small at VGS = - 6 V and a high current rectification is obtained. On the other hand, the work function of the graphene decreases as the gate is positively biased lowering the electron injection barrier height from the source into the organic layer. Consequently, the reverse current increases dramatically when VGS 0 as shown in Figure 3, explaining the n-type fieldeffect behavior in Figure 2 (a). A significant current modulation with VGS is also observed in the injection-limited forward bias region where the applied voltage is still smaller than the barrier height.
Figure 3. (a) Linear-scale ID–VDS output curves of an n-type VOTFT at various VGS values. VGS increases from -6 V to +6 V with a 2 V step in the direction indicated by the arrow. (b)
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Semilogarithmic plot of ID–VDS with the dashed line indicating the fit to obtain the diode ideality factor (n) at the injection-limited (exponential) regime. Because the electrostatics at a metal/semiconductor interface and associated charge-injection properties are temperature scaled, the response of the electrical behavior to a range of temperatures provides a direct access to such interface physics. Figure 4 (a) shows the variation of the output curves (diode characteristics) for the absolute temperature T from 180 to 320 K at a fixed VGS = -4 V. The observed overall enhancement of current with increasing T has two possible components; temperature activated mobility and a change in interface energetics. As the current in the high forward-bias regime is limited by the conductivity of the semiconducting bulk, the significant enhancement of |ID| at VDS < -1 V in Figure 4 (a) results from the T-activated mobility that is characteristic of disordered organic semiconductors.26 In contrast, the modulation of the reverse-bias current (0 < VDS) originates from the T-affected interface energetics because the current in this regime is injection- or diffusion-limited. We characterized each output curve by the diode saturation current Is extracted as the zero-VDS extrapolation value of the low-voltage exponential forward-regime ID. For systematic extraction, a voltage range with an apparently exponential ID vs. VDS relationship was first determined close to VDS = 0 V. A linear fit, such as one drawn in Figure 3 (b) for ideality factor (n), was conducted over this voltage range. Extrapolation was used where necessary to assign the value of Is on each output curve, which corresponds to the ID value where the fit line crosses VDS = 0 V. Recent studies have observed that, due to the low density of thermal carriers in an unintentionally-doped organic semiconductor, the metal-insulator-metal type diode model could better describe the conduction mechanism of organic diodes than the conventional depletion-modulation (Schottkytype) model.27, 28 However, in the results in Figure 4, due to the rather thick C60 film (140 nm), 9 ACS Paragon Plus Environment
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and an expected low and VGS-dependent built-in potential, it is not straightforward to identify a single valid model. We therefore use the conventional thermionic-emission based model as an approximate description for barrier extraction. The corresponding saturation current is written as 29
qφ I s = AA *T 2 exp − B , kT
(1)
where A is the diode active area, A* the effective Richardson constant, q the elementary charge, k the Boltzmann constant, and φB the potential barrier for electron injection from graphene to C60, as illustrated in Figure 4 (c). Equation (1) dictates an Arrhenius dependence between T and IS/T2 with the activation energy equivalent to the charge injection barrier. In order to fully address of the validity of Equation (1), we conducted a linear regression of the experimental log(Is/T2) vs. T curves with a VGS-independent prefactor.30 The results in Figure 4 (b) show good overall agreement between the experiments and theory. It is worth pointing out that the pronounced deviation from the linear fits in the data with VGS = -6 and -4 V at low T is mainly attributed to the measurement noise as the reduced current approaches the detection limit of the electrical system (pA range). Figure 4 (c) traces the modulation of the graphene-to-C60 electron injection barrier by VGS, extracted from the analyses in Figure 4 (b). The reduction of qφB is as large as approximately 0.3 eV, which exceeds that reported for the graphene/Si junction.1 We infer that the van der Waals nature of organic crystals allows more conformable interface formation on graphene as compared to the inorganic (covalent) crystals, thus leading to low density of interface defects and highly efficient work function modulation of the graphene contact.
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Figure 4. (a) Semi-log scale output curves measured at different temperature with a fixed VGS of -4 V. (b) Temperature dependence of the diode saturation current to examine the validity of an Arrhenius type relationship. The symbols are measured data and the solid lines are linear regressions with a fixed prefactor corresponding to the convergence point at 1/T → 0. Data with VGS = -6 and -4 V at low T are visibly affected by the measurement noise as the reduced current approaches the detection limit of the electrical system. (c) Gate-modulated electron injection barrier extracted from the slopes in (b). The inset illustrates the energetics at the graphene/C60 junction. The extracted barrier height (principal vertical axis) translates into the estimated 11 ACS Paragon Plus Environment
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graphene work function (second vertical axis) under the assumption of C60 electron affinity as 4.2 eV. VOTFTs with desirable characteristics can be obtained by selecting the appropriate organic semiconductor in the vertical heterostructure with graphene. Pentacene layer with a film thickness of ~150 nm was used in conjunction with an Au top electrode for ohmic contact to fabricate the complementary p-channel devices necessary for logic operation. Figure 5 (a) exhibits typical p-channel characteristics where ID decreases with increasing VGS, yielding an on/off ratio ~ 5. At zero and negative gate voltages (VGS 0), no significant injection barrier exists at the pentancene/graphene interface due to the close proximity of graphene workfunction with highest occupied molecular orbital (HOMO) of pentacene (~5 eV) resulting in almost linear I-V characteristics. At VGS >0, an increase in the barrier height results in a modest reduction of the reverse bias current as shown in Figure 5 (b). However, the off-current density of p-channel VOTFTs is an order of magnitude higher than that of its n-channel counterpart, significantly reducing the on/off ratio. The relatively large leakage current can be attributed to the inhomogeneous island growth of pentacene on graphene forming pinholes and shorting paths (SI Figure S2), increasing the off-current. The deposition of a thicker semiconducting layer could eliminate the creation of pinholes but will result in a reduced current negating the desired lowvoltage operation (SI Figure S3). We are currently investigating the growth and thin film formation of various p-type organic semiconductors on graphene in order to improve the performance of p-channel devices. It might also be possible to increase the on/off ratio of the pchannel device by introducing an organic semiconductor with a deeper HOMO level and/or employing n-doped graphene creating a larger initial injection barrier at zero gate voltage.
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Figure 5. (a) Semilogarithmic ID–VDS output characteristics of a p-type VOTFT at various gate from 8 V to -8 V with -4 V step. (b) Semilogarithmic ID–VGS transfer characteristics of the same device measured at VDS of -0.5, -1 and -2 V. The active area (A) of the transistor measured for this figure is 600 µm × 800 µm (4.8 × 10-3 cm2). (c) The optical image and schematic of an inverter obtained by integrating p- and n- channel VOTFTs. The active area (A) of both transistors is 600 µm × 980 µm (5.9 × 10-3 cm2). (d) Output behavior of the inverter as a function of input voltage measured at VDD = 2V. Using complementary p- and n-channel VOTFTs, the first low-voltage organic complementary circuit based on a vertical architecture has been realized. Since the normal transistor operation is achieved in the reverse bias regime (VSD > 0 for n-type and VSD < 0 for p-type), source and drain connections in the inverter configuration are not interchangeable, in contrast with an inverter based on traditional OFETs. An optical image and schematic of our inverter configuration is shown in Figure 5 (c). The supply voltage is applied to the bottom graphene contact of p-type 13 ACS Paragon Plus Environment
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VOTFT while the bottom graphene contact of the n-type VOTFT is connected to ground. The output voltage is measured at the joint between the two top metal contacts as a function of the input voltage applied to the combined ITO gate electrodes. Figure 5 (d) shows the Vin versus Vout characteristics of a fabricated inverter at a drain bias voltage (VDD) of 2 V. Since ID at VDS ~ 2 V is comparable for both p- and n-type devices, a logic converter combining two complementary VOTFTs device is able to invert the low input signal Vin to high Vout and vice versa. However, due to the poor performance of the p-type device, signal gain is below the unity in the entire range of the applied Vin. We believe that the performance of our inverter can be improved further with enhanced performance of the p-type VOTFT. In conclusion, we have shown that high performance VOTFTs can be realized based on a gatetunable injection barrier in a vertical heterostructure of graphene and an organic semiconductor. N-channel VOTFTs based on C60 show a room temperature on/off ratio exceeding 4 orders of magnitude, high current density of up to 44 mAcm-2 and operating voltages as low as 200 mV, satisfying critical requirements for application in logic circuits as well as active matrix displays. VOTFTs can also be vertically integrated as a built-in switch for a wide range of electronic and optoelectronic applications. A complementary p-channel device based on pentacene, and an inverter based on the two complementary transistors was further demonstrated. The simple, scalable, and low-temperature deposition of organic semiconductors combined with the optical transparency and mechanical flexibility of graphene make VOTFTs promising elements for future transparent, flexible, and low-power organic electronics.
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ASSOCIATED CONTENT Supporting Information. Scanning electron microscope image of Pentacene film deposited on graphene/Silicon substrate. This material is available free of charge via the Internet at http://pubs.acs.org.
AUTHOR INFORMATION Corresponding Author *Email: [email protected] (H.H.). *Email: [email protected] (I.K.).
ACKNOWLEDGMENT I. Kymissis, H. Hlaing, and overall project coordination as well as sample growth and characterization were supported as part of the Center for Re-Defining Photovoltaic Efficiency Through Molecular-Scale Control, an Energy Frontier Research Center funded by the U.S. Department of Energy (DOE), Office of Science, Office of Basic Energy Sciences under Award DE-SC0001085. C.-H. Kim acknowledges financial and administrative support from Ecole Polytechnique and Alliance Program. Research carried out at the Center for Functional Nanomaterials, Brookhaven National Laboratory, is supported by the U.S. Department of Energy, Office of Basic Energy Sciences, under Contract No. DE-AC02-98CH10886.
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