Letter pubs.acs.org/NanoLett
Modularized Construction of General Integrated Circuits on Individual Carbon Nanotubes Tian Pei, Panpan Zhang, Zhiyong Zhang,* Chenguang Qiu, Shibo Liang, Yingjun Yang, Sheng Wang, and Lian-Mao Peng* Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China S Supporting Information *
ABSTRACT: While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future. KEYWORDS: Carbon nanotube, field-effect transistor, integrated circuits ince the first carbon nanotube (CNT) field-effect transistor (FET) was invented in 1998,1,2 extensive studies have been conducted to explore the potential of CNTs as a channel material for replacing Si in future nanoelectronic integrated circuits (ICs). 3−5 While high-performance CNT FETs operating close to the ballistic limit have been experimentally realized for both p-type and n-type FETs,6−8 and a doping-free approach has been proposed9 and experimentally realized for constructing high performance CNT complementary metaloxide-semiconductor (CMOS) ICs on individual CNTs,10 so far CNT CMOS circuits of very limited complexity have been realized.11−13 Large scale ICs require dense arrays of all semiconducting single-walled CNTs,14 but in reality as-grown CNTs are always composed of mixed metallic and semiconducting CNTs.15 To construct CNT circuits CNTs are either fabricated on CNT-network with many junctions16 or on aligned semiconducting CNTs arrays but with degraded performance due to the removing processes of metallic CNTs from the arrays.17−20 Recently an efficient technique was demonstrated for removing metallic CNTs,21 but the remaining semiconducting CNT array is not uniform and thus cannot be used as an ideal materials to construct ICs. Here a modularized approach is reported for constructing CNT ICs on individual CNTs without compromising the performance of individual CNT FETs; in particular, an 8-bits BUS system is constructed on six semiconducting CNTs and allows signals to be passed
S
© XXXX American Chemical Society
between systems through seven stages of logic gates without much signal degradation. It has long been predicted that silicon-based CMOS technology will reach absolute limits on its performance by around 2020, and various potential micro or nanoelectronic technologies have been proposed and explored to extend Moore’s Law.22 Among those technologies, the most promising one in the near future is adopting another semiconducting material with thinner body and higher carrier mobility as alternative conducting channel to replace silicon. A thinner body of the conducting channel may lead to better gate electrostatics and controllability, which would be propitious to minimize short-channel effect in ultrasmall transistor. In addition, higher carrier mobility promise higher speed operation of the device. Therefore, many nanomaterials, including semiconducting nanowires, graphene nanoribbon, and CNTs, were investigated as the candidates for constructing high performance transistors.23−29 Among the candidate materials, CNT is the most promising one in that it has both extremely thin body and ultrahigh carrier mobility,30 and then CNT-based electronics has been identified as the most promising candidate technology to extend CMOS technology to the very end of the roadmap.4,5 Received: January 14, 2014 Revised: April 18, 2014
A
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
The devices used in this work for constructing integrated circuits are CNT-based complementary FETs fabricated via a doping-free approach.7−10 Benefiting from the symmetric band structure of the semiconducting CNT about the Fermi level, as well as the same carrier injection efficiency for electron (via Sc electrode) and hole (via Pd electrode) from contacts,6,7 the device characteristics of n-type and p-type CNTFETs are almost symmetric as shown in Supporting Information Figure S1. Through gate electrode engineering as developed previously,32 the threshold voltages of both n-type and p-type transistors are adjusted to center around 0 V so as to make the transistors feasible to construct PTL circuits efficiently.13,40,41 The excellent transfer and output characteristics of the CNT CMOS FETs have been fully demonstrated, and in particular saturation current of up to about 20 μA and high transconductance of up to 30 μS are routinely achieved. The symmetric and high-performing CNT CMOS FETs with threshold voltages close to zero are then used as the basic blocks to construct more complex PTL integrated circuits.40 Compared with the conventional CMOS configuration, PTL has been demonstrated to be a more efficient logic style for CNT-based integrated circuits because PTL can take full advantage of the CNT CMOS FETs.13,40,41 It is well-known that a programmable and multifunctional digital unit can provide an important and efficient module fashion to construct complex integrated circuits for nanoelectronics in which the fabrication of high-performance devices and circuits is not perfect and optimized.42 Here we show that a PTL-style CNT 8-T unit can be used as a basic module for generating various logic functions and for constructing more complex electronic systems. Circuit diagram of the 8-Tunit is shown in Figure 1a in
The CNT-based electronics has advanced significantly since the appearance of the first CNT FETs in 1998.1,2 High-quality single-walled semiconducting CNTs have been successfully used as channel material to construct both n- and p-type FETs that outperform stat-of-the-art silicon CMOS FETs with similar gate length.6−8,31−33 More recently, CNT-based FETs have been scaled down to sub-10 nm regime.34,35 These short channel CNT FETs are found to preserve excellent gate controlling ability and show negligible short channel effect, promising much better scaling down potential than silicon FETs.34,35 However, the development of CNT FET integrated circuits lagged far behind individual devices because only a few scalable methods have been developed for fabricating CNT FETs owing to the well-known material challenge as to how to obtain suitable semiconducting CNTs at the required locations in a chip.36 Extensive studies have been devoted to wafer-scale CNT device fabrication and complicated ICs16−19 and even a computer construction.20 However, CNT FETs were usually fabricated on CNT-network or aligned semiconducting CNT arrays with degraded performance during removing metallic CNTs from the array; the thus fabricated FETs either show performance that is no comparison with that of state-of-the-art Si FETs or cannot be readily scaled down to meet the requirement of the next generation technology. The dilemma is that we cannot construct high-performance ICs with optimized performance and small-size CNT FETs that can be built only on individual undamaged CNTs. Therefore, constructing ICs with FETs built on individual CNTs is currently the viable way to explore the performance and density potential of CNT ICs. However, individual CNT-based ICs are generally built on a single individual CNT in order to comply with the performance uniformity issues of CNT FETs, and the complexity and layout of IC are thus severely restricted. As a result, most of published CNT CMOS ICs on individual CNT are just simple logic and arithmetical gates, and to date the most complicated ICs are 5stage oscillator and 1-bit full adder/subtracter.10,11,37−41Although constructing complicated ICs on individual CNTs with different diameters and properties is a valid and necessary way to explore the potential advantages of CNT electronics at circuit level, this fabrication has not been demonstrated so far owing to the difficulty in controlling uniformity of CNT FETs based on different CNTs. Obviously FETs fabricated on different CNTs with different chiralities must present performance fluctuation much larger than those fabricated on the same CNT. It is thus an urgent task to develop an efficient method to build complex ICs on different CNTs with large property fluctuation In this paper, we explored the possibility of constructing complicated ICs on different CNTs by utilizing a modularized method. An 8-transistor (8-T) unit with pass-transistor-logic (PTL) style is designed and built on two individual CNTs with different electronic properties, and this 8-T unit is further used as the basic module to construct more complex ICs. The 8-T unit shows excellent tolerance to the property difference between CNTs and demonstrates as a powerful functional generator that can realize all logic and arithmetic functions. Using the 8-T unit as the basic module we designed and demonstrated an 8-bits BUS system that is an important IC used to transfer data between CPU, memory, and input/output systems. The BUS system works well although it contains up to 46 FETs built on 6 different semiconducting CNTs, which is so far the most complicated IC based on individual CNTs.
Figure 1. CNTs-based 8-T function generator. (a) Circuit diagram. (b) SEM image showing a real 8-T function generator that was fabricated on two CNTs (marked with two white dotted lines) and (c) the truth table. (d) An ideal compact layout design for an 8-T unit fabricated on two parallel semiconducting nanotubes. The rectangular region marked in red dotted box is the active region with an area of about 3λ × 17λ with λ being the minimum processable scale. The scale bar in Figure 1b denotes 100 μm. B
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
Figure 2. Simulated and measured outputs from a CNT-based 8-T function generator. (a) Simulated results of the 8-T unit for 16 distinct logic operations. The simulated results that are marked by red, blue, and pink dotted boxes correspond to the function of NAND, NOR, and XOR respectively. (b) Experimental measurements for three typical functions realized by the same 8-T unit for all four distinct input combinations. The working principle analysis of (c) NAND, (d) NOR, and (e) XOR functions of the 8-T unit.
realized for a given input combination (A, B). The selection of the logic function is made by the combinations of (G0, G1, G2, G3), and the truth table of the 8-T unit is given in Figure 1c. While the 8-T unit may be realized on a single CNT, it can be designed with a more compact and symmetrical layout using two parallel semiconducting CNTs (Figure 1b). The total area of the 8-T unit shown in Figure 1b is about 8000 μm2. This large area is caused by the large spacing between the two CNTs used. The modularized method that we demonstrated in this work is still dependent on the position of semiconducting CNTs, but it can be further extended to a prefabrication design on uniform all-semiconducting CNT array. In an optimized design, assuming an ideal spacing between the two CNTs or a
which 4 p-FETs and 4 n-FETs are used. It should be noted that the 8-T unit can be readily realized using two parallel semiconducting CNTs with symmetric layout and shown in Figure 1b is the scanning electron microscopy (SEM) image of such a fabricated 8-T unit. This unit is designed as a universal function generator and can be used to realize all logic and arithmetic functions between A and B according to a set of instructions (G0, G1, G2, G3). The output from the 8-T unit can be summarized as Out = G0·AB ̅ ̅ + G1·A̅ B + G2·AB̅ + G3·AB
(1)
where A and B are inputs, and G0−G3 are programming voltages. According to eq 1, a total of 16 distinct outputs can be C
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
efficient module to construct more complicated ICs on different CNTs. One important advantage of CNT-based ICs over silicon CMOS comes from their ability to operate at low supply voltages. This is because CNT allows the use of metals of different work function as the gate to effectively adjust the threshold voltage of CNT CMOS FETs, for example, to near zero (see Figure S1e in Supporting Information).32,34 As a result, PTL logic style that is more efficient than CMOS but requires zero threshold voltage may be readily implemented using CNT CMOS FETs. The 8-T unit illustrated in Figure 1a is designed using PTL style and thus has the potential of operation at low supply voltage. As an example, the NAND function of the 8-T unit is measured under a supply voltage of 0.5 V, and the output voltages for all four input combinations of (A,B) follow the standard NAND logic functions as shown in Figure S3 (in Supporting Information). Among the four outputs, the ones corresponding to the input combinations (0, 0) and (1, 0) are very close to the ideal high level (0.5 V). The outputs for the other two input combinations (0, 1) and (1, 1) are slightly degraded, where the high and low outputs show voltage levels centered on 0.45 V (see Figure S3c in Supporting Information) and 0.015 V (see Figure S3d in Supporting Information) respectively. The three logic functions demonstrated in Figure 2 are key components for the arithmetic logic unit (ALU) in a computer system. In fact the 8-T unit can be used as a powerful building block for constructing general ICs because it can realize all logic and arithmetic functions and present good tolerance to the inhomogeneity in CNTs. As an example, an 8-bits data BUS circuit was constructed by using 8-T units as the building blocks (Figure 3). Data BUS is a frequently used circuit and an important part in a computer system to transfer data between CPU and memory or input/output circuits as shown in Figure 3a.43,44 The circuit diagram of this data BUS is shown in Figure 3b, which contains four 8-T units (U1−U4), four CNTs-based CMOS inverters, three individual n-type, and three individual p-type CNT FETs. A total of 46 CNT FETs fabricated on six individual semiconducting CNTs are used to construct the 8-bit BUS circuit, and an SEM image of an as-fabricated IC is shown in Figure 3c. It should be noted that to successfully fabricate the 8-bit BUS system directly as designed (Figure 3c), the yield for the fabrication of 8-T units should be very high, close to 100%. However, with the current CNT growth technique there is no guarantee that the required semiconducting CNTs will present in the right locations. Instead, in this work we use a modularized method to construct complex circuits. Many 8-T units are first fabricated on available semiconducting CNTs, and those functioning 8-T units are selected and connected to form the designed circuit. For the BUS circuit, four 8-T units are selected and measured before constructing the final BUS circuit. The whole BUS circuit is realized by connecting the four selected 8-T units with additional CMOS inverters and controlling FETs and a typical layout of a BUS circuit fabricated in this way is shown in Supporting Information Figure S4. While not ideal, circuits as complex as BUS circuits can be constructed although the current yield of 8-T unit fabrication is still not very high, demonstrating that the modularized method is expedient but effective given current level of material synthesis and device fabrication. In principle, we can fabricate complex circuit such as a BUS circuit as shown in Figure 3c without selecting 8-T units prior, either on individual or parallel
high density parallel array of all-semiconducting CNTs is available,14 the 8-T unit can be aggressively scaled down with finer layout design and patterning technology. The parasitic capacitance and resistance that originated from the redundantly interconnected wires and pads of transistors may in principle be avoided if a compact layout is used based on CNT films of uniform density. According to the prospective layout shown in Figure 1d, total active area of the compacted 8-T unit can be scaled down to about 51λ2 with λ being the minimum processable line width. If λ = 20 nm (representing state-of-theart fabricating process capability) is used, the unit size down to 0.02 um2 is achievable. As a comparison, the whole area of a 6T SRAM unit using 22 nm silicon CMOS technology is about 0.092 μm2.33 All 16 logic functions realizable by the 8-T unit or function generator for a given pair of inputs A and B are first verified using a simulation tool HSPICE (companied with a lookuptable model, see Methods), and simulation results are shown in Figure 2a. Among these 16 logic functions, three functions are experimentally demonstrated and illustrated in Figure 2b. Unless otherwise noted, all high level in this paper is set to 1 V and low level to zero or ground, that is, only one supply voltage is used in powering our CNT ICs. NAND (A̅ B or A + B̅ ) function is first considered and tested. To implement this function, the programming voltages (G0, G1, G2, G3) are set to (1, 1, 0, 1). These voltages are respectively transmitted to the output F under the bias combination of (A, B), and the detailed operational principle is illustrated through the circuit diagram in Figure 2c. The measured outputs for all four (A, B) input combinations (see the left panel in Figure 2b) are all correct with the output voltage of high level “1” ranging between 0.75 to 1.0 V while output voltage of low level “0’’ranging from 0 to 0.2 V. We now consider the logic function NOR, that is, A + B or A̅ B̅ . The programming voltages (G0, G1, G2, G3) are set to (0, 0, 0, 1), which are respectively transmitted to the output F at the bias combination of (A, B), and the detailed operational principle is illustrated in the circuit diagram in Figure 2d. The measured outputs for all input combinations are shown in the middle panel of Figure 2b, which are consistent with the expected logic values of the truth table (Figure 1c). It should be noted that the output voltages for all input combinations are almost perfect, that is, around 0 V for low level and 1 V for high level. XOR is a very important logic gate, as well as a basic arithmetic function, that is, semiadder (or semisubtractor). This logic can be realized by the 8-T unit by setting programming voltages (G0, G1, G2, G3) as (0, 1, 1, 0), and the detailed operational principle is illustrated in the circuit diagram shown in Figure 2e. The result presented in the right panel of Figure 2b indicates that the XOR logic is well realized with almost perfect “0” and “1” states. As a universal building block for constructing general ICs, the 8-T unit should provide good tolerance to the inhomogeneity in the CNTs used. To test this inhomogeneity tolerance of the 8-T unit on CNTs, we built the 8-T unit on two CNTs with very different diameters and thus different transfer characteristics (see Figure S2 in Supporting Information). Although electric properties such as the on-state current of the two CNTs used are very different, that is, 0.7 μA versus 2 μA, the final circuit as shown in Figure 1b works fine (Figure 2b). We thus expect that the 8-T unit presents good tolerance to the inhomogeneity in the CNTs used and can be used as an D
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
G0 (or G1, or G2, or G3). It is obvious that a pair of 8-T units connected in series can be used to transfer data between Gi (i = 0, 1, 2, 3) of one unit and that of the other. Then in the 8-bits BUS circuit as shown in Figure 3b, two pairs of 8-T units are used to form two branches to transfer data, that is, the upper one is formed between U1 and U2 (for the paths between A0− A3 and F0−F3), and the lower one is formed between U3 and U4 (for the path between A4−A7 and F4−F7). In this way, the 8bit BUS system can be readily extended into higher bits, that is, 16-bits BUS system when 10 8-T units are used. Selection between the two branches is made by C2. Explicitly, the upper branch is selected if C2 = 0, and the lower branch is selected if C2 is set to 1. Within a branch, C0 and C1 are used to select the path to transfer data. Furthermore, the direction of data transfer may be controlled by Dir, that is, data will be transferred from left to right when Dir is set to “1” and be transferred from right to left when Dir is set to “0”. The complete data transmitting paths of the 8-bit BUS are all listed in Figure 4a. One of the major difficulties in implementing PTL circuits is that PTL gates do not provide gain of more than one. As a result signal degradation is unavoidable in PTL circuits, especially after passing through seven-stage cascaded gates as in a typical path in a BUS circuit.44 Cascading CMOS inverters with large gains in the path is an effective method to restore the signal to its ideal value in a multistage circuit.13 In the middle part of the BUS circuit (Figure 3b), two cascaded inverters (with typical characteristics shown in Figure 5S in Supporting Information) are used to restore the data passing through each 8-T unit. The CNT CMOS inverter is efficient in providing high voltage gain (typically about 50) and with excellent noise margin (high noise margin 0.44 V and low noise margin 0.46 V) owing to the symmetric nature and suitably controllable threshold voltages of p-type and n-type CNT FETs. This high gain and large noise margin of the CNT inverter ensures that the degraded signal is restored and the data being transferred does not suffer from large losses or errors in the BUS circuits. An example of the data after being transferred via the path from A6 to F6 is shown in Figure S6c of Supporting Information. When a square-wave signal with a period of 5 s and 50% duty ratio is applied to A6, an output square-wave signal with similar period and duty ratio is received at F6. This proves that this BUS circuit responses well to the input, that is, the signal can be transferred by the selected path. Sequential measurements on the bus system were made using a homemade probe card system (see Figure 6S in Supporting Information) and some representative results are shown in Figure 4b. For clarity, only those results for odd index paths in the 8-bit BUS system are given, that is, data transfers from F1 to A1, F3 to A3, F5 to A5, and F7 to A7. Because the BUS system is bidirectional, an inverse transfer path, that is, path 7 from A7 to F7, is also tested to verify the direction control bit Dir. The address and direction of data transfer are set by (C0, C1, C2, Dir), for example, if (C0, C1, C2, Dir) are set as (1, 1, 1, 0), the seventh path is opened and the signal is allowed to be transferred from A7 to F7. On the other hand, if (C0, C1, C2, Dir) are set as (1, 1, 1, 1), the same seventh path is opened but the signal is allowed to be transferred from F7 to A7. It is obviously that in our BUS system the signal can be transferred from the original termination (A1,...,7 or F1,...,7) to the target one by passing through 7 cascaded gates without much degradation, which is made possible by the introduction of CMOS inverters between the 8-T units and the excellent control on the threshold voltages of the FETs involved.
Figure 3. Function and structure diagrams of a complete 8-bits BUS circuit designed by using 8-T units as basic modules. (a) Block diagram showing the function of BUS systems in a computer system. A BUS system is used as the connection between different parts of the computer to communicate data. (b) The design diagram of an 8-bits BUS system. (c) SEM image showing an as-fabricated BUS circuit based on five semiconducting CNTs selected through electrical measurement. The scale bar denotes 50 μm.
arrays of semiconducting CNTs as the manufacturing technology is further improved. Without requiring additional or redundant devices, the BUS circuit layout in Figure 3c is significant more compact than that shown in Supporting Information Figure S4. The main function of a BUS circuit is to transmit data selectively between systems. For an 8-bits BUS, the path used to transmit data may be selected from eight available paths by controlling terminations (C0, C1, C2), in which C0 and C1 are respectively connected to inputs A and B of all 8-T units (see Figure 1a), while C2 is used to control the state of four individual FETs (N1, P1, N3, P3). In fact, the 8-T unit can also act as a four-to-one multiplexer (MUX) circuit in which one of the four inputs (G0 to G3) can be selected to connect with the output according to the combination of control voltages (A, B). For example, a channel can be opened between the input G0 (or G1, or G2, or G3) and the output if the control voltages (A, B) are set as (0,0) [or (0, 1), or (1, 0), or (1, 1)], and data can thus be transferred between the output and one of the inputs E
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
Figure 4. Sequential measurement results of an 8-T units based BUS system. (a) The truth table of the BUS system for all possible combinations of inputs (C0, C1, C2, Dir). (b) Sequential measurement results of the BUS system. The outputs shown in the lower part of the figure represent (from top to bottom) F1 → A1, F3 → A3, F5 → A5, F7 → A7, and A7 → F7 respectively, and the corresponding control voltages are shown in the upper part of the figure representing (C0, C1, C2, Dir) = (1, 0, 0, 0), (0, 1, 0, 0), (1, 0, 1, 0), (1, 1, 1, 0), and (1, 1, 1, 1) respectively.
CNTs were identified via field-effect measurements using the substrate as the back gate, and then were used for further device fabrication. High-performance CNT-based CMOS FETs were fabricated via the well-developed doping-free approaches. Fourteen nanometer HfO2 was deposited by atomic layer deposition (ALD) as oxide dielectric and followed by 10 nm Pd deposited as the top-gate electrode to adjust the threshold voltage of FETs to center around 0 V. While n-type CNTFETs were fabricated by using 60 nm Sc as the contact metals, p-type CNT FETs were fabricated using 60 nm Pd as the contact metals. Measurement of Circuits. The 8-T function generator circuit is measured using a probe station that is equipped with 7 probes. In addition, a semiconductor analyzer (Keithley 4200) is used to set programming voltage, and a signal generator (Agilent MXG N5181A) is used to apply square signals to the inputs (A, B). The output is measured by an oscilloscope (Agilent DSO7054A). Sequential measurement of the BUS system is illustrated in Figure.S6 (Supporting Information). To complete this measurement, all electrode pads are led to the edge of the wafer, and a probe card with 40 terminations is used to connect the pads for applying and detecting signals. A matrix switch (Agilent 34972A) is used to allocate sequential signals to each probe and also collect the output signals. When the control voltages (C0, C1, C2, Dir) are set to choose the transmit path, a square signal generated by signal generator (Agilent MXG N5181A) is applied to the input termination of chosen path. The output signal at the target output termination is then measured through Keithley 4200. Simulation of CNT ICs. The CNT-based ICs are simulated using the semiempirical HSPICE method similar to ref 46 but with the CNT FET model we developed independently. The device model is a semi-empirical one in which the measured transfer and output characteristics (Id−Vgs and Id−Vds) of both n-type and p-type CNT FETS were tabulated and used directly
While only result on a BUS system is demonstrated, the 8-T unit introduced in this work can indeed be used as a powerful module for constructing general CNT ICs, such as multiplexer, field-programmable gate array (FPGA), and ALU (relevant circuit diagrams are shown in Figure S7 in Supporting Information). Therefore, the modularized method is a universal and efficient way to construct large scale CNT ICs. The method is particularly valuable now because it allows us to explore the feasibility and performance limits of complex CNT ICs while the outstanding CNT material problems are not completely solved. In conclusion, a modularized method for constructing general ICs on individual CNTs is proposed and experimentally demonstrated. The proposed module is an 8-T unit consisting of 4 pairs of CMOS FETs designed using PTL style and two parallel semiconducting CNTs. It is demonstrated that although the two CNTs on which the 8-T unit is built may be very different, for example, with different diameters and onstate currents, the 8-T unit can work very well yielding 16 different logic functions, including NAND, NOR, and XOR. It is further shown that the 8-T unit may be used as a building block for constructing general ICs. An 8-bits BUS system consisting of 46 FETs was built on 6 different CNTs. It was found that the BUS system is able to provide full BUS function for transferring data in bidirections via eight distinct paths, and the signal is found to suffer tolerable degradation during the transfer although the signal needs to pass through as many as seven cascading logic gates in the system. The modularized method may also be used directly for constructing ICs using network type CNT films or arrays of parallel CNTs and allows us to explore the potentials and performance limits of CNT integrated circuits although the outstanding CNT materials problems are not yet fully solved. Methods. Fabrication of CNT and FETs. The CNTs used in this work were directionally grown on a Si substrate covered with 300 nm SiO2 layer,45 and semiconducting single-walled F
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
(17) Kang, S. J.; et al. High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. Nat. Nanotechnol. 2007, 2, 230−236. (18) Sun, D.-M.; et al. Flexible high-performance carbon nanotube integrated circuits. Nat. Nanotechnol. 2011, 6, 156−161. (19) Zhang, J.; Wang, C.; Zhou, C. W. Rigid/flexible transparent electronics based on separated carbon nanotube thin film transistors and their application in display electronics. ACS Nano 2012, 8, 7412− 7419. (20) Shulaker, Max M.; et al. Carbon nanotube computer. Nature 2013, 501, 526−530. (21) Jin, H. S.; Dunham, N. S.; Song, J.; Xie, X.; Kim, J.-H.; Lu, C.; Islam, A.; Du, F.; Kim, J.; Felts, J.; Li, Y.; Xiong, F.; Wahab, A. M.; Menon, M.; Cho, E.; Grosse, L. K.; Lee, J. D.; Chung, H. U.; Pop, E.; Alam, A. M.; King, P. W.; Huang, Y.; Rogers, A. J. Using nanoscale thermocapillary flows to create arrays of purely semiconducting singlewalled carbon nanotubes. Nat. Nanotechnol. 2013, 8, 347−355. (22) International Technology Roadmap for Semiconductors, 2011 ed. http://public.itrs.net/. (23) Xiang, J.; Lu, W.; Hu, Y.; Yan, H.; Lieber, M. C. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nat. Nanotechnol. 2006, 441, 489−493. (24) Jiang, X.; Xiong, Q.; Nam, S.; Qian, F.; Li, Y.; Lieber, M. C. InAs/InP Radial Nanowire Heterostructures as High Electron Mobility Devices. Nano Lett. 2007, 7, 3214−3218. (25) Bryllert, T.; Wernersson, L.-E.; Froberg, L. E. Samuelson, Lars. Vertical high-mobility wrap-gated InAs nanowire transistor. IEEE Electron Device Lett. 2006, 27, 323. (26) Wang, X.; Ouyang, Y.; Jiao, L.; Wang, H.; Xie, L.; Wu, J.; Guo, J.; Dai, H. J. Graphene nanoribbons with smooth edges behave as quantum wires. Nat. Nanotechnol. 2011, 6, 563−567. (27) Yao, J.; Yan, H.; Lieber, M. C. A nanoscale combing technique for the large-scale assembly of highly aligned nanowires. Nat. Nanotechnol. 2013, 8, 329−335. (28) Sprinkle, M.; Ruan, M.; Hu, Y.; Hankinson, J.; Rubio-Roy, M.; Zhang, B.; Wu, X.; Berger, C.; De Heer, W. A. Scalable templated growth of graphene nanoribbons on SiC. Nat. Nanotechnol. 2010, 5, 727−731. (29) Yao, J.; Yan, H.; Das, S.; Klemic, F. J.; Ellenbogen, C. J.; Lieber, M. C. Nanowire nanocomputer as a finite-state machine. Proc. Natl. Acad. Sci. U.S.A. 2014, 111, 2431−2435. (30) Saito, R.; Dresselhaus, G.; Dresselhaus, M. S. Physical Properties of Carbon Nanotubes; Imperial College Press: London, 1998. (31) Javey, A.; et al. Carbon nanotube field-effect transistors with integrated ohmic contacts and high-κ gate dielectrics. Nano Lett. 2004, 4, 447−450. (32) Zhang, Z. Y.; et al. Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage. Nano Lett. 2008, 8, 3696−3701. (33) Wang, Z. X.; et al. Yttrium oxide as a perfect high-κ gate dielectric for carbon-based electronics. Nano Lett. 2010, 10, 2024− 2030. (34) Franklin, A. D.; Chen, Z. Length scaling of carbon nanotube transistors. Nat. Nanotechnol. 2010, 5, 858−862. (35) Franklin, A. D.; et al. Sub-10 nm carbon nanotube transistor. Nano Lett. 2012, 12, 758−762. (36) Rutherglen, C.; Jain, D.; Burke, P. Nanotube Electronics for Radiofrequency Applications. Nat. Nanotechnol. 2009, 4, 811−819. (37) Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon nanotube inter- and intramolecular logic gates. Nano Lett. 2001, 1, 453−456. (38) Bachtold, A.; et al. Logic circuits with carbon nanotube transistors. Science 2001, 294, 1317−1320. (39) Chen, Z.; et al. An integrated logic circuit assembled on a single carbon nanotube. Science 2006, 311, 1735−1735. (40) Ding, Li; et al. Carbon nanotube field-effect transistors for use as pass transistors in integrated logic gates and full subtractor circuits. ACS Nano 2012, 6, 4013−4019.
to describe the DC characteristic of the 3-terminal FET. The AC characteristics of the CNT FETs are derived using the intrinsic and parasitic parameters of the self-aligned device structure and measurement system.
■
ASSOCIATED CONTENT
S Supporting Information *
Additional figures. This material is available free of charge via the Internet at http://pubs.acs.org.
■
AUTHOR INFORMATION
Corresponding Authors
*E-mail: (Z.Y.Z.) [email protected]. *E-mail: (L.M.P.) [email protected]. Notes
The authors declare no competing financial interest.
■
ACKNOWLEDGMENTS This work was supported by the Ministry of Science and Technology of China (Grants 2011CB933001 and 2011CB933002), National Science Foundation of China (Grants 61322105, 61271051, 61376126, 61321001, and 61390504), and Beijing Municipal Science and Technology Commission (Grants Z131100003213021 and 20121000102).
■
REFERENCES
(1) Tan, S. J.; Verschueren, A. R. M.; Dekker, C. Room temperature transistor based on a single carbon nanotube. Nature 1998, 393, 49− 52. (2) Martel, R.; et al. Single- and multi-wall carbon nanotube fieldeffect transistors. Appl. Phys. Lett. 1998, 73, 2447−2449. (3) Ralph, K. C.; Paolo, L.; Victor, V. Z. Science and Engineering Beyond Moore’s Law. Proc. IEEE 2012, 100, 1720−1749. (4) Avouris, P.; Chen, Z. H.; Perebeinos, V. Carbon-based electronics. Nat. Nanotechnol. 2007, 2, 605−615. (5) Burghard, M.; Klauk, H.; Kern, K. Carbon-based field-effect transistors for nanoelectronics. Adv. Mater. 2009, 21, 2586−2600. (6) Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. J. Ballistic carbon nanotube field-effect transistor. Nature 2003, 424, 654−657. (7) Zhang, Z. Y.; et al. Doping-free fabrication of carbon nanotube based ballistic CMOS devices and circuits. Nano Lett. 2007, 7, 3603− 3607. (8) Ding, L.; et al. Y-contacted high-performance n-type single-walled carbon nanotube field-effect transistors: scaling and comparison with sc-contacted devices. Nano Lett. 2009, 9, 4209−4214. (9) Peng, L.-M.; Zhang, Z. Y.; Wang, S.; Liang, X. L. A doping-free approach to carbon nanotube electronics and optoelectronics. AIP Adv. 2012, 2, 041403. (10) Zhang, Z. Y.; et al. Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 2009, 3, 3781−3187. (11) Javey, A.; et al. Carbon nanotube transistor arrays for multistage complementary logic and ring oscillators. Nano Lett. 2002, 2, 929− 932. (12) Chen, Z. Y.; et al. An integrated logic circuit assembled on a single carbon nanotube. Science 2006, 311, 1735−1736. (13) Ding, Li; et al. CMOS-based carbon nanotube pass-transistor logic integrated circuits. Nat. Commun. 2012, 3, 677. (14) Franklin, A. The road to carbon nanotube transistors. Nature 2013, 498, 443−444. (15) Ding, L.; et al. Selective growth of well-aligned semiconducting single-walled carbon nanotubes. Nano Lett. 2009, 9, 800−805. (16) Cao, Q.; et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 2008, 454, 495−500. G
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
(41) Ding, Li; et al. Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V. Appl. Phys. Lett. 2012, 100, 263116−263116. (42) Yan, H.; et al. Programmable nanowire circuits for nanoprocessors. Nature 2011, 470, 240−244. (43) Auth, C.; et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, selfaligned contacts and high density MIM capacitors. IEDM 2012, 131− 132. (44) Weste, N. H. E.; Harris, D. CMOS VLSI Design: a Circuits and System Perspective, 3rd ed.; Addison Wesley: Reading, MA, 2004. (45) Zhou, W.; et al. Copper catalyzing growth of single-walled carbon nanotubes on substrates. Nano Lett. 2006, 6, 2987−2990. (46) Dwyer, C.; et al. Semi-empirical SPICE models for carbon nanotube FET logic. Proc. 4th IEEE Conf. Nanotechnol. 2004, 386− 388.
H
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Modularized Construction of General Integrated Circuits on Individual Carbon Nanotubes Tian Pei, Panpan Zhang, Zhiyong Zhang,* Chenguang Qiu, Shibo Liang, Yingjun Yang, Sheng Wang, and Lian-Mao Peng* Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China S Supporting Information *
ABSTRACT: While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future. KEYWORDS: Carbon nanotube, field-effect transistor, integrated circuits ince the first carbon nanotube (CNT) field-effect transistor (FET) was invented in 1998,1,2 extensive studies have been conducted to explore the potential of CNTs as a channel material for replacing Si in future nanoelectronic integrated circuits (ICs). 3−5 While high-performance CNT FETs operating close to the ballistic limit have been experimentally realized for both p-type and n-type FETs,6−8 and a doping-free approach has been proposed9 and experimentally realized for constructing high performance CNT complementary metaloxide-semiconductor (CMOS) ICs on individual CNTs,10 so far CNT CMOS circuits of very limited complexity have been realized.11−13 Large scale ICs require dense arrays of all semiconducting single-walled CNTs,14 but in reality as-grown CNTs are always composed of mixed metallic and semiconducting CNTs.15 To construct CNT circuits CNTs are either fabricated on CNT-network with many junctions16 or on aligned semiconducting CNTs arrays but with degraded performance due to the removing processes of metallic CNTs from the arrays.17−20 Recently an efficient technique was demonstrated for removing metallic CNTs,21 but the remaining semiconducting CNT array is not uniform and thus cannot be used as an ideal materials to construct ICs. Here a modularized approach is reported for constructing CNT ICs on individual CNTs without compromising the performance of individual CNT FETs; in particular, an 8-bits BUS system is constructed on six semiconducting CNTs and allows signals to be passed
S
© XXXX American Chemical Society
between systems through seven stages of logic gates without much signal degradation. It has long been predicted that silicon-based CMOS technology will reach absolute limits on its performance by around 2020, and various potential micro or nanoelectronic technologies have been proposed and explored to extend Moore’s Law.22 Among those technologies, the most promising one in the near future is adopting another semiconducting material with thinner body and higher carrier mobility as alternative conducting channel to replace silicon. A thinner body of the conducting channel may lead to better gate electrostatics and controllability, which would be propitious to minimize short-channel effect in ultrasmall transistor. In addition, higher carrier mobility promise higher speed operation of the device. Therefore, many nanomaterials, including semiconducting nanowires, graphene nanoribbon, and CNTs, were investigated as the candidates for constructing high performance transistors.23−29 Among the candidate materials, CNT is the most promising one in that it has both extremely thin body and ultrahigh carrier mobility,30 and then CNT-based electronics has been identified as the most promising candidate technology to extend CMOS technology to the very end of the roadmap.4,5 Received: January 14, 2014 Revised: April 18, 2014
A
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
The devices used in this work for constructing integrated circuits are CNT-based complementary FETs fabricated via a doping-free approach.7−10 Benefiting from the symmetric band structure of the semiconducting CNT about the Fermi level, as well as the same carrier injection efficiency for electron (via Sc electrode) and hole (via Pd electrode) from contacts,6,7 the device characteristics of n-type and p-type CNTFETs are almost symmetric as shown in Supporting Information Figure S1. Through gate electrode engineering as developed previously,32 the threshold voltages of both n-type and p-type transistors are adjusted to center around 0 V so as to make the transistors feasible to construct PTL circuits efficiently.13,40,41 The excellent transfer and output characteristics of the CNT CMOS FETs have been fully demonstrated, and in particular saturation current of up to about 20 μA and high transconductance of up to 30 μS are routinely achieved. The symmetric and high-performing CNT CMOS FETs with threshold voltages close to zero are then used as the basic blocks to construct more complex PTL integrated circuits.40 Compared with the conventional CMOS configuration, PTL has been demonstrated to be a more efficient logic style for CNT-based integrated circuits because PTL can take full advantage of the CNT CMOS FETs.13,40,41 It is well-known that a programmable and multifunctional digital unit can provide an important and efficient module fashion to construct complex integrated circuits for nanoelectronics in which the fabrication of high-performance devices and circuits is not perfect and optimized.42 Here we show that a PTL-style CNT 8-T unit can be used as a basic module for generating various logic functions and for constructing more complex electronic systems. Circuit diagram of the 8-Tunit is shown in Figure 1a in
The CNT-based electronics has advanced significantly since the appearance of the first CNT FETs in 1998.1,2 High-quality single-walled semiconducting CNTs have been successfully used as channel material to construct both n- and p-type FETs that outperform stat-of-the-art silicon CMOS FETs with similar gate length.6−8,31−33 More recently, CNT-based FETs have been scaled down to sub-10 nm regime.34,35 These short channel CNT FETs are found to preserve excellent gate controlling ability and show negligible short channel effect, promising much better scaling down potential than silicon FETs.34,35 However, the development of CNT FET integrated circuits lagged far behind individual devices because only a few scalable methods have been developed for fabricating CNT FETs owing to the well-known material challenge as to how to obtain suitable semiconducting CNTs at the required locations in a chip.36 Extensive studies have been devoted to wafer-scale CNT device fabrication and complicated ICs16−19 and even a computer construction.20 However, CNT FETs were usually fabricated on CNT-network or aligned semiconducting CNT arrays with degraded performance during removing metallic CNTs from the array; the thus fabricated FETs either show performance that is no comparison with that of state-of-the-art Si FETs or cannot be readily scaled down to meet the requirement of the next generation technology. The dilemma is that we cannot construct high-performance ICs with optimized performance and small-size CNT FETs that can be built only on individual undamaged CNTs. Therefore, constructing ICs with FETs built on individual CNTs is currently the viable way to explore the performance and density potential of CNT ICs. However, individual CNT-based ICs are generally built on a single individual CNT in order to comply with the performance uniformity issues of CNT FETs, and the complexity and layout of IC are thus severely restricted. As a result, most of published CNT CMOS ICs on individual CNT are just simple logic and arithmetical gates, and to date the most complicated ICs are 5stage oscillator and 1-bit full adder/subtracter.10,11,37−41Although constructing complicated ICs on individual CNTs with different diameters and properties is a valid and necessary way to explore the potential advantages of CNT electronics at circuit level, this fabrication has not been demonstrated so far owing to the difficulty in controlling uniformity of CNT FETs based on different CNTs. Obviously FETs fabricated on different CNTs with different chiralities must present performance fluctuation much larger than those fabricated on the same CNT. It is thus an urgent task to develop an efficient method to build complex ICs on different CNTs with large property fluctuation In this paper, we explored the possibility of constructing complicated ICs on different CNTs by utilizing a modularized method. An 8-transistor (8-T) unit with pass-transistor-logic (PTL) style is designed and built on two individual CNTs with different electronic properties, and this 8-T unit is further used as the basic module to construct more complex ICs. The 8-T unit shows excellent tolerance to the property difference between CNTs and demonstrates as a powerful functional generator that can realize all logic and arithmetic functions. Using the 8-T unit as the basic module we designed and demonstrated an 8-bits BUS system that is an important IC used to transfer data between CPU, memory, and input/output systems. The BUS system works well although it contains up to 46 FETs built on 6 different semiconducting CNTs, which is so far the most complicated IC based on individual CNTs.
Figure 1. CNTs-based 8-T function generator. (a) Circuit diagram. (b) SEM image showing a real 8-T function generator that was fabricated on two CNTs (marked with two white dotted lines) and (c) the truth table. (d) An ideal compact layout design for an 8-T unit fabricated on two parallel semiconducting nanotubes. The rectangular region marked in red dotted box is the active region with an area of about 3λ × 17λ with λ being the minimum processable scale. The scale bar in Figure 1b denotes 100 μm. B
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
Figure 2. Simulated and measured outputs from a CNT-based 8-T function generator. (a) Simulated results of the 8-T unit for 16 distinct logic operations. The simulated results that are marked by red, blue, and pink dotted boxes correspond to the function of NAND, NOR, and XOR respectively. (b) Experimental measurements for three typical functions realized by the same 8-T unit for all four distinct input combinations. The working principle analysis of (c) NAND, (d) NOR, and (e) XOR functions of the 8-T unit.
realized for a given input combination (A, B). The selection of the logic function is made by the combinations of (G0, G1, G2, G3), and the truth table of the 8-T unit is given in Figure 1c. While the 8-T unit may be realized on a single CNT, it can be designed with a more compact and symmetrical layout using two parallel semiconducting CNTs (Figure 1b). The total area of the 8-T unit shown in Figure 1b is about 8000 μm2. This large area is caused by the large spacing between the two CNTs used. The modularized method that we demonstrated in this work is still dependent on the position of semiconducting CNTs, but it can be further extended to a prefabrication design on uniform all-semiconducting CNT array. In an optimized design, assuming an ideal spacing between the two CNTs or a
which 4 p-FETs and 4 n-FETs are used. It should be noted that the 8-T unit can be readily realized using two parallel semiconducting CNTs with symmetric layout and shown in Figure 1b is the scanning electron microscopy (SEM) image of such a fabricated 8-T unit. This unit is designed as a universal function generator and can be used to realize all logic and arithmetic functions between A and B according to a set of instructions (G0, G1, G2, G3). The output from the 8-T unit can be summarized as Out = G0·AB ̅ ̅ + G1·A̅ B + G2·AB̅ + G3·AB
(1)
where A and B are inputs, and G0−G3 are programming voltages. According to eq 1, a total of 16 distinct outputs can be C
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
efficient module to construct more complicated ICs on different CNTs. One important advantage of CNT-based ICs over silicon CMOS comes from their ability to operate at low supply voltages. This is because CNT allows the use of metals of different work function as the gate to effectively adjust the threshold voltage of CNT CMOS FETs, for example, to near zero (see Figure S1e in Supporting Information).32,34 As a result, PTL logic style that is more efficient than CMOS but requires zero threshold voltage may be readily implemented using CNT CMOS FETs. The 8-T unit illustrated in Figure 1a is designed using PTL style and thus has the potential of operation at low supply voltage. As an example, the NAND function of the 8-T unit is measured under a supply voltage of 0.5 V, and the output voltages for all four input combinations of (A,B) follow the standard NAND logic functions as shown in Figure S3 (in Supporting Information). Among the four outputs, the ones corresponding to the input combinations (0, 0) and (1, 0) are very close to the ideal high level (0.5 V). The outputs for the other two input combinations (0, 1) and (1, 1) are slightly degraded, where the high and low outputs show voltage levels centered on 0.45 V (see Figure S3c in Supporting Information) and 0.015 V (see Figure S3d in Supporting Information) respectively. The three logic functions demonstrated in Figure 2 are key components for the arithmetic logic unit (ALU) in a computer system. In fact the 8-T unit can be used as a powerful building block for constructing general ICs because it can realize all logic and arithmetic functions and present good tolerance to the inhomogeneity in CNTs. As an example, an 8-bits data BUS circuit was constructed by using 8-T units as the building blocks (Figure 3). Data BUS is a frequently used circuit and an important part in a computer system to transfer data between CPU and memory or input/output circuits as shown in Figure 3a.43,44 The circuit diagram of this data BUS is shown in Figure 3b, which contains four 8-T units (U1−U4), four CNTs-based CMOS inverters, three individual n-type, and three individual p-type CNT FETs. A total of 46 CNT FETs fabricated on six individual semiconducting CNTs are used to construct the 8-bit BUS circuit, and an SEM image of an as-fabricated IC is shown in Figure 3c. It should be noted that to successfully fabricate the 8-bit BUS system directly as designed (Figure 3c), the yield for the fabrication of 8-T units should be very high, close to 100%. However, with the current CNT growth technique there is no guarantee that the required semiconducting CNTs will present in the right locations. Instead, in this work we use a modularized method to construct complex circuits. Many 8-T units are first fabricated on available semiconducting CNTs, and those functioning 8-T units are selected and connected to form the designed circuit. For the BUS circuit, four 8-T units are selected and measured before constructing the final BUS circuit. The whole BUS circuit is realized by connecting the four selected 8-T units with additional CMOS inverters and controlling FETs and a typical layout of a BUS circuit fabricated in this way is shown in Supporting Information Figure S4. While not ideal, circuits as complex as BUS circuits can be constructed although the current yield of 8-T unit fabrication is still not very high, demonstrating that the modularized method is expedient but effective given current level of material synthesis and device fabrication. In principle, we can fabricate complex circuit such as a BUS circuit as shown in Figure 3c without selecting 8-T units prior, either on individual or parallel
high density parallel array of all-semiconducting CNTs is available,14 the 8-T unit can be aggressively scaled down with finer layout design and patterning technology. The parasitic capacitance and resistance that originated from the redundantly interconnected wires and pads of transistors may in principle be avoided if a compact layout is used based on CNT films of uniform density. According to the prospective layout shown in Figure 1d, total active area of the compacted 8-T unit can be scaled down to about 51λ2 with λ being the minimum processable line width. If λ = 20 nm (representing state-of-theart fabricating process capability) is used, the unit size down to 0.02 um2 is achievable. As a comparison, the whole area of a 6T SRAM unit using 22 nm silicon CMOS technology is about 0.092 μm2.33 All 16 logic functions realizable by the 8-T unit or function generator for a given pair of inputs A and B are first verified using a simulation tool HSPICE (companied with a lookuptable model, see Methods), and simulation results are shown in Figure 2a. Among these 16 logic functions, three functions are experimentally demonstrated and illustrated in Figure 2b. Unless otherwise noted, all high level in this paper is set to 1 V and low level to zero or ground, that is, only one supply voltage is used in powering our CNT ICs. NAND (A̅ B or A + B̅ ) function is first considered and tested. To implement this function, the programming voltages (G0, G1, G2, G3) are set to (1, 1, 0, 1). These voltages are respectively transmitted to the output F under the bias combination of (A, B), and the detailed operational principle is illustrated through the circuit diagram in Figure 2c. The measured outputs for all four (A, B) input combinations (see the left panel in Figure 2b) are all correct with the output voltage of high level “1” ranging between 0.75 to 1.0 V while output voltage of low level “0’’ranging from 0 to 0.2 V. We now consider the logic function NOR, that is, A + B or A̅ B̅ . The programming voltages (G0, G1, G2, G3) are set to (0, 0, 0, 1), which are respectively transmitted to the output F at the bias combination of (A, B), and the detailed operational principle is illustrated in the circuit diagram in Figure 2d. The measured outputs for all input combinations are shown in the middle panel of Figure 2b, which are consistent with the expected logic values of the truth table (Figure 1c). It should be noted that the output voltages for all input combinations are almost perfect, that is, around 0 V for low level and 1 V for high level. XOR is a very important logic gate, as well as a basic arithmetic function, that is, semiadder (or semisubtractor). This logic can be realized by the 8-T unit by setting programming voltages (G0, G1, G2, G3) as (0, 1, 1, 0), and the detailed operational principle is illustrated in the circuit diagram shown in Figure 2e. The result presented in the right panel of Figure 2b indicates that the XOR logic is well realized with almost perfect “0” and “1” states. As a universal building block for constructing general ICs, the 8-T unit should provide good tolerance to the inhomogeneity in the CNTs used. To test this inhomogeneity tolerance of the 8-T unit on CNTs, we built the 8-T unit on two CNTs with very different diameters and thus different transfer characteristics (see Figure S2 in Supporting Information). Although electric properties such as the on-state current of the two CNTs used are very different, that is, 0.7 μA versus 2 μA, the final circuit as shown in Figure 1b works fine (Figure 2b). We thus expect that the 8-T unit presents good tolerance to the inhomogeneity in the CNTs used and can be used as an D
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
G0 (or G1, or G2, or G3). It is obvious that a pair of 8-T units connected in series can be used to transfer data between Gi (i = 0, 1, 2, 3) of one unit and that of the other. Then in the 8-bits BUS circuit as shown in Figure 3b, two pairs of 8-T units are used to form two branches to transfer data, that is, the upper one is formed between U1 and U2 (for the paths between A0− A3 and F0−F3), and the lower one is formed between U3 and U4 (for the path between A4−A7 and F4−F7). In this way, the 8bit BUS system can be readily extended into higher bits, that is, 16-bits BUS system when 10 8-T units are used. Selection between the two branches is made by C2. Explicitly, the upper branch is selected if C2 = 0, and the lower branch is selected if C2 is set to 1. Within a branch, C0 and C1 are used to select the path to transfer data. Furthermore, the direction of data transfer may be controlled by Dir, that is, data will be transferred from left to right when Dir is set to “1” and be transferred from right to left when Dir is set to “0”. The complete data transmitting paths of the 8-bit BUS are all listed in Figure 4a. One of the major difficulties in implementing PTL circuits is that PTL gates do not provide gain of more than one. As a result signal degradation is unavoidable in PTL circuits, especially after passing through seven-stage cascaded gates as in a typical path in a BUS circuit.44 Cascading CMOS inverters with large gains in the path is an effective method to restore the signal to its ideal value in a multistage circuit.13 In the middle part of the BUS circuit (Figure 3b), two cascaded inverters (with typical characteristics shown in Figure 5S in Supporting Information) are used to restore the data passing through each 8-T unit. The CNT CMOS inverter is efficient in providing high voltage gain (typically about 50) and with excellent noise margin (high noise margin 0.44 V and low noise margin 0.46 V) owing to the symmetric nature and suitably controllable threshold voltages of p-type and n-type CNT FETs. This high gain and large noise margin of the CNT inverter ensures that the degraded signal is restored and the data being transferred does not suffer from large losses or errors in the BUS circuits. An example of the data after being transferred via the path from A6 to F6 is shown in Figure S6c of Supporting Information. When a square-wave signal with a period of 5 s and 50% duty ratio is applied to A6, an output square-wave signal with similar period and duty ratio is received at F6. This proves that this BUS circuit responses well to the input, that is, the signal can be transferred by the selected path. Sequential measurements on the bus system were made using a homemade probe card system (see Figure 6S in Supporting Information) and some representative results are shown in Figure 4b. For clarity, only those results for odd index paths in the 8-bit BUS system are given, that is, data transfers from F1 to A1, F3 to A3, F5 to A5, and F7 to A7. Because the BUS system is bidirectional, an inverse transfer path, that is, path 7 from A7 to F7, is also tested to verify the direction control bit Dir. The address and direction of data transfer are set by (C0, C1, C2, Dir), for example, if (C0, C1, C2, Dir) are set as (1, 1, 1, 0), the seventh path is opened and the signal is allowed to be transferred from A7 to F7. On the other hand, if (C0, C1, C2, Dir) are set as (1, 1, 1, 1), the same seventh path is opened but the signal is allowed to be transferred from F7 to A7. It is obviously that in our BUS system the signal can be transferred from the original termination (A1,...,7 or F1,...,7) to the target one by passing through 7 cascaded gates without much degradation, which is made possible by the introduction of CMOS inverters between the 8-T units and the excellent control on the threshold voltages of the FETs involved.
Figure 3. Function and structure diagrams of a complete 8-bits BUS circuit designed by using 8-T units as basic modules. (a) Block diagram showing the function of BUS systems in a computer system. A BUS system is used as the connection between different parts of the computer to communicate data. (b) The design diagram of an 8-bits BUS system. (c) SEM image showing an as-fabricated BUS circuit based on five semiconducting CNTs selected through electrical measurement. The scale bar denotes 50 μm.
arrays of semiconducting CNTs as the manufacturing technology is further improved. Without requiring additional or redundant devices, the BUS circuit layout in Figure 3c is significant more compact than that shown in Supporting Information Figure S4. The main function of a BUS circuit is to transmit data selectively between systems. For an 8-bits BUS, the path used to transmit data may be selected from eight available paths by controlling terminations (C0, C1, C2), in which C0 and C1 are respectively connected to inputs A and B of all 8-T units (see Figure 1a), while C2 is used to control the state of four individual FETs (N1, P1, N3, P3). In fact, the 8-T unit can also act as a four-to-one multiplexer (MUX) circuit in which one of the four inputs (G0 to G3) can be selected to connect with the output according to the combination of control voltages (A, B). For example, a channel can be opened between the input G0 (or G1, or G2, or G3) and the output if the control voltages (A, B) are set as (0,0) [or (0, 1), or (1, 0), or (1, 1)], and data can thus be transferred between the output and one of the inputs E
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
Figure 4. Sequential measurement results of an 8-T units based BUS system. (a) The truth table of the BUS system for all possible combinations of inputs (C0, C1, C2, Dir). (b) Sequential measurement results of the BUS system. The outputs shown in the lower part of the figure represent (from top to bottom) F1 → A1, F3 → A3, F5 → A5, F7 → A7, and A7 → F7 respectively, and the corresponding control voltages are shown in the upper part of the figure representing (C0, C1, C2, Dir) = (1, 0, 0, 0), (0, 1, 0, 0), (1, 0, 1, 0), (1, 1, 1, 0), and (1, 1, 1, 1) respectively.
CNTs were identified via field-effect measurements using the substrate as the back gate, and then were used for further device fabrication. High-performance CNT-based CMOS FETs were fabricated via the well-developed doping-free approaches. Fourteen nanometer HfO2 was deposited by atomic layer deposition (ALD) as oxide dielectric and followed by 10 nm Pd deposited as the top-gate electrode to adjust the threshold voltage of FETs to center around 0 V. While n-type CNTFETs were fabricated by using 60 nm Sc as the contact metals, p-type CNT FETs were fabricated using 60 nm Pd as the contact metals. Measurement of Circuits. The 8-T function generator circuit is measured using a probe station that is equipped with 7 probes. In addition, a semiconductor analyzer (Keithley 4200) is used to set programming voltage, and a signal generator (Agilent MXG N5181A) is used to apply square signals to the inputs (A, B). The output is measured by an oscilloscope (Agilent DSO7054A). Sequential measurement of the BUS system is illustrated in Figure.S6 (Supporting Information). To complete this measurement, all electrode pads are led to the edge of the wafer, and a probe card with 40 terminations is used to connect the pads for applying and detecting signals. A matrix switch (Agilent 34972A) is used to allocate sequential signals to each probe and also collect the output signals. When the control voltages (C0, C1, C2, Dir) are set to choose the transmit path, a square signal generated by signal generator (Agilent MXG N5181A) is applied to the input termination of chosen path. The output signal at the target output termination is then measured through Keithley 4200. Simulation of CNT ICs. The CNT-based ICs are simulated using the semiempirical HSPICE method similar to ref 46 but with the CNT FET model we developed independently. The device model is a semi-empirical one in which the measured transfer and output characteristics (Id−Vgs and Id−Vds) of both n-type and p-type CNT FETS were tabulated and used directly
While only result on a BUS system is demonstrated, the 8-T unit introduced in this work can indeed be used as a powerful module for constructing general CNT ICs, such as multiplexer, field-programmable gate array (FPGA), and ALU (relevant circuit diagrams are shown in Figure S7 in Supporting Information). Therefore, the modularized method is a universal and efficient way to construct large scale CNT ICs. The method is particularly valuable now because it allows us to explore the feasibility and performance limits of complex CNT ICs while the outstanding CNT material problems are not completely solved. In conclusion, a modularized method for constructing general ICs on individual CNTs is proposed and experimentally demonstrated. The proposed module is an 8-T unit consisting of 4 pairs of CMOS FETs designed using PTL style and two parallel semiconducting CNTs. It is demonstrated that although the two CNTs on which the 8-T unit is built may be very different, for example, with different diameters and onstate currents, the 8-T unit can work very well yielding 16 different logic functions, including NAND, NOR, and XOR. It is further shown that the 8-T unit may be used as a building block for constructing general ICs. An 8-bits BUS system consisting of 46 FETs was built on 6 different CNTs. It was found that the BUS system is able to provide full BUS function for transferring data in bidirections via eight distinct paths, and the signal is found to suffer tolerable degradation during the transfer although the signal needs to pass through as many as seven cascading logic gates in the system. The modularized method may also be used directly for constructing ICs using network type CNT films or arrays of parallel CNTs and allows us to explore the potentials and performance limits of CNT integrated circuits although the outstanding CNT materials problems are not yet fully solved. Methods. Fabrication of CNT and FETs. The CNTs used in this work were directionally grown on a Si substrate covered with 300 nm SiO2 layer,45 and semiconducting single-walled F
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
(17) Kang, S. J.; et al. High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. Nat. Nanotechnol. 2007, 2, 230−236. (18) Sun, D.-M.; et al. Flexible high-performance carbon nanotube integrated circuits. Nat. Nanotechnol. 2011, 6, 156−161. (19) Zhang, J.; Wang, C.; Zhou, C. W. Rigid/flexible transparent electronics based on separated carbon nanotube thin film transistors and their application in display electronics. ACS Nano 2012, 8, 7412− 7419. (20) Shulaker, Max M.; et al. Carbon nanotube computer. Nature 2013, 501, 526−530. (21) Jin, H. S.; Dunham, N. S.; Song, J.; Xie, X.; Kim, J.-H.; Lu, C.; Islam, A.; Du, F.; Kim, J.; Felts, J.; Li, Y.; Xiong, F.; Wahab, A. M.; Menon, M.; Cho, E.; Grosse, L. K.; Lee, J. D.; Chung, H. U.; Pop, E.; Alam, A. M.; King, P. W.; Huang, Y.; Rogers, A. J. Using nanoscale thermocapillary flows to create arrays of purely semiconducting singlewalled carbon nanotubes. Nat. Nanotechnol. 2013, 8, 347−355. (22) International Technology Roadmap for Semiconductors, 2011 ed. http://public.itrs.net/. (23) Xiang, J.; Lu, W.; Hu, Y.; Yan, H.; Lieber, M. C. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nat. Nanotechnol. 2006, 441, 489−493. (24) Jiang, X.; Xiong, Q.; Nam, S.; Qian, F.; Li, Y.; Lieber, M. C. InAs/InP Radial Nanowire Heterostructures as High Electron Mobility Devices. Nano Lett. 2007, 7, 3214−3218. (25) Bryllert, T.; Wernersson, L.-E.; Froberg, L. E. Samuelson, Lars. Vertical high-mobility wrap-gated InAs nanowire transistor. IEEE Electron Device Lett. 2006, 27, 323. (26) Wang, X.; Ouyang, Y.; Jiao, L.; Wang, H.; Xie, L.; Wu, J.; Guo, J.; Dai, H. J. Graphene nanoribbons with smooth edges behave as quantum wires. Nat. Nanotechnol. 2011, 6, 563−567. (27) Yao, J.; Yan, H.; Lieber, M. C. A nanoscale combing technique for the large-scale assembly of highly aligned nanowires. Nat. Nanotechnol. 2013, 8, 329−335. (28) Sprinkle, M.; Ruan, M.; Hu, Y.; Hankinson, J.; Rubio-Roy, M.; Zhang, B.; Wu, X.; Berger, C.; De Heer, W. A. Scalable templated growth of graphene nanoribbons on SiC. Nat. Nanotechnol. 2010, 5, 727−731. (29) Yao, J.; Yan, H.; Das, S.; Klemic, F. J.; Ellenbogen, C. J.; Lieber, M. C. Nanowire nanocomputer as a finite-state machine. Proc. Natl. Acad. Sci. U.S.A. 2014, 111, 2431−2435. (30) Saito, R.; Dresselhaus, G.; Dresselhaus, M. S. Physical Properties of Carbon Nanotubes; Imperial College Press: London, 1998. (31) Javey, A.; et al. Carbon nanotube field-effect transistors with integrated ohmic contacts and high-κ gate dielectrics. Nano Lett. 2004, 4, 447−450. (32) Zhang, Z. Y.; et al. Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage. Nano Lett. 2008, 8, 3696−3701. (33) Wang, Z. X.; et al. Yttrium oxide as a perfect high-κ gate dielectric for carbon-based electronics. Nano Lett. 2010, 10, 2024− 2030. (34) Franklin, A. D.; Chen, Z. Length scaling of carbon nanotube transistors. Nat. Nanotechnol. 2010, 5, 858−862. (35) Franklin, A. D.; et al. Sub-10 nm carbon nanotube transistor. Nano Lett. 2012, 12, 758−762. (36) Rutherglen, C.; Jain, D.; Burke, P. Nanotube Electronics for Radiofrequency Applications. Nat. Nanotechnol. 2009, 4, 811−819. (37) Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon nanotube inter- and intramolecular logic gates. Nano Lett. 2001, 1, 453−456. (38) Bachtold, A.; et al. Logic circuits with carbon nanotube transistors. Science 2001, 294, 1317−1320. (39) Chen, Z.; et al. An integrated logic circuit assembled on a single carbon nanotube. Science 2006, 311, 1735−1735. (40) Ding, Li; et al. Carbon nanotube field-effect transistors for use as pass transistors in integrated logic gates and full subtractor circuits. ACS Nano 2012, 6, 4013−4019.
to describe the DC characteristic of the 3-terminal FET. The AC characteristics of the CNT FETs are derived using the intrinsic and parasitic parameters of the self-aligned device structure and measurement system.
■
ASSOCIATED CONTENT
S Supporting Information *
Additional figures. This material is available free of charge via the Internet at http://pubs.acs.org.
■
AUTHOR INFORMATION
Corresponding Authors
*E-mail: (Z.Y.Z.) [email protected]. *E-mail: (L.M.P.) [email protected]. Notes
The authors declare no competing financial interest.
■
ACKNOWLEDGMENTS This work was supported by the Ministry of Science and Technology of China (Grants 2011CB933001 and 2011CB933002), National Science Foundation of China (Grants 61322105, 61271051, 61376126, 61321001, and 61390504), and Beijing Municipal Science and Technology Commission (Grants Z131100003213021 and 20121000102).
■
REFERENCES
(1) Tan, S. J.; Verschueren, A. R. M.; Dekker, C. Room temperature transistor based on a single carbon nanotube. Nature 1998, 393, 49− 52. (2) Martel, R.; et al. Single- and multi-wall carbon nanotube fieldeffect transistors. Appl. Phys. Lett. 1998, 73, 2447−2449. (3) Ralph, K. C.; Paolo, L.; Victor, V. Z. Science and Engineering Beyond Moore’s Law. Proc. IEEE 2012, 100, 1720−1749. (4) Avouris, P.; Chen, Z. H.; Perebeinos, V. Carbon-based electronics. Nat. Nanotechnol. 2007, 2, 605−615. (5) Burghard, M.; Klauk, H.; Kern, K. Carbon-based field-effect transistors for nanoelectronics. Adv. Mater. 2009, 21, 2586−2600. (6) Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. J. Ballistic carbon nanotube field-effect transistor. Nature 2003, 424, 654−657. (7) Zhang, Z. Y.; et al. Doping-free fabrication of carbon nanotube based ballistic CMOS devices and circuits. Nano Lett. 2007, 7, 3603− 3607. (8) Ding, L.; et al. Y-contacted high-performance n-type single-walled carbon nanotube field-effect transistors: scaling and comparison with sc-contacted devices. Nano Lett. 2009, 9, 4209−4214. (9) Peng, L.-M.; Zhang, Z. Y.; Wang, S.; Liang, X. L. A doping-free approach to carbon nanotube electronics and optoelectronics. AIP Adv. 2012, 2, 041403. (10) Zhang, Z. Y.; et al. Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 2009, 3, 3781−3187. (11) Javey, A.; et al. Carbon nanotube transistor arrays for multistage complementary logic and ring oscillators. Nano Lett. 2002, 2, 929− 932. (12) Chen, Z. Y.; et al. An integrated logic circuit assembled on a single carbon nanotube. Science 2006, 311, 1735−1736. (13) Ding, Li; et al. CMOS-based carbon nanotube pass-transistor logic integrated circuits. Nat. Commun. 2012, 3, 677. (14) Franklin, A. The road to carbon nanotube transistors. Nature 2013, 498, 443−444. (15) Ding, L.; et al. Selective growth of well-aligned semiconducting single-walled carbon nanotubes. Nano Lett. 2009, 9, 800−805. (16) Cao, Q.; et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 2008, 454, 495−500. G
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
Nano Letters
Letter
(41) Ding, Li; et al. Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V. Appl. Phys. Lett. 2012, 100, 263116−263116. (42) Yan, H.; et al. Programmable nanowire circuits for nanoprocessors. Nature 2011, 470, 240−244. (43) Auth, C.; et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, selfaligned contacts and high density MIM capacitors. IEDM 2012, 131− 132. (44) Weste, N. H. E.; Harris, D. CMOS VLSI Design: a Circuits and System Perspective, 3rd ed.; Addison Wesley: Reading, MA, 2004. (45) Zhou, W.; et al. Copper catalyzing growth of single-walled carbon nanotubes on substrates. Nano Lett. 2006, 6, 2987−2990. (46) Dwyer, C.; et al. Semi-empirical SPICE models for carbon nanotube FET logic. Proc. 4th IEEE Conf. Nanotechnol. 2004, 386− 388.
H
dx.doi.org/10.1021/nl5001604 | Nano Lett. XXXX, XXX, XXX−XXX
