REVIEW OF SCIENTIFIC INSTRUMENTS 86, 016116 (2015)
Note: The design of thin gap chamber simulation signal source based on field programmable gate array Kun Hu,1,2,a) Houbing Lu,1,2,3 Xu Wang,1,2 Feng Li,1,2 Futian Liang,1,2,4 and Ge Jin1,2,b)
State Key Laboratory of Particle Detection & Electronics, University of Science and Technology of China, Hefei 230026, China 2 Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China 3 Hefei Electronic Engineering Institute, Hefei 230037, China 4 Hefei National Laboratory for Physical Sciences at the Microscale, University of Science and Technology of China, Hefei 230026, China
1
(Received 4 December 2014; accepted 14 January 2015; published online 29 January 2015) The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability. C 2015 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4906604] The Thin Gap Chamber (TGC), an important gas detector, is widely applied in particle detector and nuclear science. In the ATLAS detector,1 the TGC is used for muon trigger. The structure of TGC detector is illustrated in Fig. 1. The pads are used through a 3-out-of-4 coincidence to identify muon tracks roughly pointing to the Interaction Point (IP). The charge of all strips is readout for offline track reconstruction. The New Small Wheel (NSW) is constructed as part of the upgrade to deal with high luminosities.2 In the NSW trigger system, the TGC is used for the primary trigger, which requires that TGC can provide both trigger and precision measurements. In previous trigger system, the fake trigger is caused by low energy protons generated in materials located between the Small Wheel (SW) and End-cap Muon detector (EM) by hitting the end-cap trigger chamber. 2012’s data demonstrate that approximately 90% of the muon trigger in the end-caps is fake.3 In order to solve the problem, it is proposed by the ATLAS collaboration to replace the muon small wheel with the NSW. The basic detector design for the NSW has two quadruplets. Each quadruplet contains four TGCs, each TGC with multi-channel pad, wire, and strip readout. The ATLAS detector is designed to detect the secondary particles produced by p-p collision. In the first long shutdown (LS1) during 2013-2014, the luminosity of the accelerator can reach the designed value of 1 × 1034 cm−2 s−1. For the second long shutdown (LS2) in 2018, the luminosity will be increased to 2-3×1034 cm−2 s−1, and the bunch spacing is 25 ns. In other words, the secondary muon randomly hits the TGC detector per 25 ns. At present, the new trigger electronics for LS2 is under design. In order to test the trigger electronics to be developed, we design a special multi-channel TGC simulation
a)This research was performed while Kun Hu was at State Key Laboratory of
Particle Detection & Electronics, University of Science and Technology of China, Hefei, Anhui 230026, China. b)Author to whom correspondence should be addressed. Electronic mail: [email protected] 0034-6748/2015/86(1)/016116/3/$30.00
signal source, which can randomly generate signals in 256 channels. Targeting the multi-strip and multi-pad structure of TGC, we design three modes of the signal source. In first mode, the source uniformly outputs 256-channel signal for every channel of the trigger electronics. For the pad of TGC, only one pad can generate the output signal when an event strikes the detector. According to the feature above, the second mode is defined as the “pad-mode.” In the pad-mode, the source randomly generates one signal in 256 channels. For the strip of detector, when one event hits the detector, not only the hit strip but the adjacent strip can output signal due to the induced charge. Therefore, the last mode is the “strip-mode.” In the strip-mode, the adjacent three signals simultaneously output in a given period. The core of the design is based on Field Programmable Gate Array (FPGA). The FPGA can be reprogrammed, as a result, having more flexibility. The development of FPGA is easier and faster. Due to randomly output simulation signal, the source requires the generation of randomness. In our system, the main task of FPGA is to generate source of randomness. Typically, there are two approaches to generate random number, including pseudorandom number generator (PRNG) and true random number generator (TRNG). In order to approximate the actual TGC detector, the TRNG is an optimal option. The traditional TRNG is based on the thermal noise.4,5 Nowadays, there is a trend that some methods of the digital circuit are used for the generation of random bit sequences. It is proposed that the generator is constructed by using the programmable device based on metastability.6,7 Recently, the generator using ring oscillator (RO) based on FPGA gives an easy way to generate a random bit sequence, which is based on several equal length ROs composing of odd number of inverters.8 Moreover, a theoretical proposal for a random number generator is given. The outputs from ROs are XORed together and sampled by a D flip-flop. The entropy source of the method is the jitter from each RO. The jitter actually originates from the noise of the semiconductor
86, 016116-1
© 2015 AIP Publishing LLC
016116-2
Hu et al.
Rev. Sci. Instrum. 86, 016116 (2015)
FIG. 1. The structure of TGC detector, which consists of a grid of 50 µm gold-plated tungsten wires with 1.8 mm pitch, located between two cathode planes at a distance of 1.4 m from the wire plane. The strip runs perpendicular to the wires and the pad covers large rectangular surfaces.
forming the RO. The jitter is assumed to cover the whole time-axis while several ROs are superimposed together. The logic low and logic high level will be uniformly distributed in the sampling period. The weakness of the approach is that the XOR gate cannot cope with the high-speed transitions from ROs. The synthesis for XOR gate is the look-up table (LUT) in FPGA. The setup-time and hold-time for LUT eventually determine the performance of the random number generator. To deal with the drawback mentioned above, an enhanced TRNG based on ROs is proposed by adding an extra D flip-flop after each RO.9 The diagram of the enhanced TRNG is shown in Fig. 2. The frequency of RO is dependent of the total delay of inverters in each ring. The higher the oscillated frequency is, the more percentage the jitter in the oscillated period can reach. Therefore, the number of inverters should be as few as possible. The advantage of the enhanced TRNG is that the signal at the input of the XOR gate is synchronized by a low sampling clock. Lowering the rate of change between the logic low and logic high levels will satisfy the limit of the setup-time and hold-time in FPGA. The enhanced TRNG has no bias and therefore no requirement for complicated post-processing. Eventually, the enhanced TRNG is applied in our design of TGC simulation signal source. The block diagram and the photograph of our hardware are illustrated in Fig. 3. In order to simultaneously evaluate 256 channels of the under-develop trigger electronics, we set the first mode, which is implemented in FPGA. To generate 256 random numbers, we use 8-bit random sequence in parallel. It is required that there is no missing code in 256 numbers. Each of 256 numbers can be randomly generated. If every bit of the generated number is the true random number, the 8-bit bus should have no missing code. For the pad-mode
FIG. 2. The block diagram of the enhanced TRNG.
FIG. 3. The block diagram (a) and the photograph (b) of TGC signal source. The source can be configured into three modes through an Ethernet interface. The capacitor array of 1 pF is placed for voltage-to-charge conversion. The charge signal is delivered into the developing trigger electronics through Zebra-256 connector.
and strip-mode of the signal source, the post-processing is to decode with the corresponding function, respectively. The three modes are configurable through an Ethernet interface, which is implemented in Media Access Control (MAC) layer of the Ethernet. The output signal from FPGA is 2.5 V Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS) level. For a true random bit sequence, the probability of logic one should be close to 0.5, let X1, X2, ..., X n be n independently random bit sources generated by ROs, their expected values are E(X1), E(X2), ..., E(X n ), respectively. If E(X1) = E(X2) = ··· = E(X n ) = µ, the expected value of the XOR of n sequence is given by7 E ′ = E(X1 ⊕ X2 ⊕ ··· X n ) =
1 1 + (−2)n−1(µ − )n . 2 2
(1)
The formula can be expressed as E′ =
1 1 − (1 − 2µ)n . 2 2
(2)
Since µ ∈ (0,1), |1 − 2µ| ∈ (0,1). |E ′| will exponentially go to 0.5. In other words, the probability of ones will be fast close to 0.5 as the number n of ROs goes highly. For the case of n = 4 and µ = 0.51, E ′ is 0.5-8 × 10−8. The accuracy of the probability of ones is adequate for our system. Finally, each of the random bit sequence is generated by 4 ROs. For an 8-bit number comprising 8 random bit sequences, the expected value from the output of the XOR gates is E1′, E2′, ..., E8′, respectively. For a random bit sequence, the expected value is nearly equal to the probability of ones we observe, the probability P11111111 of a 8-bit number
016116-3
Hu et al.
Rev. Sci. Instrum. 86, 016116 (2015)
TABLE I. The bias of pre-constraint and post-constraint. n
Pre-constraint
Post-constraint
3 5 7 9 11
2.9 × 10−4
2.6 × 10−4 4.8 × 10−4 3.2 × 10−4 9.5 × 10−5 5.8 × 10−4
5.0 × 10−4 7.5 × 10−4 1.9 × 10−4 8.2 × 10−4
“11111111” is given by P11111111 = E1′ · E2′ ··· E8′ .
(3)
Since = = ··· = ≈ 0.5, the P11111111 is about 1/28. Actually, the probability of any of 8-bit random number is about 1/28 because the probability of ones is approximately equal to the probability of zeros for every random bit sequence. The experiments are carried out based on a Virtex-6 FPGA. The random bit sequence generated by ROs is stored in an internal First In and First Out (FIFO) and subsequently transmitted to Personal Computer (PC) software through Ethernet interface. The random bit sequence is read out from the FIFO and stored in a file. A maximum size of the file is 1 MB. The sampling frequency in FPGA is 40 MHz. For the random bit constructed by ROs, the assumption is that the equal-length ring oscillator has the same oscillated frequency.8 Actually, the frequency is different from each other due to P&R (place and route) in Xilinx ISE software. Also, the delay of every LUT is not equal each other. However, these inverters can be constrained in a common region, decreasing the delay of the route. For the Virtex-6 family, there are four LUTs in every slice. In our design, every ring is constrained in the adjacent slices. The results of the ROs constructed by different numbers n of the inverters are shown in Table I, where the bias (|E ′ − 0.5|) for pre-constraint and post-constraint is listed. From the table, it is apparent that the bias decreases after the constraint. Considering the resource of the FPGA, the ROs constructed by 3 inverters are used for 8-bit random number. A histogram is plotted in Fig. 4. The size of 8-bit random number is 1 MB. In order to evaluate these random numbers, we define the deviation σ of the probability of 8-bit random numbers. For a set of 8-bit random numbers, the probabilities of every random number are P0, P1, ..., P255, respectively. The deviation σ is defined as 1 1 2 1 2 [(P0 − ) + (P1 − ) + ··· σ2 = 256 256 256 1 2 +(P255 − ) ]. (4) 256 After the calculations, σ is 2.4 × 10−4. The relative deviation 1 σ/( 256 ) is less than 6.2%. The random number is relatively E1′
E2′
E8′
FIG. 4. The histogram of 8-bit random number. The size of 8-bit random number is 1 MB. The result shows that the 8-bit random numbers are uniformly plotted in the histogram.
uniform in the histogram. We have carried out a test for 6 h. The signal source works normally, and the relative deviation is still around 6.2%. In summary, we have designed a simulation signal source for TGC detector, randomly outputting 256-channel simulation signals. The source is based on TRNG implemented in FPGA. An analysis of the random bit sequence is given in this note. Targeting the feature of TGC detector, the source can be configured as different modes. The experimental results show that the relative deviation of the random numbers is less than 6.2%. This work is supported by the National Natural Science Foundation of China under Grant No. 11375179. 1ATLAS Collaboration, “The ATLAS experiment at the CERN Large Hadron
Collider,” J. Inst. 3, S0800S (2008) 2J. Wang, J. Chapman, J. Zhu, T. Dai, and B. Zhou, TDS Design Specification,
2013. 3ATLAS Collaboration, New small wheel techincal design Report No. CERN-
LHCC-2013-006 or ATLAS-TDR-020, 1995. Brederlow, R. Prakash, C. Paulus, and R. Thewes, “A low-power true random number generator using random telegraph noise of single oxidetraps,” in IEEE International Solid-State Circuits Conference (IEEE, 2006), pp. 1666–1675. 5C. S. Petrie and J. A. Connelly, “A noise-based IC random number generator for applications in cryptography,” IEEE Trans. Circuits Syst. 47, 615 (2000). 6C. Tokunaga, D. Blaauw, and T. Mudge, “True random number generator with a metastability-based quality control,” J. Solid-State Circuits 43, 78 (2008). 7P. Z. Wieczorek and K. Golofit, “Dual-metastability time-competitive true random number generator,” IEEE Trans. Circuits Syst. 61, 134 (2014). 8B. Sunar, W. J. Martin, and D. R. Stinson, “A provable secure true random number generator with built-in tolerance to active attacks,” IEEE Trans. Comput. 56, 109 (2007). 9K. Wold and C. H. Tan, “Analysis and enhancement of random number generator in FPGA based on oscillator rings,” in Proceedings of International Conference on Reconfigurable Computing and FPGAs (IEEE Computer Society, 2008), p. 385 4R.
Review of Scientific Instruments is copyrighted by AIP Publishing LLC (AIP). Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. For more information, see http://publishing.aip.org/authors/rights-and-permissions.
Note: The design of thin gap chamber simulation signal source based on field programmable gate array Kun Hu,1,2,a) Houbing Lu,1,2,3 Xu Wang,1,2 Feng Li,1,2 Futian Liang,1,2,4 and Ge Jin1,2,b)
State Key Laboratory of Particle Detection & Electronics, University of Science and Technology of China, Hefei 230026, China 2 Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China 3 Hefei Electronic Engineering Institute, Hefei 230037, China 4 Hefei National Laboratory for Physical Sciences at the Microscale, University of Science and Technology of China, Hefei 230026, China
1
(Received 4 December 2014; accepted 14 January 2015; published online 29 January 2015) The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability. C 2015 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4906604] The Thin Gap Chamber (TGC), an important gas detector, is widely applied in particle detector and nuclear science. In the ATLAS detector,1 the TGC is used for muon trigger. The structure of TGC detector is illustrated in Fig. 1. The pads are used through a 3-out-of-4 coincidence to identify muon tracks roughly pointing to the Interaction Point (IP). The charge of all strips is readout for offline track reconstruction. The New Small Wheel (NSW) is constructed as part of the upgrade to deal with high luminosities.2 In the NSW trigger system, the TGC is used for the primary trigger, which requires that TGC can provide both trigger and precision measurements. In previous trigger system, the fake trigger is caused by low energy protons generated in materials located between the Small Wheel (SW) and End-cap Muon detector (EM) by hitting the end-cap trigger chamber. 2012’s data demonstrate that approximately 90% of the muon trigger in the end-caps is fake.3 In order to solve the problem, it is proposed by the ATLAS collaboration to replace the muon small wheel with the NSW. The basic detector design for the NSW has two quadruplets. Each quadruplet contains four TGCs, each TGC with multi-channel pad, wire, and strip readout. The ATLAS detector is designed to detect the secondary particles produced by p-p collision. In the first long shutdown (LS1) during 2013-2014, the luminosity of the accelerator can reach the designed value of 1 × 1034 cm−2 s−1. For the second long shutdown (LS2) in 2018, the luminosity will be increased to 2-3×1034 cm−2 s−1, and the bunch spacing is 25 ns. In other words, the secondary muon randomly hits the TGC detector per 25 ns. At present, the new trigger electronics for LS2 is under design. In order to test the trigger electronics to be developed, we design a special multi-channel TGC simulation
a)This research was performed while Kun Hu was at State Key Laboratory of
Particle Detection & Electronics, University of Science and Technology of China, Hefei, Anhui 230026, China. b)Author to whom correspondence should be addressed. Electronic mail: [email protected] 0034-6748/2015/86(1)/016116/3/$30.00
signal source, which can randomly generate signals in 256 channels. Targeting the multi-strip and multi-pad structure of TGC, we design three modes of the signal source. In first mode, the source uniformly outputs 256-channel signal for every channel of the trigger electronics. For the pad of TGC, only one pad can generate the output signal when an event strikes the detector. According to the feature above, the second mode is defined as the “pad-mode.” In the pad-mode, the source randomly generates one signal in 256 channels. For the strip of detector, when one event hits the detector, not only the hit strip but the adjacent strip can output signal due to the induced charge. Therefore, the last mode is the “strip-mode.” In the strip-mode, the adjacent three signals simultaneously output in a given period. The core of the design is based on Field Programmable Gate Array (FPGA). The FPGA can be reprogrammed, as a result, having more flexibility. The development of FPGA is easier and faster. Due to randomly output simulation signal, the source requires the generation of randomness. In our system, the main task of FPGA is to generate source of randomness. Typically, there are two approaches to generate random number, including pseudorandom number generator (PRNG) and true random number generator (TRNG). In order to approximate the actual TGC detector, the TRNG is an optimal option. The traditional TRNG is based on the thermal noise.4,5 Nowadays, there is a trend that some methods of the digital circuit are used for the generation of random bit sequences. It is proposed that the generator is constructed by using the programmable device based on metastability.6,7 Recently, the generator using ring oscillator (RO) based on FPGA gives an easy way to generate a random bit sequence, which is based on several equal length ROs composing of odd number of inverters.8 Moreover, a theoretical proposal for a random number generator is given. The outputs from ROs are XORed together and sampled by a D flip-flop. The entropy source of the method is the jitter from each RO. The jitter actually originates from the noise of the semiconductor
86, 016116-1
© 2015 AIP Publishing LLC
016116-2
Hu et al.
Rev. Sci. Instrum. 86, 016116 (2015)
FIG. 1. The structure of TGC detector, which consists of a grid of 50 µm gold-plated tungsten wires with 1.8 mm pitch, located between two cathode planes at a distance of 1.4 m from the wire plane. The strip runs perpendicular to the wires and the pad covers large rectangular surfaces.
forming the RO. The jitter is assumed to cover the whole time-axis while several ROs are superimposed together. The logic low and logic high level will be uniformly distributed in the sampling period. The weakness of the approach is that the XOR gate cannot cope with the high-speed transitions from ROs. The synthesis for XOR gate is the look-up table (LUT) in FPGA. The setup-time and hold-time for LUT eventually determine the performance of the random number generator. To deal with the drawback mentioned above, an enhanced TRNG based on ROs is proposed by adding an extra D flip-flop after each RO.9 The diagram of the enhanced TRNG is shown in Fig. 2. The frequency of RO is dependent of the total delay of inverters in each ring. The higher the oscillated frequency is, the more percentage the jitter in the oscillated period can reach. Therefore, the number of inverters should be as few as possible. The advantage of the enhanced TRNG is that the signal at the input of the XOR gate is synchronized by a low sampling clock. Lowering the rate of change between the logic low and logic high levels will satisfy the limit of the setup-time and hold-time in FPGA. The enhanced TRNG has no bias and therefore no requirement for complicated post-processing. Eventually, the enhanced TRNG is applied in our design of TGC simulation signal source. The block diagram and the photograph of our hardware are illustrated in Fig. 3. In order to simultaneously evaluate 256 channels of the under-develop trigger electronics, we set the first mode, which is implemented in FPGA. To generate 256 random numbers, we use 8-bit random sequence in parallel. It is required that there is no missing code in 256 numbers. Each of 256 numbers can be randomly generated. If every bit of the generated number is the true random number, the 8-bit bus should have no missing code. For the pad-mode
FIG. 2. The block diagram of the enhanced TRNG.
FIG. 3. The block diagram (a) and the photograph (b) of TGC signal source. The source can be configured into three modes through an Ethernet interface. The capacitor array of 1 pF is placed for voltage-to-charge conversion. The charge signal is delivered into the developing trigger electronics through Zebra-256 connector.
and strip-mode of the signal source, the post-processing is to decode with the corresponding function, respectively. The three modes are configurable through an Ethernet interface, which is implemented in Media Access Control (MAC) layer of the Ethernet. The output signal from FPGA is 2.5 V Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS) level. For a true random bit sequence, the probability of logic one should be close to 0.5, let X1, X2, ..., X n be n independently random bit sources generated by ROs, their expected values are E(X1), E(X2), ..., E(X n ), respectively. If E(X1) = E(X2) = ··· = E(X n ) = µ, the expected value of the XOR of n sequence is given by7 E ′ = E(X1 ⊕ X2 ⊕ ··· X n ) =
1 1 + (−2)n−1(µ − )n . 2 2
(1)
The formula can be expressed as E′ =
1 1 − (1 − 2µ)n . 2 2
(2)
Since µ ∈ (0,1), |1 − 2µ| ∈ (0,1). |E ′| will exponentially go to 0.5. In other words, the probability of ones will be fast close to 0.5 as the number n of ROs goes highly. For the case of n = 4 and µ = 0.51, E ′ is 0.5-8 × 10−8. The accuracy of the probability of ones is adequate for our system. Finally, each of the random bit sequence is generated by 4 ROs. For an 8-bit number comprising 8 random bit sequences, the expected value from the output of the XOR gates is E1′, E2′, ..., E8′, respectively. For a random bit sequence, the expected value is nearly equal to the probability of ones we observe, the probability P11111111 of a 8-bit number
016116-3
Hu et al.
Rev. Sci. Instrum. 86, 016116 (2015)
TABLE I. The bias of pre-constraint and post-constraint. n
Pre-constraint
Post-constraint
3 5 7 9 11
2.9 × 10−4
2.6 × 10−4 4.8 × 10−4 3.2 × 10−4 9.5 × 10−5 5.8 × 10−4
5.0 × 10−4 7.5 × 10−4 1.9 × 10−4 8.2 × 10−4
“11111111” is given by P11111111 = E1′ · E2′ ··· E8′ .
(3)
Since = = ··· = ≈ 0.5, the P11111111 is about 1/28. Actually, the probability of any of 8-bit random number is about 1/28 because the probability of ones is approximately equal to the probability of zeros for every random bit sequence. The experiments are carried out based on a Virtex-6 FPGA. The random bit sequence generated by ROs is stored in an internal First In and First Out (FIFO) and subsequently transmitted to Personal Computer (PC) software through Ethernet interface. The random bit sequence is read out from the FIFO and stored in a file. A maximum size of the file is 1 MB. The sampling frequency in FPGA is 40 MHz. For the random bit constructed by ROs, the assumption is that the equal-length ring oscillator has the same oscillated frequency.8 Actually, the frequency is different from each other due to P&R (place and route) in Xilinx ISE software. Also, the delay of every LUT is not equal each other. However, these inverters can be constrained in a common region, decreasing the delay of the route. For the Virtex-6 family, there are four LUTs in every slice. In our design, every ring is constrained in the adjacent slices. The results of the ROs constructed by different numbers n of the inverters are shown in Table I, where the bias (|E ′ − 0.5|) for pre-constraint and post-constraint is listed. From the table, it is apparent that the bias decreases after the constraint. Considering the resource of the FPGA, the ROs constructed by 3 inverters are used for 8-bit random number. A histogram is plotted in Fig. 4. The size of 8-bit random number is 1 MB. In order to evaluate these random numbers, we define the deviation σ of the probability of 8-bit random numbers. For a set of 8-bit random numbers, the probabilities of every random number are P0, P1, ..., P255, respectively. The deviation σ is defined as 1 1 2 1 2 [(P0 − ) + (P1 − ) + ··· σ2 = 256 256 256 1 2 +(P255 − ) ]. (4) 256 After the calculations, σ is 2.4 × 10−4. The relative deviation 1 σ/( 256 ) is less than 6.2%. The random number is relatively E1′
E2′
E8′
FIG. 4. The histogram of 8-bit random number. The size of 8-bit random number is 1 MB. The result shows that the 8-bit random numbers are uniformly plotted in the histogram.
uniform in the histogram. We have carried out a test for 6 h. The signal source works normally, and the relative deviation is still around 6.2%. In summary, we have designed a simulation signal source for TGC detector, randomly outputting 256-channel simulation signals. The source is based on TRNG implemented in FPGA. An analysis of the random bit sequence is given in this note. Targeting the feature of TGC detector, the source can be configured as different modes. The experimental results show that the relative deviation of the random numbers is less than 6.2%. This work is supported by the National Natural Science Foundation of China under Grant No. 11375179. 1ATLAS Collaboration, “The ATLAS experiment at the CERN Large Hadron
Collider,” J. Inst. 3, S0800S (2008) 2J. Wang, J. Chapman, J. Zhu, T. Dai, and B. Zhou, TDS Design Specification,
2013. 3ATLAS Collaboration, New small wheel techincal design Report No. CERN-
LHCC-2013-006 or ATLAS-TDR-020, 1995. Brederlow, R. Prakash, C. Paulus, and R. Thewes, “A low-power true random number generator using random telegraph noise of single oxidetraps,” in IEEE International Solid-State Circuits Conference (IEEE, 2006), pp. 1666–1675. 5C. S. Petrie and J. A. Connelly, “A noise-based IC random number generator for applications in cryptography,” IEEE Trans. Circuits Syst. 47, 615 (2000). 6C. Tokunaga, D. Blaauw, and T. Mudge, “True random number generator with a metastability-based quality control,” J. Solid-State Circuits 43, 78 (2008). 7P. Z. Wieczorek and K. Golofit, “Dual-metastability time-competitive true random number generator,” IEEE Trans. Circuits Syst. 61, 134 (2014). 8B. Sunar, W. J. Martin, and D. R. Stinson, “A provable secure true random number generator with built-in tolerance to active attacks,” IEEE Trans. Comput. 56, 109 (2007). 9K. Wold and C. H. Tan, “Analysis and enhancement of random number generator in FPGA based on oscillator rings,” in Proceedings of International Conference on Reconfigurable Computing and FPGAs (IEEE Computer Society, 2008), p. 385 4R.
Review of Scientific Instruments is copyrighted by AIP Publishing LLC (AIP). Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. For more information, see http://publishing.aip.org/authors/rights-and-permissions.
