sensors Article

Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents Amad Ud Din, Seneke Chamith Chandrathna and Jong-Wook Lee * Department of Electronics Engineering, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea; [email protected] (A.U.D.); [email protected] (S.C.C.) * Correspondence: [email protected]; Tel.: +82-31-201-3730 Academic Editor: Vittorio M. N. Passaro Received: 20 February 2017; Accepted: 17 April 2017; Published: 19 April 2017

Abstract: Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 µm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power POUT of 564 µW and a rectifier output voltage VRECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a POUT of 288 µW and a VRECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier. Keywords: AC-DC converters; energy harvesting; piezoelectric; rectifier

1. Introduction There is increasing demand for autonomous sensing devices, deployed in various applications, such as medical, healthcare, and environmental monitoring [1]. To enable uninterrupted data gathering from a large population of sensing devices, e.g., the Internet of Things (IoT), a long lifetime is critical. Although there are continued innovations in battery capacity, battery lifetime is still finite. To extend the lifetime of sensing devices, energy can be acquired from ambient sources. There exist various sources from which energy can be extracted, including thermal, solar, vibrations, and wind. Among those energy sources, vibrations can provide a relatively large amount of energy through highly-efficient piezoelectric (PE) transducers. The equivalent electrical model of a PE transducer is represented as a sinusoidal current source IP (t) = IP sin(ω p t) in parallel with a capacitor Cp and a resistor Rp , where ω p = 2πfp is the angular frequency. In general, Rp is very large during low-frequency transducer operation, and the open-circuit voltage can be expressed as Vp = IP /ω p Cp . The output of a PE transducer is alternating current (AC) and, thus, needs conversion to direct current (DC). The commonly used AC-DC converters are full-bridge rectifiers (FBRs) and voltage doubler rectifiers (VDRs). Both FBR and VDR deliver a similar maximum output power when ideal diodes are used [2]. The operation of an FBR is well understood, which

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provides current for every half-cycle only after charging Cp to ±(VRECT + 2VD ). Here, VRECT is the 2VD). Here, VRECT is the rectified output voltage and VD is the diode voltage drop. The VDR provides rectified output voltage and VD is the diode voltage drop. The VDR provides current to the output only current to the output only during the positive half-cycle. In the negative half-cycle, a diode in during the positive half-cycle. In the negative half-cycle, a diode in parallel with the PE transducer parallel with the PE transducer provides a path to discharge Cp to the ground. During the positive provides a path to discharge Cp to the ground. During the positive half-cycle, IP only needs to charge half-cycle, IP only needs to charge Cp from −VD to (VRECT + VD) before current can flow into the output. Cp from −InVDthe to rectifier, (VRECT +a Vcommonly can flow intoisthe D ) before current used figure-of-merit theoutput. power transfer efficiency, which is In the rectifier, a commonly used figure-of-merit is thepower powerPtransfer which by is defined defined as the ratio of the output power POUT to the input IN, whichefficiency, can be delivered the as the ratio of the output power P to the input power P , which can be delivered by the PE PE transducer. Rectifying a low voltage from a PE transducerIN may induce significant power losses OUT transducer. a low voltage from a PE transducer may induce significant power losses due to due to Rectifying the diode voltage drop. An effective way to increase the efficiency of the rectifier is (1) reducing the diode’s voltage drop; and increasing the input of voltage by implementing the the the diode voltage drop. An effective way to (2) increase the efficiency the rectifier is (1) reducing bias-flip strategy. diode’s voltage drop; and (2) increasing the input voltage by implementing the bias-flip strategy. Figure 1 shows several reportedtechniques techniques for for improving improving the [2–6]. TheThe switch-only Figure 1 shows several reported theefficiency efficiency [2–6]. switch-only rectifier is introduced to reduce the power to charge Cp (not delivered to output) during the negative rectifier is introduced to reduce the power to charge Cp (not delivered to output) during the negative cycle of the VDR. In this approach, a switch M1 is shunted across the PE transducer, as shown in cycle of the VDR. In this approach, a switch M1 is shunted across the PE transducer, as shown in Figure 1a. The purpose of this switch is to discharge Cp instantaneously when IP crosses zero. Since Figure 1a. The purpose of this switch is to discharge Cp instantaneously when IP crosses zero. Since the switch is on at the zero crossing, the initial voltage to charge Cp starts from 0 rather than −VD. the switch is on at the zero crossing, the initial voltage to delivered charge Cp to starts 0 rather than −Vthe D . This This modification reduces the charge which is not the from output and increases modification extractedreduces power. the charge which is not delivered to the output and increases the extracted power.

(a)

(b)

(c) Figure 1. Schematics of the rectifiers for piezoelectric energy harvesting utilizing (a) switch-only; (b)

Figure 1. Schematics of the rectifiers for piezoelectric energy harvesting utilizing (a) switch-only; bias-flip using an inductor; and (c) bias-flip using two switches and diodes with an inductor. The (b) bias-flip using an inductor; and (c) bias-flip using two switches and diodes with an inductor. output load includes CL and RL. The output load includes CL and RL .

During the period when Cp is charged, however, there is still a large portion of IP that is not deliveredthe to the output. The C highlighted portion of IP, shown indicates the of portion of Iis P, not During period when however, thereinisFigure still a1a, large portion IP that p is charged, which is used to charge C p from 0 to ±(V RECT + 2V D ). To reduce the charge, the work in [2] introduces delivered to the output. The highlighted portion of IP , shown in Figure 1a, indicates the portion of IP , bias-flip 1b. +An inductor LP is the shunted across the PE whicha is used totechnique, charge Cpshown from 0in to Figure ±(VRECT 2VD ). To reduce charge, the work in transducer [2] introduces through the switches realized with M2 and M3. When IP crosses zero, the pulse signal VSW briefly a bias-flip technique, shown in Figure 1b. An inductor LP is shunted across the PE transducer through turns M2 and M3 on. At this time, the resonant loop formed by Cp and LP flips the voltage, VPN = VP − the switches realized with M2 and M3 . When IP crosses zero, the pulse signal VSW briefly turns M2 and VN across the transducer. Then, the charging starts from the flip-voltage Vf rather than from 0 V. M3 on. At this time, the resonant loop formed by Cp and LP flips the voltage, VPN = increases VP − VNthe across Since flipping reduces the amount needed to charge Cp from 0 to Vf, this technique the transducer. Then,However, the charging starts from theexists flip-voltage Vf rather than fromdrop 0 V. Since extracted power. we note that there power loss from the voltage of the flipping two reduces the amount needed to charge C from 0 to V , this technique increases the extracted power. p switches. In addition, the body diode of switchesf may be conducting for a large VPN (This However, we note that there exists power loss from the voltage drop of the two switches. In addition, observation also applies to M1 in Figure 1a. To reduce the voltage drop, current paths for positive and negative are split Sharing a single LP(This as shown in Figurealso 1c, this approach the body diode ofcycles switches may[4–6]. be conducting for a inductor large VPN observation applies to M1 in provides branches for the drop, bias-flip using paths two diodes and twoand shunt switches. The are transducer Figure 1a. To two reduce the voltage current for positive negative cycles split [4–6]. voltage is flipped alternatively throughin two paths.1c, Then, voltage drop by thetwo switch is reduced Sharing a single inductor LP as shown Figure thisthe approach provides branches for the from two to one, but with an additional diode voltage drop. The drawback of this approach is that bias-flip using two diodes and two shunt switches. The transducer voltage is flipped alternatively through two paths. Then, the voltage drop by the switch is reduced from two to one, but with an additional diode voltage drop. The drawback of this approach is that the two bias-flip voltages, Vf1

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and Vf2 for positive and negative cycles, respectively, are different, i.e., Vf1 6= Vf2 . This is because the impedance at VP and VN seen from the flipping path is different, and we observe asymmetric flipping in the waveform. The asymmetry results in fluctuation of the extracted power and increased output ripple. The diode voltage drop VD existing in the rectifier loop is the third reason for the low efficiency. The VD drop can be reduced by adding a bias voltage between the gate and drain terminal of a transistor [7]. To generate the bias voltages for a multi-stage rectifier, an extra bias distributor is required, which increases circuit complexity and the losses associated with it. In [3], an active diode, based on an op-amp with a pre-set DC offset, is used to reduce VD and the leakage current. Another method to reduce VD is by using a comparator-controlled switch [8]. This approach requires approximately one threshold voltage VTH plus two overdrive voltages to power up, limiting the input voltage for start-up to 1.2 V using a 0.35 µm CMOS process. Usually, the comparator is powered up from the output storage capacitor. If there is not enough voltage to power up, the comparator will not be readily activated. Herein, we propose two resonant rectifiers using low-voltage drop diode equivalents to overcome the limitations that exist in previous studies. We propose two diode equivalents, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE), which effectively reduces the VD of the rectifying stage. The diode equivalents are efficiently combined with a symmetric and low-loss resonant loop to realize the bias-flip technique. Harnessing MDDE and LDDE, two resonant rectifier integrated circuits (ICs) having self-startup capabilities are designed. To improve the efficiency under the self-power condition, the rectifier using MDDE includes synchronous bootstrap pulse generators (SBPGs). The SBPG provides boosted bias-flipping pulses that are synchronized with the frequency of the PE transducer. Two resonant rectifier ICs using both MDDE and LDDE, are fabricated in a 0.18 µm CMOS process. The rectifier using LDDE shows measured POUT of 564 µW under an external-powered condition with a corresponding efficiency of 68.1%. The rectifier using MDDE shows enhanced efficiency under the self-powered condition. It delivers a POUT of 288 µW with a corresponding efficiency of 78.4% and this result compares favorably with results from previous works. 2. Design For an energy harvester, the capability for self-startup is one of the critical functions and several techniques have been reported [9–12]. In [9], the authors introduce a cold startup technique using a transformer. For high voltage boosting, this approach needs a transformer with a large turn ratio, which can increase the overall size of the harvester. In [10], the authors propose a mechanical switch that provides an instant power jerk to kick start the harvester. In [11], the authors present a low-voltage startup technique using a VTH -tuned oscillator and a capacitor pass-on technique. Although a low startup voltage of 95 mV is achieved, the drawback is that this approach requires external programming of a body voltage after fabrication. In [12], a charge pump with a switched body-biasing technique is presented. Since the body terminal of a transistor is connected to a high voltage when it is turned off, the reverse leakage is effectively suppressed. In these previous works, except [11], the self-startup function, which is vital to autonomous operation, is not fully supported. In this work, we embed a simple, yet efficient, approach for self-startup into the two resonant rectifiers. 2.1. Resonant Rectifier Using LDDE Figure 2a shows the block diagram of the resonant rectifier IC using LDDE. The rectifier consists of a three-stage voltage multiplier (VM), an oscillator (OSC), a bootstrap pulse generator (BPG), a symmetric bias-flip circuit, and a full-bridge rectifying stage. The BPG provides the bootstrapped pulse signals V SW1 and V SW2 for the bias-flip circuit. The clock (CLK) signal for the BPG is generated by the OSC with a frequency that can be tuned using a ring oscillator. The supply voltage of the OSC is driven by the output V VM of the voltage multiplier shown in Figure 2b. For efficient operation, the

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VM uses Schottky diodes (DV1 –DV6 ) realized in a standard CMOS process, which shows a low VD of 160 mV at 1shows µA [13]. Since the160 VMmV and powered from transducer, the rectifier which a low VD of at OSC 1 μAare [13]. Since the VMthe andPE OSC are powered from theprovides PE transducer, the rectifier provides the self-startup function. the self-startup function.

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(b)

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Figure 2. (a) Block diagram of the proposed resonant rectifier IC using LDDE; (b) voltage multiplier;

Figure 2. (a) Block diagram of the proposed resonant rectifier IC using LDDE; (b) voltage multiplier; (c) bootstrap pulse generator; and (d) the symmetric bias-flip circuit and rectifying stage using (c) bootstrap pulse generator; and (d) the symmetric bias-flip circuit and rectifying stage using LDDEs. LDDEs.

Figure 2c shows schematicofofthe theBPG BPGwhich which generates generates V and VSW2 . The amplitudes of of Figure 2c shows thethe schematic VSW1 and VSW2 . The amplitudes SW1 these signals are increased to almost 2V VM , which provide the high overdrive voltage needed to fully these signals are increased to almost 2VVM , which provide the high overdrive voltage needed to fully onswitches the switches the bias-flip circuit, shown in Figure 2d. bias-flip The bias-flip circuit consists of turnturn on the in theinbias-flip circuit, shown in Figure 2d. The circuit consists of Schottky Schottky diodes (DG1, DG2), inductors (LG1, LG2), and transmission (T)-gate transistors (TG1, TG2). The diodes (DG1 , DG2 ), inductors (LG1 , LG2 ), and transmission (T)-gate transistors (TG1 , TG2 ). The T-gate is T-gate is used to reduce the on-resistance of the switch [14]. The size of NMOS and PMOS transistors used to reduce the on-resistance of the switch [14]. The size of NMOS and PMOS transistors in the in the T-gate are W/L = 1000 μm/0.2 μm and 2000 μm/0.18 μm, respectively, with values optimized T-gate are W/L = 1000 µm/0.2 µm and 2000 µm/0.18 µm, respectively, with values optimized by using by using a circuit simulator. When IP crosses zero, the bias-flip circuit changes the polarity of VPN a circuit When IP crosses zero,cycle the bias-flip changes polarity of VPN using usingsimulator. two separate paths. The positive uses the circuit path formed by Tthe G1, LG1, and DG1, while the two separate paths. The positive cycle uses the path formed by T , L , and D , while the path formed G1 G1 G1 path formed by TG2, LG2, and DG2 is used in the negative cycle. Inductors are bulky and expensive; by Tthe , L , and D is used in the negative cycle. Inductors are bulky and expensive; the bias-flip circuit G2 bias-flip G2 G2 shown in Figure 2d is improved to use only one inductor (see Section 2.2). circuit shown is improved to use one inductor Section Figurein3 Figure shows 2d a detailed schematic ofonly the rectifying stage(see using four 2.2). LDDEs. LDDE1,3 are NMOS-based LDDEs and the LDDE 2,4 are of PMOS-based LDDEs. When VP >four VN, LDDE 1 and LDDE1,3 4 are Figure 3 shows a detailed schematic the rectifying stage using LDDEs. LDDE conduct and form aand closed LDDE 4 consists of a main transmission transistor MP 1 and and control NMOS-based LDDEs the loop. LDDE are PMOS-based LDDEs. When V > V , LDDE LDDE 2,4 1 4 P N circuit (MP 2, MN1, and MN2). The LDDE1 consists of the main transistor MN3 and control circuit conduct and form a closed loop. LDDE4 consists of a main transmission transistor MP1 and control (MN4, MP3, and MP4). In a previous work [15], the control circuit for the LDDE is implemented circuit (MP2 , MN1 , and MN2 ). The LDDE1 consists of the main transistor MN3 and control circuit using discrete bipolar junction transistors (BJTs). In this work, we remove the base current of the BJT (MN4 , MP3 , and MP4 ). In a previous work [15], the control circuit for the LDDE is implemented using using metal-oxide field effect transistors (MOSFETs) realized in IC technology. A voltage polarity discrete bipolar junction transistors (BJTs). In this work, we remove the base current of the BJT using sense circuit is formed by the diodes DS1–DS4 and CS. The circuit detects the positive (VP > VN) and metal-oxide field effect transistors (MOSFETs) realized in IC technology. A voltage polarity sense negative (V P < VN) cycles using four terminal voltages, VR1, VR2, VC1, and VC2. Using the four voltages, circuit formed by the diodesthe DS1conduction –DS4 and Cof The main circuittransistor detects the positive (VP reverse > VN ) and negative S . the theissense circuit controls while blocking leakage (VP < VN ) cycles using four terminal voltages, VR1 , Vthe VC1 , and Vof Using the four current. The voltage at nodes VC1 and VC2 control 1 and LDDEvoltages, 4 in the the R2 , conduction C2 .LDDE sense circuitcycle controls the conduction main transistor while blocking reverse leakage current. positive (LDDE 2 and LDDE3 in of thethe negative cycle), respectively. The voltage at nodes VR1 and V R2 blocks reverse conduction of LDDE 4 and LDDE 1 in the negative cycle (LDDE 3 and LDDE 2 in the The voltage at nodes VC1 and VC2 control the conduction of LDDE1 and LDDE4 in the positive cycle positive cycle), respectively. (LDDE 2 and LDDE3 in the negative cycle), respectively. The voltage at nodes VR1 and VR2 blocks The operation the LDDE is described using four states, shown in Figure 3b. When IP crosses reverse conduction of of LDDE 4 and LDDE1 in the negative cycle (LDDE3 and LDDE2 in the positive zero from negative to positive, DS2 and DS4 are forward-biased forming the conducting path DS2 – CS cycle), respectively. – DS4. The terminal voltages detected by the sense circuit satisfy the condition (VC1 = VP) > (VR2 = VP −

The operation of the LDDE is described using four states, shown in Figure 3b. When IP crosses zero from negative to positive, DS2 and DS4 are forward-biased forming the conducting path DS2 – CS – DS4 . The terminal voltages detected by the sense circuit satisfy the condition (VC1 = VP ) > (VR2 = VP − VD1 )

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> (VR1 = VN + VD1 ) > (VC2 = VN ), where V D1 is the forward voltage drop of a diode in the sense circuit. We consider four operation states for LDDE4 as follows. (1)

(2)

(3)

(4)

State-1: In17, the Sensors 2017, 901positive cycle when V P > V N , we have the condition of (VP = VC1 ) > (V 5 of C215= VN ). Terminal VC2 is connected to the negative terminal VN of the PE transducer through MN2 . Then VD1) turns > (VR1 on = VNand + Vsubsequently D1) > (VC2 = VN), where VD1 is the forward voltage drop of a diode in the sense MP turns on MN2 , as well. The CSG of MP1 is charged by V PN . 2 circuit. We consider four operation states for LDDE4 as follows. State-2: The source and gate terminals of MP1 are approximately VP and VN + V DS,MN2 , (1) State-1: InHere, the positive cycle when VP > VN, wevoltage have theofcondition of (V P = VC1) > (VC2 = VN). respectively. V DS,MN2 is the drain-source MN2 . The voltage at node VP keeps Terminal V C2 is connected to the negative terminal VN of the PE transducer through MN2. Then increasing. Then, MP1 begins conducting when VSG > |VTH |. The voltage across CSG of MP1 MP2 turns on and subsequently turns on MN2, as well. The CSG of MP1 is charged by VPN. keeps increasing and MP1 enters the triode from the saturation mode. Using the rectifier operation, (2) State-2: The source and gate terminals of MP1 are approximately VP and VN + VDS,MN2, V RECTrespectively. increases. Here, Then,Vthe condition (VPN − V DS,MN2 |) > (VP − V MP1 to DS,MN2 is the drain-source voltage − of |V MNTH 2. The voltage atRECT node) allows VP keeps enterincreasing. the triodeThen, mode, which can be written as V > (V + |V | + V ). RECT N voltage TH across DS,MN2 MP1 begins conducting when VSG > |VTH|. The CSG of MP1 keeps State-3: When and the MP VSD1 enters of MPthe decreases by increasing V , it turns MP When MP2 is increasing triode from the saturation mode. Using the rectifier 1 RECT 2 off.operation, RECT Then, the condition PN − VDS,MN2 − |VTH > (V P − VRECT ) allows MP 1MP to enter the off, CVSG ofincreases. MP1 stops charging and it(Vmaintains the V|) of MP . This allows 1 1 to continue SG triode mode, which can be written as V RECT > (VN + |VTH| + VDS,MN2). conducting in the triode mode. When MP2 is off, the gate of MN2 has no path to conduct and, (3) State-3: When the VSD of MP1 decreases by increasing VRECT, it turns MP2 off. When MP2 is off, therefore, MN2 is kept on. This state is different from the BJT version of the LDDE [15]; the base CSG of MP1 stops charging and it maintains the VSG of MP1. This allows MP1 to continue current of a BJT provides a path to discharge while the MOSFET MN2 is kept on. conducting in the triode mode. When MP2 is off, the gate of MN2 has no path to conduct and, State-4: When MN ip changes direction (V < VN ), thefrom current direction sense circuit reversed. therefore, 2 is kept on. This statePis different the BJT versionin of the the LDDE [15]; theisbase Then,current the terminal voltagesa path detected by thewhile sense satisfy the condition (VC2 = VN ) > of a BJT provides to discharge thecircuit MOSFET MN2 is kept on. (4)R1 = State-4: direction P p changes (VR2 = V )> = Vcurrent condition turns oncircuit MN1 .isBy discharging P + VD1(V P ). Thisdirection Then, the terminal voltages detected by the sense circuit satisfy the condition (V C2 = VN ) > (VR1 = the CGD of MP , MN subsequently turns off MP to prevent reverse leakage. Since V 1 1 1 C2 is positive V N − VD1) > (VR2 = VP + VD1) > (VC1 = VP). This condition turns on MN1. By discharging the CGD of and increasing, MN2 is turned off, which prevents the discharging of VRECT through MN1 .

MP1, MN1 subsequently turns off MP1 to prevent reverse leakage. Since VC2 is positive and increasing, turned off, which prevents the discharging VRECT through MN In the case of V MN < V2 is, LDDE and LDDE conduct. During theofzero-crossing of I 1. from positive to P

N

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3

negative, DInS1the and DS3ofare forming the conduction DS3 –CS –D . Thepositive operation of case VP VN(V ), MDDE and MDDE close the loop,the as shown Figure in 5a. leakage In the positive P > VN),2 MDDE 2 and3 MDDE 3 close loop, asin shown The diode D is forward biased, which turns on N . At this time, the gate of TP is connected to Figure 5a. The 2 diode D2 is forward biased, which 2turns on N2. At this time, the 2 gate of TP2 is VN through which turns on TPturns VN2. is negative, it also turns onturns P3 and TheDV of connected to N VN2 ,through N2, which on TP Since VN is negative, it also onD P33 .and 3.SG The 2 . Since is determined by the voltage the gate VDS,N2 source (VRECT ). With the condition VTP SG 2of TP2 is determined by the at voltage at (V the gate (VN) +and VDS,N2 ) and source (VRECT ). With the N + (VRECT − (V VNRECT − −VDS,N2 )> |V)TH |, TP on. The TN is determined by the at the condition VN − V DS,N2 > |V TH|, TPturned 2 is turned on. V The VGS of3 TN 3 is determined byvoltage the voltage 2 is GS of gate VPSD,P3 ) and source (VRECT arethe thesource-drain source-drainvoltage voltage −V at the(V gate − VSD,P3 ) and source (VRECT − D,RL VD,RL),),where whereVVSD,P3 SD,P3 and VD,RL P −(V D,RLare − − of P and the voltage drop across R , respectively. With the condition (V V V + VD,RL of P33 and the across RLL, respectively. With the condition (V SD,P3 − VRECT + VD,RL ) >) P P − VSD,P3 RECT between VN and , closing the loop. V>THV, TH the, the TNTN 3 connects between VN and VRECTV,RECT closing the loop. 3 connects

(a)

(b)

Figure Figure 5.5. Schematic Schematicofofthe therectifier rectifierloop loopusing usingMDDE MDDEand andoperation operationduring during(a) (a)positive positiveand and(b) (b) negative cycles. negative cycles. Table 1. Values of the delay line depending on RL, IP, and fP. Next, we find the condition for TP2 and TN3 to operate in triode mode. In TP2 , we observe (Hz) 300 that thefpsource-drain voltage is200 VRECT − VP and the source-gate voltage is VRECT 400 − (VN + V DS,N2 ). Therefore, the condition operation of TP2 . 20 For TN3 , RL (KΩ) 100VPN >> 50(|VTH | 20+ V DS,N2 100) allows 50 deep-triode 20 100 50 we observe that the drain-source voltage VN − (V RDLis(MΩ)/C DL RECT (nF) − VD,RL ) and the gate-source voltage is (VP − V SD,P3 ) 200 − (VRECT8/1 − VD,RL8/1 ). Then, the condition VPN >> (V 10/1 8/1 8/1 8/1TH + V8/1 8/1 deep-triode 8/1 SD,P3 ) allows mode operation for TN . In the negative cycle (V < V ), D and D are reverse biased, and the voltage 300 10/1 14/1 12/1 4/1.5 5/0.5 5/0.5 5/0.5 2 2 3 P8/1 N 4/1.5 IP (μA) at the source terminal of N2 is V P3 , it is8/1 VP < 0). Therefore, N2 and P off and 400 10/1 14/1 14/1 8/1 5/1 both 8/0.5 8/0.5 3/1.2 3 are kept N > 0 (for the reverse leakage and TN is blocked. The operation of MDDE and MDDE 600 through 16/1 TP16/1 14/1 8/1.5 8/1.5 7/1.5 8/1 8/1 5/1.2 2 3 1 4 in the negative cycle (VP < VN ) can be similarly described, as shown in Figure 5b. Next, we find the condition for TP2 and TN3 to operate in triode mode. In TP2, we observe that the source-drain voltage is VRECT − VP and the source-gate voltage is VRECT − (VN + VDS,N2). Therefore, the condition VPN >> (|VTH| + VDS,N2) allows deep-triode operation of TP2. For TN3, we observe that the drain-source voltage is VN − (VRECT − VD,RL) and the gate-source voltage is (VP − VSD,P3) − (VRECT − VD,RL). Then, the condition VPN >> (VTH + VSD,P3) allows deep-triode mode operation for TN2. In the

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Figure 6 901 shows the comparison of VD of the LDDE and MDDE as a function of IP . The two Sensors 2017, 17, 8 ofR15 L values and the size of the main transistor are chosen to match the result in [15]. Since the control circuit equivalents increases thesmall smallIPIPvalues, range from 20 to show 40 μA.that When IPDincreases aboveequivalents 60 μA, VD does not fully turn on in with the results the V of both diode with . The ILDDE has a narrow in the IP range from 40 V μA. In the case of increases in theIPsmall from 20 to 40window µA. When IP increases above3060toµA, with P range D increases the V D is abelow 50 mV in the I P range from 30 to 60 μA. In order to investigate the IMDDE, . The LDDE has narrow window in the I range 30 to 40 µA. In the case of MDDE, the V P P D is performance for different PE transducer parameters, Figure 6b shows the comparison of V D of the below 50 mV in the IP range from 30 to 60 µA. In order to investigate the performance for different LDDE and MDDE for the different periphery. For a PE transducer IP = 600 μA, the VDfor is 230 PE transducer parameters, Figure 6b shows the comparison of VD having of the LDDE and MDDE the mV and 360 mV in case of MDDE and LDDE having the same size, respectively. The results show different periphery. For a PE transducer having IP = 600 µA, the VD is 230 mV and 360 mV in case that the MDDE showshaving an overall smaller VDrespectively. than that of The the LDDE broad of Ishows P. The of MDDE and LDDE the same size, resultsover showa that therange MDDE LDDE use smaller three extra control theover on-resistance of the conducting transistor. In an overall V D transistors than that oftothe LDDE a broad range of main IP . The LDDE use three extra the case of the MDDE, the control is achieved using a transistor and a diode, which makes it simple, transistors to control the on-resistance of the main conducting transistor. In the case of the MDDE, withcontrol a low is loss. the achieved using a transistor and a diode, which makes it simple, with a low loss. 700

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RL = 80 k (LDDE)

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RL = 113 k (MDDE)

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W/L=1.5mm/3.5m (MDDE) W/L= 200m/1m (MDDE) W/L= 1.5mm/3.5m (LDDE) W/L= 200m/1m (LDDE)

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(b)

Figure 6. of of thethe diode voltage drops as a as function of IP for loads; and (b) Figure 6. Comparison Comparison diode voltage drops a function of (a) IP different for (a) different loads; periphery (W/L). (W/L). and (b) periphery

2.3. Loss Calculation 2.3. Loss Calculation Figure 7 shows the key waveforms of the resonant rectifier. When the PE element starts Figure 7 shows the key waveforms of the resonant rectifier. When the PE element starts providing providing IP, the rectifier enters a startup state. In this state, the BPG starts generating VSW1 and VSW2, IP , the rectifier enters a startup state. In this state, the BPG starts generating VSW1 and VSW2 , which which have amplitudes that increase with VPN. A steady-state is assumed after t1. Just before time t1, have amplitudes that increase with VPN . A steady-state is assumed after t1 . Just before time t1 , Cp Cp is pre-recharged to −(VRECT + 2VD). At time t1, IP changes direction and the bias-flip operation is pre-recharged to −(VRECT + 2VD ). At time t1 , IP changes direction and the bias-flip operation allows the charging of Cp from Vf to (VRECT + 2VD) until t2. During this period, the output current Io allows the charging of Cp from Vf to (VRECT + 2VD ) until t2 . During this period, the output current starts flowing to the load. In the negative cycle, Cp is discharged from −Vf to −(VRECT + 2VD). The Io starts flowing to the load. In the negative cycle, Cp is discharged from −Vf to −(VRECT + 2VD ). effectiveness of bias-flip is usually expressed using a flipping efficiency ηf, defined as: The effectiveness of bias-flip is usually expressed using a flipping efficiency η f , defined as:

V V

RECT  f Vf f + V RECT

ηf =

as:

2VRECT

(1) (1)

2VRECT The amount of charge QCp lost due to charging Cp during time interval [t1, t2] can be expressed The amount of charge QCp lost due to charging Cp during time interval [t1 , t2 ] can be expressed as: QCp = [V + 2V − Vf ]fC]C [VRECT − (2 VRECT (2η QRECT [V  2+ VD2V VDRECT  f 1)] Cfp − 1)]C p p p= RECT Cp [VRECT D2VD V

(2) (2)

inthe thetime timeinterval interval[t[t tπ].]. Since Since VVPN PN varies during consider the the charge chargelost lostacross acrossRRp pin Next, we consider 1 ,1,tπ time interval, interval, we weconsider considertwo twocases casesofofcharge chargelosses, losses,QQ Rp1during during [t 1,t t] 2]and and Q Rp2 during [t22, ttππ], the time [t , Q 1 2 Rp1 Rp2 during [t given by: Z t2 Z V (t) t tπ VPN (t) t ) dt + V PN ( t ) Q Rp = Q Rp1 + Q Rp2 = t 2 V PN (PN dt (3) Q Rp  Q Rp1  Q Rp 2   t1 dt R pdt  t 2 t2 Rp (3) t1 Rp Rp During the time interval [t1, t2], Vf is inverted via a bias-flip. In this period, VPN(t) can be obtained by integrating IP(t) as:

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Sensors 2017, 17,time 901 During the

of 15 interval [t1 , t2 ], Vf is inverted via a bias-flip. In this period, VPN (t) can be9obtained by integrating IP (t) as: Ip 1 t Z VPN (4) 1 (t ) t C t1 I p sint dt V f (t1 )  C I p(cost1  cost ) V f (t1 ) I p psin ωt dt − Vf (t1 ) = p (cos ωt1 − cos ωt) − Vf (t1 ) VPN (t) = (4) C p t1 ωC p Applying the boundary conditions Vf VRECT (2 f 1) and ωt1  0, Equation (4) can be Applying the boundary conditions Vf = VRECT (2η f − 1) and ωt1 ∼ = 0, Equation (4) can be expressed as: expressed as: V (t )  V (1 cos t )  V (2 1) (5) VPN (t)PN= Vp (1p − cos ωt) − RECT VRECT (f2η f − 1) (5)

where VP = IP/(ωpCp) is the open-circuit voltage. Using Equation (5), QRp1 is obtained as:

where VP = IP /(ω p Cp ) is the open-circuit voltage. Using Equation (5), QRp1 is obtained as: Vp t 2 V p (1 cos t )  VRECT (2 f 1) V QRpR1 t2 dt V  Vp (1−cos ωt) − V (t 2  sin t 2 )  RECT (2 f 1)t 2 (6) (2η f −1) RECT p t1 ∼  R(pωt2 − sin ωt2 ) − Rp  RVpRECT (2η f − 1)ωt2 Q Rp1 = dt = t1

Rp

ωR p

ωR p

(6)

Figure 7. Key waveforms of the resonant rectifier.

Figure 7. Key waveforms of the resonant rectifier.

To find QRp2 during the time interval [t2, tπ], we need the value of ωt2 and, thus, use the

To find Q following relationship: Rp2 during the time interval [t2 , tπ ], we need the value of ωt2 and, thus, use the following relationship: dVp dV p dVp (7) I sint  C dVp  C p I p sinp ωt = C pp dt = ωC (7) pt d  dt dωt Integrating Equation (7) over interval t2] when bias-flipping is performed, Integrating Equation (7) over the the timetime interval [t1 , [t t21], when bias-flipping is performed, wewe obtain: obtain:

Vp (− ωt2+ V cos (  cos t cos cosωt 1t)) =  VV(pt(t)2) V− (V t p)(t1 ) p

2

1

p

2

p

1

(8)

(8)

values ofp V p can obtained from waveform,which which are areVpV(pt(1t1))  = The The values of V can be be obtained from thethe waveform, Vf and V f and Vp (t2V) (= ( V + 2V ) . Then, Equation (8) can be written as: D Equation (8) can be written as: t )  (VRECT  2V ) . Then, p

2

RECT

D

2V RECT  − +V 2η f 2VD2V V 2RECT 1 1 −1 V pV− DRECT p  2VRECT f  cos ) t2 = t 2 cos ( 1 ( ) ω  V pVp

(9)

(9)

obtained as: as: Using Equation QRp2isisobtained Using Equation (9),(9), QRp2

(V RECT  2V D ) Q Rp 2  (VRECTR+ 2VD()t  t 2 ) p Q Rp2 = ( t π − t2 ) where t   /  . where tπ = π/ω.

Rp

(10)

(10)

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The total charge produced by the PE transducer in every cycle is given by: The charge produced produced by by the the PE PE transducer transducer in in every every cycle cycle is is given given by: by: The total total charge Q total  2 I p /   2 C pV p (11) Q total  2 I p /   2 C pV p (11) Qtotal = 2I p /ω = 2C p Vp (11) The theoretical extracted power POUT,calc from the PE transducer for every cycle is obtained by The theoretical extracted power POUT,calc from the PE transducer for every cycle is obtained by taking the available extracted charge Equation (11) minus the various loss terms given by Equations (2), by (6) The power P(11) from PE transducer forgiven everyby cycle is obtained OUT,calc taking thetheoretical available charge Equation minus thethe various loss terms Equations (2), (6) and (10): taking the available charge Equation (11) minus the various loss terms given by Equations (2), (6) and (10): and (10): POUT,calc  2 f pV RECT (Qtotal  QCp  Q Rp1  Q Rp 2 ) POUT,calc  2 f pV RECT (Qtotal  QCp  Q Rp1  Q Rp 2 ) Vp V RECT  2 f pV RECT {[2V p C p  [V RECT  2V D  V RECT (2 f  1)]C p  [ V p ( t 2  sin  t 2 )  V RECT POUT,calc = (Q − Q − Q − Q )  22ffppVVRECT {[2 Vtotal C  [ V  2 V  V (2  1)] C  [ ( t  sin t )     Rp2 Rp1 RECT Cp R R (12) p p RECT D RECT f p 2  R Vpp p 2  R pp VRECT (12) V RECT + 2V2V D ( ωt − sin ωt ) − = 2 f p VRECT {[f2V − V ( 2η f − 1)]C p − [ ωR (12) pC 2 2 D RECT (2  1) ] [[V ( t  t )]} pt 2− VRECT  2 V ωR p p RECT D (2 f  1)VtRECT (t  t 22 )]} +2VD R p 2 ][ (2η f − 1)ωt2 ] − [ (Rtπp − t2 )]} Rp 3. 3. Measured Results 3. Measured Results The proposed proposed rectifiers rectifiers are are fabricated fabricated in in a one-poly six-metal 0.18 µm μm CMOS process with a top The proposed rectifiers are fabricated in a one-poly six-metal 0.18 μm CMOS process with a top 2 µm μm thick thickmetal metaloption. option.Figure Figure88shows showsthe thechip chipmicrophotographs. microphotographs. The The size size of of the the rectifiers rectifiers using using 2 μm thick metal option. Figure 8 shows the chip microphotographs. The size of the rectifiers using LDDE 0.46 mm, mm, respectively. respectively. Figure 9 shows the LDDE and and MDDE MDDE are are0.26 0.26mm mm× × 0.19 mm and 0.51 mm × × 0.46 LDDE and MDDE are 0.26 mm × 0.19 mm and 0.51 mm × 0.46 mm, respectively. Figure 9 shows the experimental experimental setup setup to to characterize characterize the the rectifier rectifier using usingthe thePE PEtransducer. transducer. experimental setup to characterize the rectifier using the PE transducer.

(a) (a)

(b) (b)

Figure 8. 8. Chip micrograph of the the resonant resonant rectifier rectifier ICs using using (a) LDDE; LDDE; and (b) (b) MDDE. Figure Chip micrograph micrograph of of Figure 8. Chip the resonant rectifier ICs ICs using (a) (a) LDDE; and and (b) MDDE. MDDE.

Vibrating motor Vibrating motor

PE transducer PE transducer SUS plate SUS plate Piezo ceramic Piezo ceramic Ag electrode Ag electrode

Figure 9. Experimental setup. Figure 9. Experimental Figure 9. Experimental setup. setup.

The bimorph of the transducer has a thickness, a length and a width of 0.33, 75, and 20 mm, The bimorph of the transducer has a thickness, a length and a width of 0.33, 75, and 20 mm, respectively [16]. Each consistshas of a thickness, stainless steel (SUS)and plate, a piezo ceramic, and20anmm, Ag The bimorph of thelayer transducer a length a width of 0.33, 75, and respectively [16]. Each layer consists of a stainless steel (SUS) plate, a piezo ceramic, and an Ag electrode. The PE Each transducer mounted a vibrating mechanical [17]. respectively [16]. layer is consists of aon stainless steelmotor (SUS)for plate, a piezo excitement ceramic, and an The Ag electrode. The PE transducer is mounted on a vibrating motor for mechanical excitement [17]. The transducer is excited using 200 Hz with an acceleration of 1.8motor g. Under condition, the theoretical electrode. The PE transducer is mounted on a vibrating for this mechanical excitement [17]. transducer is excited using 200 Hz with an acceleration of 1.8 g. Under this condition, the theoretical optimum loading of the PEHz transducer 7.2 kΩ. Two both sides of the the The transducer is resistance excited using 200 with an is acceleration ofwires 1.8 g.attached Under to this condition, optimum loading resistance of the PE transducer is 7.2 kΩ. Two wires attached to both sides of the transducer optimum are interfaced with a test board containing the rectifiers. Table showsattached the parameters theoretical loading resistance of the PE transducer is 7.2 kΩ. Two2wires to both transducer are interfaced with a test board containing the rectifiers. Table 2 shows the parameters used for the transducer experiment.are The value of with the inductor for bias-flip is selected considering trade-off sides of the interfaced a test board containing the rectifiers. Table the 2 shows the used for the experiment. The value of the inductor for bias-flip is selected considering the trade-off between size and the Q-factor. The maximum current available from the transducer is 600 μA, between size and the Q-factor. The maximum current available from the transducer is 600 μA,

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parameters used Sensors 2017, 17, 901 for the experiment. The value of the inductor for bias-flip is selected considering 11 of 15 the trade-off between size and the Q-factor. The maximum current available from the transducer is which to Vp =to4.34 at 200 The The equivalent circuit of of a aPE 600 µA,corresponds which corresponds Vp =V4.34 V at Hz. 200 Hz. equivalent circuit PEtransducer transducer can can be represented as a mechanical spring-mass coupled to an electrical circuit. The current in the primary sidecorresponds corresponds to proof relative velocity, is determined by such mechanical side to proof massmass relative velocity, which iswhich determined by such parameters parameters as PE material, dimension, and acceleration. By the electromechanical coupling factor, as PE material, dimension, and acceleration. By the electromechanical coupling factor, which describes which describes the effectiveness the mechanical conversion to from mechanical to electrical energies, the the effectiveness of the conversion of from electrical energies, the maximum current maximum current is determined. is determined. Table 2. Table 2. Parameters for the experiment. experiment.

Parameters Parameters fp fp C Cpp RRpp LLG1G1,,LLG2 G3 G2,,LL G3 CL CL RL RL

Value Value 200 Hz 200 Hz 110 nFnF 110 1 MΩ 1 MΩ 1000 µH 1000 μH 1 µF 1 μF 10–200 KΩ 10–200 KΩ

Figure Figure 10 10 shows shows the the measured measured result result of of the the rectifier rectifier using using LDDE. LDDE. ItIt shows shows the the input input voltage voltageVVPN PN,, bootstrap pulse signals V and V , and the output V . The transient during self-startup bootstrap pulse signals VSW1 SW1 and VSW2 SW2, and the output VRECT RECT. The transient during self-startup is is shown generating VSW1 PN shown in in the theinset. inset.When WhenVV PNis isincreased, increased,the theBPG BPGstarts starts generating VSW1and andVSW2 VSW2. .Then, Then,VVRECT RECT starts starts increasing increasing and and the the steady-state steady-state condition condition is is reached reached at atabout about20 20s.s.After Afterthis thistime, time,VVSW1 SW1 and and V reach a value about twice that of the multiplier output and fully turn on the bias-flip circuit. VSW2 SW2 reach a value about twice that of the multiplier output and fully turn on the bias-flip circuit.

Figure rectifier using using LDDE. LDDE. Figure 10. 10. Measured Measured waveforms waveforms of of the the resonant resonant rectifier

Figure 11 shows the measured and calculated POUT and efficiency versus VRECT. We characterize Figure 11 shows the measured and calculated POUT and efficiency versus VRECT . We characterize the rectifier under external and self-power conditions. When it is externally powered, the VM the rectifier under external and self-power conditions. When it is externally powered, the VM provides provides power only to the BPG and the internal oscillator is turned off. The CLK frequency is power only to the BPG and the is turned off. The the CLK frequency is generates supplied supplied externally to match the internal fp of the oscillator PE transducer. By receiving CLK, the BPG externally to match the f of the PE transducer. By receiving the CLK, the BPG generates V and p measured with IP = 600 μA. Since VRECT depends on RL, it is variedSW1 VSW1 and VSW2. The VRECT is from 10 V The searching V RECT is measured with IPvalue. = 600When µA. Since RECT depends L , it is varied toSW2 200. kΩ, for an optimum VRECTVreaches 3.36 V, on theRmeasured peakfrom POUT 10 of to searchingwith for an value. When VRECT reaches 3.36 V, the measured peak POUT 564200 μWkΩ, is achieved an optimum RL of 20 kΩ. The P OUT,calc obtained using Equation (12) is 626 μW, which of 564 µWthat is achieved with an RL of by 20 kΩ. The POUT,calc using is 626 µW, indicates the power consumed the control circuitobtained is 62 μW. The Equation maximum(12) input power which indicates that the power consumed by the control circuit is 62 µW. The maximum input power which can be delivered by the PE transducer is obtained as PIN = 2 Cpfp(Vp)22 = 828 μW. Using the which can for be power delivered by the PE transducer isINobtained as 68.1%. PIN = 2Using Cp fp (Vthe = 828 µW.VUsing the p ) measured definition transfer efficiency = POUT/P , we obtain f of 1.53 V definition for(1), power transfer efficiency , we obtainUnder 68.1%.the Using the Vf of 1.53 V OUT /Pis INachieved. in Equation a flipping efficiency ηf =ofP72.8% same PEmeasured input condition and in Equation (1), a flipping efficiency η of 72.8% is achieved. Under the same PE input condition and with VD = 0.7 V, the maximum powerf that can be obtained using the FBR [2] is 190 μW. The results with 0.7 rectifier V, the maximum power that can betimes obtained using FBR [2]ofisthe 190FBR. µW. The results D = the showVthat using LDDE delivers three higher POUTthe than that show that the rectifier using LDDE delivers three times higher POUT than that of the FBR.

Sensors 2017, 17, 901 Sensors 2017, 17, 901 Sensors 2017, 17, 901 100 100 80 80

Efficiency (%) Efficiency (%)

Measured (external) Measured (self-power) Measured (external) Calculated Measured (self-power) Calculated

P OUT ( W) P OUT ( W)

700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0

12 of 15 12 of 15 12 of 15 Measured (external) Measured (self-power) Measured (external) Calculated Measured (self-power) Calculated

60

60 40

40

IP= 600A IP= 600A 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VRECT (V) VRECT (V)

(a) (a)

20

20 0 0

IP= 600A IP= 600A 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VRECT (V) VRECT (V)

(b) (b)

Figure11. 11.Performance Performanceofofthe therectifier rectifier using LDDE: output power versus output voltage; Figure using LDDE: (a)(a) output power versus output voltage; and and (b) Figure 11. Performance of the versus rectifieroutput using voltage. LDDE: (a) output power versus output voltage; and (b) power transfer efficiency power transfer efficiency versus output voltage. (b) power transfer efficiency versus output voltage.

Under the self-power condition, a resistive voltage divider is placed at the output of the VM. Underthe theself-power self-power condition, a resistive voltage divider placed at output the VM. Under a resistive voltage divider is is placed thethe output of of the VM. The role of the divider iscondition, controlling the supply voltage of OSC, whichatdetermines the CLK. The Therole role of the the divider isiscontrolling the supply voltage of OSC, which determines the CLK. CLK. The voltage The divider controlling the supply voltage of OSC, which The voltageofdivider is tuned so that the CLK frequency is closely matched todetermines the fp of PE the transducer. The dividerdivider is tuned so thatso the CLK frequency is closely matched to the to fp of PE transducer. The results voltage is tuned that the CLK frequency is closely matched the f p of PE transducer. The results show a POUT of 261 μW with a VRECT of 2.8 V. show show a POUT ofOUT 261 with a VRECT of 2.8 results a 12 P ofµW 261the μW with a VRECT of V. 2.8 V.of the rectifier using MDDE. The result shows the Figure shows measured waveform Figure12 12shows shows the the measured waveform ofofthe rectifier using MDDE. TheThe result shows the initial Figure measured waveform the rectifier using MDDE. result shows the initial transient waveform during self-startup. When VPN starts increasing, the SBPG generates transient waveform during self-startup. When V starts increasing, the SBPG generates pulses for PN initial transient during When VPNisstarts increasing, generates pulses for the waveform bias-flip. After the self-startup. steady-state condition reached at about the 2 s, SBPG VPN flips abruptly. the bias-flip. After theAfter steady-state condition is reached at about 2ats,about V flips Figure 13 pulses for13the bias-flip. theand steady-state reached 2 s,for Vabruptly. PN flips abruptly. Figure shows the measured calculatedcondition POUT andisefficiency versusPN VRECT two cases: IP = 600 shows the measured and calculated P and efficiency versus V for two cases: I = 600 and OUT RECT P Figure 13 shows theThe measured calculated POUT efficiency versus cases: PµA = 600 μA and 400 μA. rectifierand is characterized byand varying RL from 10 toVRECT 200 for kΩ two to find an Ioptimum 400 µA. The rectifier is characterized by varying R from 10 to 200 kΩ to find an optimum condition. L μAcondition. and 400 μA. The is acharacterized kΩextracted to find anwith optimum Using IP rectifier = 400 μA, peak POUT of by 288varying μW andRaL from VRECT 10 of to 2.4200 V are an RL of Using IP Using = 400 µA, peak PaOUT of P 288 andμW a Vand 2.4 of V are extracted with an RL an of 20 kΩ, RECTa of condition. I P = a 400 μA, peak OUTµW of 288 V RECT 2.4 V are extracted with 20 kΩ, which corresponds to an efficiency of 78.4%. The POUT,calc obtained using Equation (12)RLisof 386 corresponds to an to efficiency of 78.4%. The PThe ,calc using Equation (12)(12) is 386 µW, OUTP 20which kΩ, which corresponds an efficiency of 78.4%. OUT,obtained calc obtained using Equation is 386 μW, which indicates that the additional loss and control power is 98 μW. Since POUT depends on the which indicates that thethe additional loss and power isis98 Since dependson onthe the μW, indicates that additional loss andcontrol control power 98µW. μW. Since PPOUT OUT depends PEwhich transducer characteristics and the mechanical vibration [18,19], it is difficult to directly compare PEtransducer transducercharacteristics characteristics and themechanical mechanical vibration [18,19], isdifficult difficulttotodirectly directly compare PE the vibration [18,19], it itisbe POUT performance (See Tableand 3). However, the conventional FBR can used as a commoncompare reference. P performance (See Table 3). However, the conventional FBR can be used as a common reference. OUT POUT performance (See Table 3). However, the conventional FBR can be used as a common reference. Under the same conditions, the maximum power that can be obtained using the FBR is 48.8 μW. Underthe thesame sameconditions, conditions,the the maximum maximum power power that be using the FBR is is 48.8 µW. The Under that can can 5.9 beobtained obtained using the FBR 48.8 μW. The results show that the rectifier using MDDE delivers times higher POUT than that of the FBR. results show that the rectifier using MDDE delivers 5.9 times higher P than that of the FBR. Using OUT The results thata the using MDDE delivers times higher POUT than that of the FBR. Using IP =show 600 μA, POUTrectifier of 441 μW is extracted with a V5.9 RECT of 2.1 V using an RL of 10 kΩ. The result IP = 600 aμA, POUT of 441 µWμW is extracted with aV 2.1 V an R of 10 10kΩ. kΩ.The Theresult result RECT Using I P = µA, 600 a P OUT of 441 is extracted with a V RECTof of V using using RLL This of shows that efficiency is reduced when IP is increased from2.1 400 to 600an μA. is related to the showsthat thatefficiency efficiency is is reduced when IPIPisisincreased from 400400 to 600 µA. This is related to the narrow shows reduced increased to 600 narrow working window wherewhen VD is increased with IPfrom (See Figure 6). μA. This is related to the working window where where V D is increased with IPwith (SeeIPFigure 6). 6). narrow working window VD is increased (See Figure

Figure 12. Measured waveforms of the resonant rectifier using MDDE. Figure 12. Measured waveforms of the resonant rectifier using MDDE. Figure 12. Measured waveforms of the resonant rectifier using MDDE.

Sensors 2017, 17, 901 Sensors 2017, 17, 901

13 of 15 13 of 15 100

700 Calculated Measured

600

IP= 600A

80

Efficiency ()

POUT (W)

500 400 300 200

IP= 400A

60

40

20

100 0

Calculated Measured

IP= 400A 0.5

1.0

1.5

2.0

2.5

3.0

0

IP= 600A 0.5

1.0

1.5

2.0

2.5

3.0

VRECT (V)

VRECT (V)

(a)

(b)

Figure 13. 13. Performance Performanceofofthe the rectifier using MDDE for Itwo IP values: (a) output power versus Figure rectifier using MDDE for two P values: (a) output power versus output output voltage; (b)transfer power transfer efficiency versus voltage. output voltage. voltage; and (b) and power efficiency versus output

Table 3 shows a performance comparison with previous works realized using IC technology. Table 3 shows a performance comparison with previous works realized using IC technology. The work in [2] presents a resonant rectifier using the bias-flip technique. The bias-flip timing is The work in [2] presents a resonant rectifier using the bias-flip technique. The bias-flip timing is controlled by a digital inverter delay line that can be programmed externally. Although the controlled by a digital inverter delay line that can be programmed externally. Although the adjustable adjustable delay control provides flexibility to accommodate various PE transducers, self-startup is delay control provides flexibility to accommodate various PE transducers, self-startup is not supported. not supported. Further, the efficiency of 58% is rather low, which can be attributed to the voltage Further, the efficiency of 58% is rather low, which can be attributed to the voltage drop in bias-flip drop in bias-flip switches and rectifying stages. In [4], a passive differentiator is used to detect the IP switches and rectifying stages. In [4], a passive differentiator is used to detect the IP polarity change. polarity change. In this work, two separate paths are used to reduce the voltage drop for bias-flip. A In this work, two separate paths are used to reduce the voltage drop for bias-flip. A relatively high relatively high POUT of 1230 μW is achieved under externally-powered conditions. The work in [6] POUT of 1230 µW is achieved under externally-powered conditions. The work in [6] proposes a parallel proposes a parallel synchronized switch harvesting on inductor (P-SSHI) technique which extracts synchronized switch harvesting on inductor (P-SSHI) technique which extracts 48 µW. The result 48 μW. The result in [20] shows a high efficiency of 91%. Including [20], however, the results in [4,6] in [20] shows a high efficiency of 91%. Including [20], however, the results in [4,6] are based on discrete are based on discrete realization and not included for comparison. realization and not included for comparison. Table 3. Performance comparison with previous works. Table 3. Performance comparison with previous works. This Work Rectifier [2] (MDDE) Rectifier Rectifier (LDDE) Rectifier This Work

Tech.

Tech.

(MDDE)

Type Type VP (V)VP (V)

Self-power

VRECT (V)

2.89

2.894.34 200

200

Thrive K7520BP2

4.34 2.8 225 V22B Mide

Thrive K7520BP2

Y 2.4

VRECT (V) 288 POUT (µW)

POUT (μW) 78.4 Efficiency (%)

Efficiency (%)

0.35 µm

Bias-flip/diode Bias-flip/diode equivalentBias-flip equivalent

PE transducer

Self-power

0.18 μm

0.18 µm

f0 (Hz) f 0 (Hz) PE transducer

(LDDE)

N

Y

3.36

2.4

564

288 68.1 78.4

N

N

3.2

[2]

[3] [3]

0.35 μm

0.18 µm

[22] [22]

0.18 0.18 μm 0.18 µm μm

0.35 µm

0.35 μm

Energy Bias-flip Active FBRActive FBR S-SSHI S-SSHI Energy Invest Invest 2.8 2.8

2.8

2.2

2.2

2.62.6

225200 200 200 200 143 143 V22B Circuit Circuit V22B Circuit model Circuit model V22B Mide MideN model Y model Mide N N N Y N 2.78

3.36

3.2

564 58 68.1

53 90 58

53

[21] [21]

81

3.6

2.78

74

81 89.5 90

3.7

3.6 74 89.5

[23]

[24]

[23]

0.35 μm

0.35 µm

[24]

0.25 μm

0.25 µm

Inductor Inductor-less SSHI SSHI -less 2.5 2.5

4.9 4.9

8282 144 144 V22W V22B V22W Mide V22B Mide Mide Mide Y N N Y 1.0

3.9

3.7

1.0

3.9

52 69

35 77 77

136 85 85

52 69

35

136

The [21][21] presents a series synchronized switch switch harvesting on inductor The work workinin presents a series synchronized harvesting on (S-SSHI) inductortechnique, (S-SSHI) which is applied to the conventional FBR. It shows a good efficiency of 89.5%. However, the results technique, which is applied to the conventional FBR. It shows a good efficiency of 89.5%. However, in [3,21] are obtained using an equivalent model of the PE transducer, therefore, its performance a the results in [3,21] are obtained using an equivalent model of the PE transducer, therefore,inits real environment unknown. The work [22] increases extraction by investing from the performance in aisreal environment is in unknown. The power work in [22] increases powerenergy extraction by battery to enhance the electromechanical coupling factor. The work in [23] presents a fully-integrated investing energy from the battery to enhance the electromechanical coupling factor. The work in [23] interface a PE transducer which does employ an inductor. dynamically switching between presents to a fully-integrated interface to not a PE transducer which By does not employ an inductor. By parallel and series configurations of two PE transducers, this work achieves a peak efficiency of dynamically switching between parallel and series configurations of two PE transducers, this work

achieves a peak efficiency of 77%. The work in [24] inserts an active diode in the resonant loop of

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77%. The work in [24] inserts an active diode in the resonant loop of the SSHI circuit which allows bias-flipping to occur at an optimal time without the need for complicated delay-tuning circuits. In the proposed rectifier using LDDE, we achieve an efficiency of 68.1% under the external-power condition. Under the self-power condition, the rectifier using MDDE delivers a POUT of 288 µW and a VRECT of 2.4 V. This corresponds to an efficiency of 78.4%. Although this efficiency number is lower than the results of [24], a POUT of 441 µW is extracted using IP = 600 µA, demonstrating the high power extraction capability of the proposed work. The results indicate the improvement is achieved using efficient bias-flipping with a low V D of the MDDE. 4. Conclusions In this work, we presented an efficient rectifier design technique for PE energy harvesting. To reduce the voltage drop in the rectifier, two diode equivalents are proposed. The diode equivalents are successfully embedded in two resonant rectifiers using the symmetric bias-flip technique. In addition, time synchronization of the bias-flip with the PE transducer is studied. Further, we propose a self-power boosted pulse generator that synchronously detects the zero crossing transition of the PE transducer. The measured results show that the proposed rectifiers significantly increase the extracted power and efficiency. The rectifier using LDDE delivers a POUT of 564 µW with a corresponding efficiency of 68.2%. The rectifier using MDDE delivers a POUT of 288 µW with a peak efficiency of 78.4%. Compared to the conventional FBR, these results show that the rectifier using MDDE and LDDE achieves a power extraction capability enhanced by factors of 5.9 and three times, respectively. The results indicate that an improvement is achieved with the proposed diode equivalents. This result can play a valuable role in various sensing applications that demand energy harvesting to obtain auxiliary power for extended battery lifetime. Acknowledgments: This research was supported by the Basic Science Research Program through the National Research Foundation (NRF) of Korea (No. 2015R1A2A2A03004160). Author Contributions: Amad Ud Din designed the resonant rectifiers and setup, performed the experimental work, and wrote the manuscript. Seneke Chamith Chandrathna supplied input to the rectifier operation and performed simulations. Jong-Wook Lee conceived the project, organized the paper content, and edited the manuscript. Conflicts of Interest: The authors declare no conflict of interest.

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