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Self-assembled nanowire array capacitors: capacitance and interface state profile
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2014 Nanotechnology 25 135201 (http://iopscience.iop.org/0957-4484/25/13/135201) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 137.229.5.94 This content was downloaded on 03/01/2015 at 12:36
Please note that terms and conditions apply.
Nanotechnology Nanotechnology 25 (2014) 135201 (6pp)
doi:10.1088/0957-4484/25/13/135201
Self-assembled nanowire array capacitors: capacitance and interface state profile Qiliang Li1,6 , Hao D Xiong2,3,6 , Xuelei Liang3,4,6 , Xiaoxiao Zhu1 , Diefeng Gu5 , Dimitris E Ioannou1 , Helmut Baumgart5 and Curt A Richter3 1
Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA 2 Department of Electrical and Electronic Engineering, South University of Science and Technology of China, Shenzhen, People’s Republic of China 3 Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, MD 20899, USA 4 Department of Electronics, Peking University, Beijing 100871, People’s Republic of China 5 Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529, USA E-mail: [email protected], [email protected] and [email protected] Received 3 December 2013, revised 19 January 2014 Accepted for publication 30 January 2014 Published 28 February 2014
Abstract
Direct characterization of the capacitance and interface states is very important for understanding the electronic properties of a nanowire transistor. However, the capacitance of a single nanowire is too small to precisely measure. In this work we have fabricated metal–oxide–semiconductor capacitors based on a large array of self-assembled Si nanowires. The capacitance and conductance of the nanowire array capacitors are directly measured and the interface state profile is determined by using the conductance method. We demonstrate that the nanowire array capacitor is an effective platform for studying the electronic properties of nanoscale interfaces. This approach provides a useful and efficient metrology for the study of the physics and device properties of nanoscale metal–oxide–semiconductor structures. Keywords: nanowire array, capacitance, interface states, MOS (Some figures may appear in colour only in the online journal)
1. Introduction
Among various nanowire based devices, the nanowire MOSFET has been considered as the fundamental device for future nanoelectronic circuits for logic, memory, optical and chemical sensing applications [9, 10]. The performance of the nanowire MOSFET will therefore determine the overall performance of the circuit. In addition, the quality of the nanowire MOSFET represents the degree of excellence and capability of a typical fabrication technology. Therefore, measurement of the properties of nanowire MOSFETs is an effective and efficient way to address issues in nanowire circuits as well as problems in the nanofabrication process. For the MOSFETs (including nanowire MOSFETs), the metal/oxide/nanowire gate stack is the key part for switching the transistor and controlling the current. The switching speed, threshold voltage and on/off-state currents are all directly related to the gate stack. In addition, the performance of
As metal–oxide–semiconductor field effect transistors (MOSFETs) are continuously scaled down to the nanoscale, nanowires have been considered as one of the most promising nanomaterials for future nanoelectronics. Nanowires can be prepared by a top-down approach which includes sophisticated electron-beam lithography and complicated wet/dry etching [1–4] or by bottom-up growth which forms the intrinsic nanowire on an atom-by-atom basis [5, 6]. Bottom-up grown nanowires have been of great interest for next-generation electronics because of their naturally grown smooth surface, small dimensions and potential for high-density self-assembled circuits at low cost [7, 8]. 6 Authors to whom any correspondence should be addressed.
0957-4484/14/135201+06$33.00
1
c 2014 IOP Publishing Ltd
Printed in the UK
Nanotechnology 25 (2014) 135201
Q Li et al
Figure 2. (a) Schematic of a single-nanowire MOS structure. (b)
Transmission electron microscopy image of the cross-section of a Si nanowire in the capacitor.
a direct measurement and analysis of nanowire capacitance and interface states will be very attractive for developing high-performance nanowire transistors and circuits. 2. Experimental details Figure 1. Scanning electron microscopy images of (a) a whole two-terminal Si nanowire array MOS capacitor (scale bar: 100 µm) and (b) part of the Si nanowire array capacitor showing arrays of nanowires covered by metal lines (scale bar: 20 µm).
Figure 1(a) shows a scanning electron microscopy (SEM) image of a MOS capacitor based on an array of Si nanowires (SiNWs). The SiNW capacitor was fabricated on a 4 in quartz wafer by self-aligning the arrays of nanowires. The insulating quartz wafer was used as the substrate for the nanowire MOS capacitor to avoid parasitic capacitance. The SiNWs were grown from Au catalysts on pre-defined locations using low pressure chemical vapor deposition with SiH4 at 0.5 Torr and 420 ◦ C. As shown in figure 1(b), the SiNW capacitor consists of many nanowires which are covered by metal lines. The density of the SiNWs in a capacitor can be tuned by adjusting the amount of Au catalyst, i.e. the thickness and area of Au film on pre-defined locations. The gate electrode (VG ), which covers the gate dielectric deposited on the SiNWs, and the bottom electrode (VB ), which directly contacts the SiNWs, are defined by photolithography and deposited by electron-beam evaporation of Al in different steps. A schematic of a single-nanowire MOS structure is shown in figure 2(a). A transmission electron microscopy (TEM) image of the cross-section of a typical nanowire MOS structure is shown in figure 2(b). The nanowires grow along the (111) direction. The gate dielectric is 20-nm HfO2 which was deposited by atomic layer deposition (ALD) at 250 ◦ C. The ALD process enables the HfO2 to surround the nanowires. In this work, the SiNW MOS capacitor consists of an array of gate electrodes on the top of HfO2 and an array of bottom electrodes contacting the SiNWs. These two arrays of electrodes are in parallel and are shown in figures 1(a) and (b). We can use n and W , which are the number of lines and the
the flash-like charge trapping memory is determined by the quality of the gate stack [11]. Therefore, it is important to have a precise characterization and analysis of the physical and electrical properties of the metal/oxide/nanowire capacitor structure. However, a precise study of the electrical properties of such a nanoscale nanowire MOS capacitor is very challenging as its gate capacitance is too small ( 5 at 1 kHz). Note that the capacitance (like the quality factor) apparently decreases at higher frequencies ( f > 10 kHz) due to the large series resistance of the intrinsic SiNWs. The accumulation and depletion of the nanowire capacitor are clearly shown in the C–V curve (figure 3), which is similar to a MOS capacitor with a lightly-doped p-type Si substrate. The ratio of the capacitance between accumulation and depletion is about six times at maximum. This remarkable difference between depletion and accumulation indicates that the capacitance of the semiconducting nanowire was directly measured. Compared with the results for InAs capacitors [15], the SiNW array capacitors show much larger capacitance, which is good for precise measurement, and a much larger ratio between the capacitance of accumulation and depletion. It is noted that we have used the insulating quartz substrate to effectively avoid the parasitic capacitance. Otherwise, if a SiO2 /Si wafer substrate is used, the parasitic capacitance between the electrodes coupled by the Si wafer underneath may dominate the whole capacitance.
I =C
dVG ; dt
(2)
where C is the capacitance of the nanowire array capacitor. The displacement current is positive when the voltage is scanned in the positive direction and negative when the voltage is scanned in the negative direction. Therefore, the displacement current has the same shape as the quasi-static capacitance of the SiNW capacitor. As shown in figure 5(a), the displacement current (a larger view of the top curve in figure 4) clearly indicates 3
Nanotechnology 25 (2014) 135201
Q Li et al
Figure 6. The correspondence between energy position in the SiNW
band gap and gate voltage VG .
Figure 5. (a) Displacement current measured at an increasing sweep rate: 0.3 V s−1 showing the accumulation, depletion and inversion regions of the SiNW. (b) Quasi-static capacitance of the SiNW array capacitor calculated based on displacement current. Figure 7. Conductance method: (G p /ω) versus ω at gate voltages varying from −4.0 to 4.0 V. The peak of the curves decreases from −4.0 to 0.25 V and increases from 0.25 to 4.0 V.
the accumulation, depletion and inversion of the SiNWs at different gate voltages, which is similar to a quasi-static C–V curve. The saturated current in the accumulation and inversion of the metal/oxide/SiNW capacitor is similar to the charge displacement in a parallel-plate capacitor. The V-shaped current during depletion is caused by the decrease in capacitance as the SiNWs are being depleted. Therefore, the quasi-static capacitance of the nanowire array capacitor can be calculated by C = I /υ. The result is shown in figure 5(b). From the quasi-static capacitance, the surface potential of the SiNWs at different gate voltages can be calculated by the following equation [19, 20]: 9S (VG ) − 9S (VG0 ) =
Z
VG
1−
VG0
C COX
dVG0 ;
as a function of gate voltage can be calculated by integrating the curve of (1 − C/Cox ). Therefore, the energy position (E) relative to the valence band (E V ) is (E − E V ) within the band gap of the SiNWs. It can be derived as a function of gate voltage: (E − E V ) = e9S (VG ); (4) where E V is the valence band of the SiNW. The calculated (E − E V ) versus VG relationship is plotted in figure 6, showing the total band gap of the SiNW ≈ 1.12 eV. This relationship between energy position and gate voltage will be used to obtain the interface state profile within the band gap of SiNWs. The interface state density of the HfO2 –Si interface can be measured by many methods, for example the high/lowfrequency C–V method [21, 22]. However, the conductance method is generally considered to be one of the most precise methods for measuring Dit [19, 22, 23]. It is based on the measurement of the equivalent parallel conductance (G P ) of
(3)
where 9S (VG ) is the surface potential as a function of VG and 9S (VG0 ) is the surface potential at a starting gate voltage (VG0 ). In this work, VG0 is selected as VG = −4.0 V at which the capacitor is accumulated with holes. The surface potential 4
Nanotechnology 25 (2014) 135201
Q Li et al
data reported by other groups [23–25]. In addition, a hump of Dit appears at E t ≈ 0.27 eV which may be due to Au contamination at SiNW surface during the growth. However, a more meaningful characterization of Au contamination on SiNW is noise spectroscopy [26]. 4. Summary
We have fabricated and characterized MOS capacitors based on self-assembled Si nanowire arrays. We have used the nanowire array capacitor as a device testing platform to study the capacitance and conductance of the nanowires, and probably more interestingly the nanowire–dielectric interface state profile. This work has proposed and analyzed a new effective nanowire array capacitor testing structure and the related metrology. This study is very attractive and important to the study of self-assembled nanowire devices and structures. Figure 8. Distribution of interface state density (Dit ) in the Si
nanowire band gap.
Acknowledgments
a MOS capacitor as a function of bias voltage and angular frequency (ω) [23]. Since the SiNW array capacitor has a relatively large capacitance (>100 pF) compared to the capacitance of a single nanowire (at 1 fF range), we can perform a precise impedance–frequency measurement. Figure 7 shows G P /ω versus ω curves at gate voltages varying from −4.0 to 4.0 V measured with a small signal amplitude of 30 mV. A clear peak can be observed for the curves at each frequency. In this range of gate voltages, the SiNW capacitor is first in accumulation, then depletion, and finally inversion, allowing direct measurement of SiNW interface state profile within the Si band gap. We can reasonably assume a continuum of interface states in the HfO2 –Si interface. Therefore, Dit can be defined from the maximum of G P /ω versus ω by using the conductance method. G P /ω can be expressed as [22, 23]: GP q Dit = ln[1 + (ωτit )2 ]; ω 2ωτit
The work described here was supported in part by NIST grant 60NANB11D148 and NSF grant ECCS-0846649. X Liang acknowledged the support of the Ministry of Science and Technology of China, grant no 2011CB921904. References [1] Gunawan O, Sekaric L, Majumdar A, Rooks M, Appenzeller J, Sleight J W, Guha S and Haensch W 2008 Measurement of carrier mobility in silicon nanowires Nano Lett. 8 1566 [2] Sekaric L, Gunawan O, Majumdar A, Liu X H, Weinstein D and Sleight J 2009 Size-dependent modulation of carrier mobility in top–down fabricated silicon nanowires Appl. Phys. Lett. 95 023113 [3] Peng J W, Lee S J, Liang G C A, Singh N, Zhu S Y, Lo G Q and Kwong D L 2008 Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors Appl. Phys. Lett. 93 073503 [4] Koo S-M, Li Q, Edelstein M D, Richter C A and Vogel E M 2005 Enhanced channel modulation in dual-gated silicon nanowire transistors Nano Lett. 5 2519 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149 [6] Schmidt V, Riel H, Senz S, Karg S, Riess W and G¨osele U 2006 Realization of a silicon nanowire vertical surround-gate field-effect transistor Small 2 85 [7] Lu W and Lieber C M 2007 Nanoelectronics from the bottom up Nature Mater. 6 841–50 [8] Yan H, Choe H S, Nam S, Hu Y, Das S, Klemic J F, Ellenbogen J C and Lieber C M 2011 Programmable nanowire circuits for nanoprocessors Nature 470 240–4 [9] Yu G H and Lieber C M 2010 Assembly and integration of semiconductor nanowires for functional nanosystems Pure Appl. Chem. 82 2295–314 [10] Tian B Z, Cohen-Karni T, Qing Q, Duan X, Xie P and Lieber C M 2010 Three-dimensional, flexible nanoscale field-effect transistors as localized bioprobes Science 329 830
(5)
where τit is the interface trap time constant and q is the magnitude of electron charge. Dit can be calculated from the maxima of the (G P /ω)–ω plots at different gate voltages: GP 2.5/q. (6) Dit = ω Max By using the correspondence between gate voltage and interface state position within the band gap (E − E v ) shown in figure 6, the interface state profile can be obtained. The calculated interface state density Dit versus (E − E v ) is shown in figure 8. This U-shape Dit distribution over the Si energy band gap is quite often observed in Si–dielectric interfaces. It should be noted that the conductance method yields a good measurement typically from flatband to weak inversion, which corresponds to a value of (E t − E v ) ranging from 0.3 to 0.5 eV [22]. At this energy position, the Dit of the HfO2 /Si on the SiNW extracted from figure 8 is about 1 × 1012 cm−2 eV−1 . This value is within the range of 5
Nanotechnology 25 (2014) 135201
Q Li et al
[11] Zhu X, Li Q, Ioannou D E, Gu D, Bonevich J E, Baumgart H, Suehle J S and Richter C A 2011 Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells Nanotechnology 22 254020 [12] Wunnicke O 2006 Gate capacitance of back-gated nanowire field-effect transistors Appl. Phys. Lett. 89 083102 [13] Zhao H et al 2009 Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM technique IEEE Electron Device Lett. 30 526–8 [14] Tu R, Zhang L, Nishi Y and Dai H 2007 Measuring the capacitance of individual semiconductor nanowires for carrier mobility assessment Nano Lett. 7 1561–5 [15] Roddaro S, Nilsson K, Astromskas G, Samuelson L, Wernersson L-E, Karlstrom O and Wacker A 2008 InAs nanowire metal–oxide–semiconductor capacitors Appl. Phys. Lett. 92 253509 [16] Astromskas G, Storm K and Wernersson L-E 2011 Transient studies on InAs/HfO2 nanowire capacitors Appl. Phys. Lett. 98 013501 [17] Li Q, Zhu X, Yang Y, Ioannou D E, Xiong H D, Kwon D-W, Suehle J S and Richter C A 2009 The large-scale integration of high-performance silicon nanowire field effect transistor Nanotechnology 20 415202 [18] Richter C A, Xiong H D, Zhu X, Wang W, Stanford V M, Hong W-K, Lee T, Ioannou D E and Li Q 2008 Metrology for the electrical characterization of semiconductor nanowires IEEE Trans. Electron Devices 55 3086–95
[19] Nicollian E H and Brews J R 2002 MOS (Metal Oxide Semiconductor) Physics and Technology (New York: Wiley–Interscience) [20] Moragues J M, Ciantar E, Jerisian R, Sagnes B and Oualid J 1994 Surface-potential determination in metal–oxide–semiconductor capacitors J. Appl. Phys. 76 5278–87 [21] Berglund C N 1966 Surface states at steam-grown silicon-silicon dioxide interfaces IEEE Electron Device Lett. 13 701–5 [22] Schroder D K 1998 Semiconductor Materials and Device Characterization 2nd edn (New York: Wiley) p 376 [23] Piscator J, Raeissi B and Engstrom O 2009 The conductance method in a bottom-up approach applied on hafnium oxide/silicon interfaces Appl. Phys. Lett. 94 213507 [24] Wong H, Zhan N, Ng K L, Poon M C and Kok C W 2004 Interface and oxide traps in high-kappa hafnium oxide films Thin Solid Films 462–463 96–100 [25] Duenas S, Castan H, Garcia H, Barbolla J, Kukli K, Aarik J and Aidla A 2004 The electrical-interface quality of as-grown atomic-layer-deposited disordered HfO2 on pand n-type silicon Semicond. Sci. Technol. 19 1141–8 [26] Sharma D, Motayed A, Krylyuk S, Li Q and Davydov A V 2013 Detection of deep-levels in doped silicon nanowires using low-frequency noise spectroscopy IEEE Trans. Electron Devices 60 4206
6
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My IOPscience
Self-assembled nanowire array capacitors: capacitance and interface state profile
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2014 Nanotechnology 25 135201 (http://iopscience.iop.org/0957-4484/25/13/135201) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 137.229.5.94 This content was downloaded on 03/01/2015 at 12:36
Please note that terms and conditions apply.
Nanotechnology Nanotechnology 25 (2014) 135201 (6pp)
doi:10.1088/0957-4484/25/13/135201
Self-assembled nanowire array capacitors: capacitance and interface state profile Qiliang Li1,6 , Hao D Xiong2,3,6 , Xuelei Liang3,4,6 , Xiaoxiao Zhu1 , Diefeng Gu5 , Dimitris E Ioannou1 , Helmut Baumgart5 and Curt A Richter3 1
Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA 2 Department of Electrical and Electronic Engineering, South University of Science and Technology of China, Shenzhen, People’s Republic of China 3 Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, MD 20899, USA 4 Department of Electronics, Peking University, Beijing 100871, People’s Republic of China 5 Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529, USA E-mail: [email protected], [email protected] and [email protected] Received 3 December 2013, revised 19 January 2014 Accepted for publication 30 January 2014 Published 28 February 2014
Abstract
Direct characterization of the capacitance and interface states is very important for understanding the electronic properties of a nanowire transistor. However, the capacitance of a single nanowire is too small to precisely measure. In this work we have fabricated metal–oxide–semiconductor capacitors based on a large array of self-assembled Si nanowires. The capacitance and conductance of the nanowire array capacitors are directly measured and the interface state profile is determined by using the conductance method. We demonstrate that the nanowire array capacitor is an effective platform for studying the electronic properties of nanoscale interfaces. This approach provides a useful and efficient metrology for the study of the physics and device properties of nanoscale metal–oxide–semiconductor structures. Keywords: nanowire array, capacitance, interface states, MOS (Some figures may appear in colour only in the online journal)
1. Introduction
Among various nanowire based devices, the nanowire MOSFET has been considered as the fundamental device for future nanoelectronic circuits for logic, memory, optical and chemical sensing applications [9, 10]. The performance of the nanowire MOSFET will therefore determine the overall performance of the circuit. In addition, the quality of the nanowire MOSFET represents the degree of excellence and capability of a typical fabrication technology. Therefore, measurement of the properties of nanowire MOSFETs is an effective and efficient way to address issues in nanowire circuits as well as problems in the nanofabrication process. For the MOSFETs (including nanowire MOSFETs), the metal/oxide/nanowire gate stack is the key part for switching the transistor and controlling the current. The switching speed, threshold voltage and on/off-state currents are all directly related to the gate stack. In addition, the performance of
As metal–oxide–semiconductor field effect transistors (MOSFETs) are continuously scaled down to the nanoscale, nanowires have been considered as one of the most promising nanomaterials for future nanoelectronics. Nanowires can be prepared by a top-down approach which includes sophisticated electron-beam lithography and complicated wet/dry etching [1–4] or by bottom-up growth which forms the intrinsic nanowire on an atom-by-atom basis [5, 6]. Bottom-up grown nanowires have been of great interest for next-generation electronics because of their naturally grown smooth surface, small dimensions and potential for high-density self-assembled circuits at low cost [7, 8]. 6 Authors to whom any correspondence should be addressed.
0957-4484/14/135201+06$33.00
1
c 2014 IOP Publishing Ltd
Printed in the UK
Nanotechnology 25 (2014) 135201
Q Li et al
Figure 2. (a) Schematic of a single-nanowire MOS structure. (b)
Transmission electron microscopy image of the cross-section of a Si nanowire in the capacitor.
a direct measurement and analysis of nanowire capacitance and interface states will be very attractive for developing high-performance nanowire transistors and circuits. 2. Experimental details Figure 1. Scanning electron microscopy images of (a) a whole two-terminal Si nanowire array MOS capacitor (scale bar: 100 µm) and (b) part of the Si nanowire array capacitor showing arrays of nanowires covered by metal lines (scale bar: 20 µm).
Figure 1(a) shows a scanning electron microscopy (SEM) image of a MOS capacitor based on an array of Si nanowires (SiNWs). The SiNW capacitor was fabricated on a 4 in quartz wafer by self-aligning the arrays of nanowires. The insulating quartz wafer was used as the substrate for the nanowire MOS capacitor to avoid parasitic capacitance. The SiNWs were grown from Au catalysts on pre-defined locations using low pressure chemical vapor deposition with SiH4 at 0.5 Torr and 420 ◦ C. As shown in figure 1(b), the SiNW capacitor consists of many nanowires which are covered by metal lines. The density of the SiNWs in a capacitor can be tuned by adjusting the amount of Au catalyst, i.e. the thickness and area of Au film on pre-defined locations. The gate electrode (VG ), which covers the gate dielectric deposited on the SiNWs, and the bottom electrode (VB ), which directly contacts the SiNWs, are defined by photolithography and deposited by electron-beam evaporation of Al in different steps. A schematic of a single-nanowire MOS structure is shown in figure 2(a). A transmission electron microscopy (TEM) image of the cross-section of a typical nanowire MOS structure is shown in figure 2(b). The nanowires grow along the (111) direction. The gate dielectric is 20-nm HfO2 which was deposited by atomic layer deposition (ALD) at 250 ◦ C. The ALD process enables the HfO2 to surround the nanowires. In this work, the SiNW MOS capacitor consists of an array of gate electrodes on the top of HfO2 and an array of bottom electrodes contacting the SiNWs. These two arrays of electrodes are in parallel and are shown in figures 1(a) and (b). We can use n and W , which are the number of lines and the
the flash-like charge trapping memory is determined by the quality of the gate stack [11]. Therefore, it is important to have a precise characterization and analysis of the physical and electrical properties of the metal/oxide/nanowire capacitor structure. However, a precise study of the electrical properties of such a nanoscale nanowire MOS capacitor is very challenging as its gate capacitance is too small ( 5 at 1 kHz). Note that the capacitance (like the quality factor) apparently decreases at higher frequencies ( f > 10 kHz) due to the large series resistance of the intrinsic SiNWs. The accumulation and depletion of the nanowire capacitor are clearly shown in the C–V curve (figure 3), which is similar to a MOS capacitor with a lightly-doped p-type Si substrate. The ratio of the capacitance between accumulation and depletion is about six times at maximum. This remarkable difference between depletion and accumulation indicates that the capacitance of the semiconducting nanowire was directly measured. Compared with the results for InAs capacitors [15], the SiNW array capacitors show much larger capacitance, which is good for precise measurement, and a much larger ratio between the capacitance of accumulation and depletion. It is noted that we have used the insulating quartz substrate to effectively avoid the parasitic capacitance. Otherwise, if a SiO2 /Si wafer substrate is used, the parasitic capacitance between the electrodes coupled by the Si wafer underneath may dominate the whole capacitance.
I =C
dVG ; dt
(2)
where C is the capacitance of the nanowire array capacitor. The displacement current is positive when the voltage is scanned in the positive direction and negative when the voltage is scanned in the negative direction. Therefore, the displacement current has the same shape as the quasi-static capacitance of the SiNW capacitor. As shown in figure 5(a), the displacement current (a larger view of the top curve in figure 4) clearly indicates 3
Nanotechnology 25 (2014) 135201
Q Li et al
Figure 6. The correspondence between energy position in the SiNW
band gap and gate voltage VG .
Figure 5. (a) Displacement current measured at an increasing sweep rate: 0.3 V s−1 showing the accumulation, depletion and inversion regions of the SiNW. (b) Quasi-static capacitance of the SiNW array capacitor calculated based on displacement current. Figure 7. Conductance method: (G p /ω) versus ω at gate voltages varying from −4.0 to 4.0 V. The peak of the curves decreases from −4.0 to 0.25 V and increases from 0.25 to 4.0 V.
the accumulation, depletion and inversion of the SiNWs at different gate voltages, which is similar to a quasi-static C–V curve. The saturated current in the accumulation and inversion of the metal/oxide/SiNW capacitor is similar to the charge displacement in a parallel-plate capacitor. The V-shaped current during depletion is caused by the decrease in capacitance as the SiNWs are being depleted. Therefore, the quasi-static capacitance of the nanowire array capacitor can be calculated by C = I /υ. The result is shown in figure 5(b). From the quasi-static capacitance, the surface potential of the SiNWs at different gate voltages can be calculated by the following equation [19, 20]: 9S (VG ) − 9S (VG0 ) =
Z
VG
1−
VG0
C COX
dVG0 ;
as a function of gate voltage can be calculated by integrating the curve of (1 − C/Cox ). Therefore, the energy position (E) relative to the valence band (E V ) is (E − E V ) within the band gap of the SiNWs. It can be derived as a function of gate voltage: (E − E V ) = e9S (VG ); (4) where E V is the valence band of the SiNW. The calculated (E − E V ) versus VG relationship is plotted in figure 6, showing the total band gap of the SiNW ≈ 1.12 eV. This relationship between energy position and gate voltage will be used to obtain the interface state profile within the band gap of SiNWs. The interface state density of the HfO2 –Si interface can be measured by many methods, for example the high/lowfrequency C–V method [21, 22]. However, the conductance method is generally considered to be one of the most precise methods for measuring Dit [19, 22, 23]. It is based on the measurement of the equivalent parallel conductance (G P ) of
(3)
where 9S (VG ) is the surface potential as a function of VG and 9S (VG0 ) is the surface potential at a starting gate voltage (VG0 ). In this work, VG0 is selected as VG = −4.0 V at which the capacitor is accumulated with holes. The surface potential 4
Nanotechnology 25 (2014) 135201
Q Li et al
data reported by other groups [23–25]. In addition, a hump of Dit appears at E t ≈ 0.27 eV which may be due to Au contamination at SiNW surface during the growth. However, a more meaningful characterization of Au contamination on SiNW is noise spectroscopy [26]. 4. Summary
We have fabricated and characterized MOS capacitors based on self-assembled Si nanowire arrays. We have used the nanowire array capacitor as a device testing platform to study the capacitance and conductance of the nanowires, and probably more interestingly the nanowire–dielectric interface state profile. This work has proposed and analyzed a new effective nanowire array capacitor testing structure and the related metrology. This study is very attractive and important to the study of self-assembled nanowire devices and structures. Figure 8. Distribution of interface state density (Dit ) in the Si
nanowire band gap.
Acknowledgments
a MOS capacitor as a function of bias voltage and angular frequency (ω) [23]. Since the SiNW array capacitor has a relatively large capacitance (>100 pF) compared to the capacitance of a single nanowire (at 1 fF range), we can perform a precise impedance–frequency measurement. Figure 7 shows G P /ω versus ω curves at gate voltages varying from −4.0 to 4.0 V measured with a small signal amplitude of 30 mV. A clear peak can be observed for the curves at each frequency. In this range of gate voltages, the SiNW capacitor is first in accumulation, then depletion, and finally inversion, allowing direct measurement of SiNW interface state profile within the Si band gap. We can reasonably assume a continuum of interface states in the HfO2 –Si interface. Therefore, Dit can be defined from the maximum of G P /ω versus ω by using the conductance method. G P /ω can be expressed as [22, 23]: GP q Dit = ln[1 + (ωτit )2 ]; ω 2ωτit
The work described here was supported in part by NIST grant 60NANB11D148 and NSF grant ECCS-0846649. X Liang acknowledged the support of the Ministry of Science and Technology of China, grant no 2011CB921904. References [1] Gunawan O, Sekaric L, Majumdar A, Rooks M, Appenzeller J, Sleight J W, Guha S and Haensch W 2008 Measurement of carrier mobility in silicon nanowires Nano Lett. 8 1566 [2] Sekaric L, Gunawan O, Majumdar A, Liu X H, Weinstein D and Sleight J 2009 Size-dependent modulation of carrier mobility in top–down fabricated silicon nanowires Appl. Phys. Lett. 95 023113 [3] Peng J W, Lee S J, Liang G C A, Singh N, Zhu S Y, Lo G Q and Kwong D L 2008 Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors Appl. Phys. Lett. 93 073503 [4] Koo S-M, Li Q, Edelstein M D, Richter C A and Vogel E M 2005 Enhanced channel modulation in dual-gated silicon nanowire transistors Nano Lett. 5 2519 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149 [6] Schmidt V, Riel H, Senz S, Karg S, Riess W and G¨osele U 2006 Realization of a silicon nanowire vertical surround-gate field-effect transistor Small 2 85 [7] Lu W and Lieber C M 2007 Nanoelectronics from the bottom up Nature Mater. 6 841–50 [8] Yan H, Choe H S, Nam S, Hu Y, Das S, Klemic J F, Ellenbogen J C and Lieber C M 2011 Programmable nanowire circuits for nanoprocessors Nature 470 240–4 [9] Yu G H and Lieber C M 2010 Assembly and integration of semiconductor nanowires for functional nanosystems Pure Appl. Chem. 82 2295–314 [10] Tian B Z, Cohen-Karni T, Qing Q, Duan X, Xie P and Lieber C M 2010 Three-dimensional, flexible nanoscale field-effect transistors as localized bioprobes Science 329 830
(5)
where τit is the interface trap time constant and q is the magnitude of electron charge. Dit can be calculated from the maxima of the (G P /ω)–ω plots at different gate voltages: GP 2.5/q. (6) Dit = ω Max By using the correspondence between gate voltage and interface state position within the band gap (E − E v ) shown in figure 6, the interface state profile can be obtained. The calculated interface state density Dit versus (E − E v ) is shown in figure 8. This U-shape Dit distribution over the Si energy band gap is quite often observed in Si–dielectric interfaces. It should be noted that the conductance method yields a good measurement typically from flatband to weak inversion, which corresponds to a value of (E t − E v ) ranging from 0.3 to 0.5 eV [22]. At this energy position, the Dit of the HfO2 /Si on the SiNW extracted from figure 8 is about 1 × 1012 cm−2 eV−1 . This value is within the range of 5
Nanotechnology 25 (2014) 135201
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