Silicon-based silicon-germanium-tin heterostructure photonics.

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Silicon-based silicon−germanium−tin heterostructure photonics Richard Soref Phil. Trans. R. Soc. A 2014 372, 20130113, published 24 February 2014

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Silicon-based silicon–germanium–tin heterostructure photonics Richard Soref rsta.royalsocietypublishing.org

Discussion Cite this article: Soref R. 2014 Silicon-based silicon–germanium–tin heterostructure photonics. Phil. Trans. R. Soc. A 372: 20130113. http://dx.doi.org/10.1098/rsta.2013.0113

One contribution of 11 to a Discussion Meeting Issue ‘Beyond Moore’s law’.

Subject Areas: nanotechnology, microsystems, quantum engineering, optics, solid state physics, quantum physics Keywords: opto-electronics, integrated photonics, mid-infrared devices, silicon, germanium, communications Author for correspondence: Richard Soref e-mail: [email protected]

Department of Physics and the Engineering Program, The University of Massachusetts at Boston, 100 Morrissey Boulevard, Boston, MA 02125, USA The wavelength range that extends from 1550 to 5000 nm is a new regime of operation for Si-based photonic and opto-electronic integrated circuits. To actualize the new chips, heterostructure active devices employing the ternary SiGeSn alloy are proposed in this paper. Foundry-based monolithic integration is described. Opportunities and challenges abound in creating laser diodes, optical amplifiers, light-emitting diodes, photodetectors, modulators, switches and a host of high-performance passive infrared waveguided components.

1. Introduction The possibilities for new electrically biased SiGeSn heterostructure photonic components—especially laser diodes (LDs), photodetectors, optical amplifiers, lightemitting diodes (LEDs), tuneable filters, electro-optical modulators, reconfigurable add/drop multiplexers and waveguided routing switches—are discussed in this paper. I shall indicate how the physical properties of SiGeSn materials can be exploited to create the active devices and how those devices can be integrated monolithically in a photonic integrated ‘circuit’ (PIC) or opto-electronic integrated circuit (OEIC). Several types of monolithic integration are described, including PICs and OEICs manufactured in a silicon foundry. Silicon photonics (SiP) is a subset of group IV photonics (GFP). Today, the mainstays of SiP are the Ge photodetector, the Ge-quantum-well modulator, the SiGe Franz–Keldysh electro-absorptive modulator and the Geon-Si LD. Germanium’s direct bandgap of 0.8 eV imposes an upper limit of about 1550 nm upon the wavelength of operation λo . The introduction of the GFP SiGeSn material enables a significant increase in λo well beyond

2014 The Author(s) Published by the Royal Society. All rights reserved.


1550 nm. This paper examines what we can expect—the likely outcomes—of applying SiGeSn technology in the 1550–5000 nm wavelength range.

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The future of nanoelectronics includes a close integration with photonic and biological entities. My mission here is to illuminate the synergistic marriage of photonics with electronics on a silicon chip. I recognize that the substrate for OEICs could be InP rather than Si and that InP microwave transistors offer some of the highest speeds available. However, I shall leave the telling of that III– V story to other authors because my expertise resides in group IV semiconductors. It is important to expand the investigation of SiP to GFP because GFP is a more general technology with greater functionality than SiP. In fact, there is a parallel with nanoelectronics. The James S. Harris group at Stanford [1] proposes using GeSn to extend ‘Ge electronics’, and we know that SiGe has expanded ‘Si electronics’. Therefore, I think there is ‘group IV electronics’ (GFE) running parallel to GFP; so, GFE and GFP can converge. In addition, my colleagues and I have shown in a series of publications that a ‘group IV plasmonics’ exists. In this paper, I am emphasizing integrated GFP devices because of their wide wavelength scope. Around the world today, complementary metaloxide semiconductor (CMOS) foundries with an added photonic capability are coming on stream and promise to give high-volume OEIC creation at a cost-per-chip lower than that of any OE technology. For OEIC manufacture, the ‘silicon foundry advantage’ could be profound. For the commercial viability of these PICs and OEICs, it is important to manufacture the chips in a modern Si factory known as a technology node. Each node has its resolution and tapeout costs. The 130 and 65 nm nodes will be adequate for most OEIC applications because the minimum photonic-device dimension d is λo /2n, where n is the real index of the waveguide core—for example, d = 220 nm at λo = 1550 nm. I expect the above-mentioned technology nodes to provide an economic future for OEICs. In special cases where deep-subwavelength plasmonic devices are integrated with opto-electronics, an advanced node—such as 40 nm—may be required for chip manufacture. At 40 nm, the advanced field-effect transistors in the OEIC could be built upon bulk Si as well as on silicon-on-insulator (SOI). Then, photonic integration on bulk Si and SOI would be needed as explained in §3. As discussed below, to make the GFP material compatible with the Si substrate, it is sometimes necessary to deposit relaxed buffer layers on the Si in a local area underneath the photonic device. The buffer is a virtual substrate or VS whose lattice is larger than that of Si. The modern foundry nodes mentioned above ‘demand’ photonics that are commensurate with the electronics; that is, the electro-optical (EO) devices must have the lowest possible switching energy and the smallest possible footprint. The minimum on-chip area of a photonic or EO component is roughly λ2o or ‘wavelength scale’. Numerically, the footprint dimensions are in the micrometre scale when compared with the millimetre scale of the chip. These proportions reveal the real possibility of large-scale photonic integration (LSPI), which is defined here as more than 10 000 components on-chip. What then are the applications of LSPI? A few applications are clear; most are speculative. In the ‘less certain’ category, I propose wavelength-division optical interconnects, intelligent optical-routing networks, EO logic arrays, neural networks, quantumcomputing processors and all-optical computers using arrays of nanosized surface-plasmonic lasers [2] or nanoscale resonant surface-plasmon-emitting diodes. However, it is clear today that an immediate use of LSPI is in electrically controlled optical phased-arrays—namely beamsteered transmitters and receivers, where the infrared beam travels in free space. The Watts group at MIT [3,4] demonstrated recently an on-chip 4096-element rectangular array of group IV waveguided elements fed from one laser source. Although they tested an independent thermooptic (TO) phase shifter at each element, I would suggest employing instead an EO phase shifter in each ‘pixel’. A tiny surface-relief grating [3] or a pair of tiny metal nanoantennas [4] is located at each of N × N pixels, thereby coupling 1550-nm light at 4096 locations from a waveguide to free space or from space to a waveguide. At present, the reconfigurable TO pixel size is 9 × 9 μm,

rsta.royalsocietypublishing.org Phil. Trans. R. Soc. A 372: 20130113

2. Background discussion

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I see five types. Type 1 is the active PIC, which preferably has LDs on-chip, although a viable alternative is to place the LDs on the second PIC (an optical power supply) linked via waveguide to the first PIC chip. Silicon 1.3/1.6 μm PICs are the present focus of OE foundry research, but I advocate that this foundry approach should be enlarged to include Z-band SiGeSn PICs. Type 2 is the multi-chip module or multi-die module, of which one die is the monolithic PIC and the other dies are mainly electronics. Those dies are electrically and/or optically interconnected on a tiny platform or ‘circuit board’. Type 3 is the full-fledged CMOS foundry OEIC wherein the photonic fabrication process is integrated into the factory transistor-process flow to yield optics and electronics in the same layer or in adjacent layers. Type 4 is a variation on Type 3 in which a bulk Si or SOI nanoelectronic wafer has various areas that are deliberately left ‘blank’ giving exposed Si surfaces on which monolithic PICs are sited. The idea proposed here is that the PICs are each self-contained active-plus-passives ‘membranes’ discussed below. Each PIC is bonded as a unit. Type 5 integration refers to a fully three-dimensional OEIC ‘multi-technology chip’ that is illustrated in fig. 2 of [6]. Returning now to type 4, the OEIC engineer can choose to bond those approximately 1 μm thick group IV PICs to open Si surfaces with approximately 1 μm of benzo-cyclo-buten (BCB) polymer or he could bond the PIC membrane directly to Si with the transfer printing process developed by Prof. Z. Q. Ma [9] and Prof. W. Zhou [10]. The BCB approach is favoured by Prof. Meint Smit [11] of the COBRA Research Institute in his proposal for bonding an InGaAsP

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3. Types of monolithic integration

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but in principle each active pixel could be reduced to an area of 1 × 1 μm. Thus, the LSPI optical beamformer approach appears scalable to mega-pixel arrays. Group IV photonics presently deals with ultrafast datacom and telecom at the 1.31 and 1.55 μm fibre-optic transmission bands of major networks, respectively. However, the useful wavelengths for GFP extend well beyond telecom, as SiGeSn is highly transparent over wide stretches of the broad infrared spectrum, suggesting that GFP will have strong application in the midinfrared (MIR), far infrared and terahertz ranges [5]. Note also that GFP offers great microwave photonics potential, another direction for foundry manufacture. My coverage here is limited to the MIR regime from 1.55 μm out to about 5.00 μm, including thereby the 3–5 μm ‘window’ where the atmosphere is transparent. That window enables free-space uses of OEICs, although I will emphasize situations in which the infrared light is confined within various waveguided devices on the chip. It is important to recognize that there are several infrared-manipulation technologies that work closely with photonics; namely plasmonics, photonic-crystals, opto-electro-mechanics, optofluidics and ‘biologics’. I am advancing the idea that these can be integrated intimately with photonics on the same nanoelectronics substrate. When GFP operation is extended from 1.55 to 5.00 μm, the mission of fast optical communications is supplemented by the new applications listed in my 2013 Photonics West paper [6]. Principal among these is photonically enabled sensing, referring to the detection/identification of chemical, biological and physical variables with a PIC or OEIC— an application that might eventually eclipse communications-and-computing in importance. As detailed below, the focus of this paper is the relatively new ternary SiGeSn discussed at length in the empirical-pseudopotential theory paper of Moontragoon, Soref and Ikonic [7] (known hereafter as MSI). The silicon foundry compatibility of SiGeSn must be established soon in order to validate the thrust of this paper, and I believe it will be proved. I also believe that the SiGeSn heterostructures explored in this paper can play a role in the new terabit/s fibreoptic communications systems being created for next-generation photonic-bandgap fibres in the 1.9–2.1 μm communications band [8]. For easy reference, I shall assign the somewhat facetious term ‘Z band’ to denote the new approximately 2 μm wavelength communications band. I am hoping that GFP Z-band will prove cost-effective for both long-haul networks and short-haul fibre interconnects (active optical cables). Z-band systems are intended to supplement the 1.55 μm network infrastructure.


The MSI paper examined unstrained relaxed material (r-SiGeSn); however, in many instances GFP is a strained-layer heterostructure technology. The band theory for strained SiGeSn is unfortunately incomplete. Therefore, the unfinished task of theory (and experiment!) awaits us for tensile-strained (t) and compressively strained (c) layers: t-SiGeSn and c-SiGeSn, respectively. This is biaxial strain with tension or compression in the growth plane. Along with dual heterostructures (DHs), multiple-quantum-well (MQW) structures are of key importance. The use of strain, or the lack of it, determines to some extent the wavelength of operation. The fully relaxed (r), lattice-matched MQW is one approach. But beyond that, we can employ an MQW having asymmetric strain (an r-c or an r-t alternation) or balanced strain (equal-and-opposite cand t-layers alternated on a relaxed VS of ‘midway’ composition). For the asymmetric case, the build-up of net strain along the heterostack axis limits the number of QWs that can be used before the stack cracks. Strain balance is better but more complicated. Examples of asymmetric strain are: (i) the LD design of Chang et al. [12] using N-doped t-Ge QWs with r-SiGeSn barriers and (ii) the photodiode (PD) experiments of Gassenq et al. [13] that employed a 3-QW PD stack of c-GeSn with r-Ge barriers. Their limit of three wells in turn limited the responsivity for normal incidence. Also, their QWs were dominated by the conduction-band (c.b.) L valley, not by the Γ valley, which is acceptable in a PD but not in an LD. A good example of strain balance is the LD proposal of Chang et al. [14] for c-Ge0.84 Sn0.16 QWs with t-Si0.09 Ge0.80 Sn0.11 barriers sited on a r-Ge0.86 Sn0.12 buffer on Si. The 16% Sn concentration gave directness in the wells and the GeSn compression split the degeneracy of LH and HH in the valence band (v.b.). For the TE polarization, they calculate high

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4. Strained-layer group IV devices

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PIC membrane to Si CMOS or to a network of SOI waveguides. I would describe COBRA as a heterogeneous hybrid integration, not monolithic. However, the group IV PIC membrane case is ‘almost monolithic’ because both the ‘bonded and the bondee’ are in group IV; hence, this hybrid is homogeneous. Transfer printing is, in principle, foundry compatible. Transfer would be accomplished using pick-and-place robotic equipment that ‘prints’ on CMOS the group IV PICs that were previously lifted off of a sacrificial substrate. I claim that transfer printing can be done on bulk Si or SOI. For that purpose, I am suggesting an active monolithic membrane that includes a network of passive strip waveguides that are held together mechanically by SiO2 that fills all the interguide spaces. When the membrane is printed to SOI, the in-membrane singlemode strip waveguide cores would be silicon, meaning that each strip becomes a silicon rib waveguide when it is bonding closely to thin-film SOI. When printing the membrane to bulk silicon, we require a strong index contrast between the membrane’s waveguide strips and the bulk silicon after bonding is performed. Therefore, drawing upon published Ge/Si results and my recommendation for SiGeSn/Si channels, the group IV membrane shall contain a series of waveguiding SiGeSn strips that contrast optically with the underlying bulk Si after bonding. Because the membrane fabrication is preferably a foundry process, the printed OEIC requires the first and the second foundry process. In addition, the membrane PIC requires local-area-on-Si buffering of its active devices. If desired, a guideless group IV PIC could be bonded to a network of on-chip waveguides. In that connection, I want to add that the hybrid integration of 1.55-μm III–V microlasers on silicon has been a huge success. Such hybridization will carry forward into the MIR I believe. Thus, when we consider individual MIR LDs, semiconductor optical amplifiers (SOAs) and LEDs—or arrays thereof—those components can be thought of as mini-membranes. Hence, there is a sub-category of type 4 integration, which is the bonding of mini-dies onto a group IV waveguide network. Returning to type 5, this is truly a ‘futuristic’ chip for which a large number of technical/process details must be worked out before it becomes a reality. In the three-dimensional multilayer, one or more technologies can be within one layer, and vertical interlayer communication is required. My three-dimensional prescription does not show specifically how the plasmonic, photonic crystal, opto-electro-mechanical, microfluidic and biological technologies would be inserted in the factory flow.


gain at the MIR 2900 nm wavelength, suitable for lasing. This strain-balanced structure is relevant to the thrusts of this paper.

6. Results so far Most of the experimental work has been on the binary GeSn. The history of GeSn is long. Happily, at present we are witnessing a build-up of research momentum as groups around the world investigate GeSn MBE, CVD, solid-phase epitaxy (SPE) and re-crystallization of the amorphous. Along with Prof. J. Menendez, Prof. J. Kouvetakis’ group at Arizona State University has pioneered the growth of crystalline SiGeSn, including epitaxy directly upon silicon. Their numerous publications are listed at a web site [19] where they present recent device work [20,21] on SiGeSn/Ge and GeSn/Si PDs, along with GeSn electro-luminescence (EL) studies. They have also grown a few SiSn samples. They promote the independent adjustment of strain and bandgap in SiGeSn. I have co-authored work on N-doped GeSn as a plasmonic conductor material for GeSn/Ge surface-plasmon/photonic applications [22]. Prof. E. Kasper and his colleagues have done fine work on GeSn epitaxy, LEDs and photodetectors [23], all of which is detailed at the Universitat Stuttgart web site [24]. Prof. H. Cheng’s group reports strong EL in GeSn [25]. Lieten et al. [26] used SPE to grow annealed GeSn on Si(111) and the mismatch in thermal expansion between GeSn and Si led to tensile GeSn during cooling. Si/GeSn/Si represents a lattice-mismatched strategy in which the GeSn has dislocations at both of its hetero-interfaces. Lin et al. [27] grew SiGeSn on InGaAs. The MSI theory paper gives design rules for type-1 direct-gap MQW photonic structures operating in the 2.8–6.2 μm range. The same paper points out that the ‘large’ SiGeSn lattice parameter must be dealt with. The ternary parameter is larger than that of Si or Ge. It approaches 5.9 Å when the Sn concentration is raised from zero to approximately 40%.

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The CSiGeSn quaternary is the most general or ‘ultimate’ alloy—of which the ternaries CSiGe [15], CSiSn, CGeSn and SiGeSn are subsets. The ternaries in turn can be decomposed into binaries SiGe, CSi, CGe, SiSn, GeSn and CSn. Here, carbon stands for the cubic phase of diamond. Today, all of the various carbon-containing alloys are essentially unexplored experimentally, and there are reasons to investigate these materials. I find indications that CSiGeSn contains alloys with a truly direct bandgap in the 0.8–1.2 eV range. According to Pandey et al. [16], my 1992 prediction [17] of an indirect bandgap for the stoichiometric Sn0.5 C0.5 alloy is incorrect because their linear combination of atomic orbitals theory indicates a 0.75 eV direct gap for this crystal. Employing an Eg versus %Sn plot of the Sn1−x Cx system, I have performed a linear interpolation by connecting the c.b. L-valley and Γ -valley energies of cubic tin (+0.960, −0.413 eV) with the corresponding c.b. energies of diamond (6.50, 7.35 eV), and I find compositions x having ‘true directness’ in the telecoms range. However, that primitive procedure does not take into account the real-world bowing of Eg ; nevertheless, the ‘directness suggestion’ remains. This L-Γ exercise gives me an opportunity to replace the incorrect α-Sn value of EΓ = 0 eV used in figure 2 of my 1991 article [18] by the accepted value of EΓ = −0.413 eV. When that change is made, a more realistic estimate of the direct-gap region of SiGeSn is given in my modified 1991 figures, a region that extends to higher energies. When considering the research frontier of carbon-containing alloys, it is clear that their band theory and their epitaxial growth present tremendous challenges. That is why I shall leave exploration of these alloys to the future, despite the prospect of directness, and shall concentrate instead upon the more immediate prospects of carbon-less SiGeSn. I say ‘immediate’ and yet difficulties abound, especially for materials requiring a large fraction of tin. A ‘miscibility gap’ might be found—analogous to that seen in III–Vs—meaning that it might be impossible to grow certain high-Sn compositions. Low-temperature growth is imposed to avoid Sn segregation. Also, there is an issue of the thermodynamic phase stability of the random and ordered SiGeSn alloys. Can epitaxial stabilization and non-equilibrium growth help? All of these questions warrant study.


5. Priorities in group IV alloys

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7. Temperature of operation

The active layers of the Si-based SiGeSn LDs/SOAs/LEDs are sandwiched between P-doped and N-doped contact layers to form a PN or PIN waveguided diode. We categorize actives as homojunction or heterojunction devices—and the relaxed VS-on-silicon is inevitable. A heterostructure interfaces an SiGeSn active layer of ‘composition 1’ with a wider-bandgap cladding or barrier layer of SiGeSn having ‘composition 2’, written as SiGeSn/SiGeSn’. These band-to-band active photonic devices can be single heterodiodes, DH diodes and MQW diodes, usually PIN. Regarding intersubband structures for λo < 5 μm, I assign a low probability of creating a SiGeSn type II interband cascade laser (ICL). Also, an SiGeSn quantum cascade laser (QCL) at λo < 5 μm does not appear feasible. Although asymmetric strain is useful in device design, I favour lattice-matched and strain-balanced strategies. In order to illuminate the issues arising in LDs/SOAs/LEDs, let us look at the ‘schematic band structure’ of SiGeSn in figure 1, which illustrates the c.b. L and Γ curves but omits the X valley at higher energy. Figure 1a places SiGeSn LDs in context with the Ge telecom art by showing bands of the heavily N-doped Ge layer employed by the MIT group [28,29] in their experimental P+ Si/N+ Ge/N+ Si LD where the Ge had a small tensile strain [30]. By contrast, the SiGeSn layers in figure 1b, c are not doped and not strained. I see this as an advantage. The Sn content in figure 1b is lower than that in figure 1c; however, the figure 1b Sn concentration is large enough to give degeneracy of the Γ and L valleys, while the bandgap in figure 1c is ‘truly direct’ (EΓg < ELg ) albeit at a smaller bandgap energy. The intervalley Γ -L electron transfer in figure 1b is discussed below. Figure 2 presents calculated values of the bandgap energy and lattice parameter of unstrained Si1−x−y Gex Sny . These predictions are reprinted from [7]. Figure 2 provides a framework for our analysis of LDs/SOAs/LEDs, and these ternary diagrams cover all compositions xy. Figure 3, also reprinted from Section V of [7], gives a specific design sequence for MQW devices. Figure 3 ternary charts show xy compositions of lattice-matched wells-and-barriers having type-I band offsets in both v.b. and c.b. Figure 3a through e presents a step-by-step procedure to determine favourable alloys for building unstrained LDs, SOAs and LEDs (lattice matched to the r-VS layer) for the 2.3–5.0 μm λo region. The devices would be direct-gap SiGeSn/SiGeSn’ PIN MQWs and the Sn fraction would be in the 15–25% range. The procedure is a straightforward and credible approach to those devices. What are the relative merits of the DH and MQW devices? The answer involves the Auger recombination of injected electrons and holes, which amounts to an unwanted non-radiative ‘path’. From the results of Sun et al. [31,32], the intensity of the Auger process is lower in the MQW than in the DH, therefore the MQW is preferred for SiGeSn/SiGeSn’ LDs/SOAs/LEDs over the 1.55–5.0 μm λo range. Although the DH is indeed a viable approach in this λo range (both unstrained and strained-layer heterostructures) the DH infrared gain per unit of injectioncurrent-density is unfortunately smaller than that exhibited by MQWs—and that gain behaviour will influence the temperature of operation. So, the MQWs are ‘primary’ while the DHs are ‘supplemental’. For 1.55 ≤ λo ≤ 2.3 μm, the LD/SOA/LED situation is challenging because the active layer’s bandgap is indirect, and because the barrier’s band offsets are inadequate. To address these issues, I propose an altered strategy of (i) doping of the active regions N type— especially for 1.55 μm ≤ λo ≤ 1.80 μm—in order to fill the SiGeSn L valley with electrons up to a level near the Γ bandedge, as in the Ge DH LD, and (ii) allowing asymmetric strain as well

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8. Laser, LED and SOA proposals


The history of semiconductor mid-infrared technology shows that some active devices require cooling, the longer the λo , the stronger the need for cryogenics. In the present PIC/OEIC case, I think that those chips will perform well at room temperature for 1.55 μm ≤ λo ≤ 3.0 μm. A trade-off seems needed for room-temperature operation over the 3–5 μm region where reduced performance for emitters, amplifiers and detectors would have to be accepted in order to keep the chip uncooled.

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Figure 1. Simplified band diagram of lasing material: (a) N-doped tensile Ge, (b) unstrained SiGeSn with approximately 5% Sn, (c) unstrained SiGeSn with approximately 10% Sn. (Online version in colour.)

as lattice mismatch, which are obtained (for example) by choosing relaxed ‘wide bandgap’ Ge barriers that are lattice-mismatched to the SiGeSn wells. Such barriers produce the desired band discontinuities. In this mismatch example, ‘thin’ wells become compressively strained when grown commensurately on Ge. Alternatively, each SiGeSn layer can become strain relieved by adjusting its thickness and composition. This strain-relaxed strategy seems to be supported by the theoretical DH laser analysis of Dutt et al. [33], who considered an ‘unstrained’ N-doped GeSn layer sandwiched between P-Si and N-Si barriers. Taking into account Auger and free carrier absorption, they found ‘reasonable’ laser thresholds for various Sn fractions up to 10%. Now I shall give concrete proposals for 1.8–2.3 μm devices. At λo = 1.8 μm, for example, the emphasis shifts to the active SiSn alloys (figure 2f ), and here I turn to table III of MSI, which lists some lattice-matched indirect materials. Taking one pair of those alloys, the unstrained 1.76 μm MQW LD would have undoped Si0.56 Sn0.44 wells (EΓg = 0.706 eV, ELg = 0.707 eV) and Si0.58 Sn0.42 barriers (EΓg = 0.789 eV, ELg = 0.752 eV) both with an approximately 5.92 Å lattice. The issues here

are: (i) reduced gain because EΓg = ELg , (ii) small type-1 alignment, and (iii) a high-Sn fraction, which is a problem for present epitaxy. For 1.9–2.1 μm LD examples, the QW Sn concentration in the above LD increases to 46–48% and the wells become direct. For 2.1–2.3 μm LD examples, I turn to the 2.3 μm unstrained, direct-gap Ge0.9 Sn0.1 /Si0.10 Ge0 .75 Sn0.15 design offered by Sun, Soref and Cheng [32]. I would modify that structure for shorter-wave 2.2 μm lasing by reducing slightly the Sn concentration in both the undoped QWs and barriers, which unavoidably decreases the desired ELg − EΓg separation. Wall-plug efficiency is often a metric for LEDs and in the DH and MQW LEDs described in this section, I expect the efficiency to improve from low to moderate to high as λo is increased from 1.55 to 2.3 to 5.0 μm. Similarly, for the present DH and MQW SOAs outlined here, a related low-to-high progression in gain per unit length is expected for the same λo increase. Overall, the 1.55–2.3 μm region is characterized as ‘difficult’ for LD/SOA/LED creation. However, for both the ‘difficult’ 1.55–2.3 μm and the ‘easy’ 2.3–5.0 μm regimes, I feel that the research community should make a serious attempt, backed by adequate resources, to actualize these LDs/SOAs/LEDs. If that device work is not undertaken, we shall never know feasibility, let alone performance and cost. Those of us advocating group IV need to have our intuitions supported by experimental facts. I have often wondered whether an ultrafast SiGeSn LED could serve in lieu of an LD as a practical, on-chip wavelength-division multiplexed (WDM) light source in chip-to-chip, intrachip and short-haul-cable Z-band optical communications. The SiGeSn LED would be a DH or MQW and it would be embedded in the point-defect cavity region of a one-dimensional

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Figure 3. Ternary composition diagrams of unstrained SiGeSn/SiGeSn’ MQWs reprinted with permission from the Journal of Applied Physics. Equi-energy contours are shown: (a) Sn content of well necessary for the chosen Si content and EgΓ , (b) Si and Sn contents in the barrier necessary for lattice matching with the well material for a range of its EgΓ , (c) direct bandgap of the barrier material, (d) band discontinuities at v.b. and c.b.Γ for the chosen well and barrier materials, (e) spacing between the Γ valley in the well and the lowest indirect valley.

9. Photodetector possibilities What are the physical mechanisms available for group IV MIR sensing? The list is voluminous and the following are some representative device mechanisms: band-to-band PIN homojunction diodes [35], avalanche PDs [35], quantum-dot photodetectors [36], impurityand bulk-photoconductors [37,38], silicon/silicide Schottky-barrier diodes [39] metal/Ge/metal Schottky-enhanced diodes [40], microbolometers [41], defect-enhanced-Si PDs [42] (extendable, I think, to defect-mediated Ge PDs), superlattice diodes [43] valence-intersubband diodes [44] and conduction-intersubband diodes. Deliberately, I shall narrow my focus here to heterostructure photodetectors, a choice for which the requirements on band offsets and ‘directness’ are less stringent than they are for LDs. Looking at figure 2, there are many direct and ‘nearly direct’

.........................................................

0.5

(b)


0.20 0.25 0.30 0.35 0.40

Edir g (eV) =

Si, Sn fraction in the barrier

(a)


Electro-optical is a term that includes electro-refraction and electro-absorption. In a 2 × 2 switch, the EO mechanism is usually the same as in a 1 × 1 modulator. There are several excellent waveguided EO modulator-and-switch possibilities for 1.55–5.00 μm in SiGeSn heterodevices. First, the fast Franz–Keldysh field effect (FKE) in SiGeSn is optimized at a target wavelength (the wavelength at which peak-modulation occurs is chosen by selecting the alloy’s composition). It is interesting that the alloy can be ‘slightly indirect’ and yet function very well near the direct bandgap wavelength (the figure of merit peaks at a photon energy around 40 meV below the direct-gap energy). The GeSn FKE theory is presented in Soref et al. [45], but the FKE in SiGeSn generally needs confirming experiments. Second, the FKE is the bulk version of the quantum confined Stark effect (QCSE). In the last few years, most if not all publications on the Si-based QCSE feature Ge QWs with SiGe barriers and an SiGe VS buffer-on-Si. The most recent papers [46] focus on a strain-balanced 1550 nm QCSE in which the buffer is r- Si0.10 Ge0.90 on Si, while the QWs are 14 nm c-Ge, the barriers are ‘highly tensile’ Si0.15 Ge0.85 , and the λo of 1550 nm is truly an upper limit for SiGe/Ge. Although this system has merit, I think that QCSE systems should be expanded to the SiGeSn compositions, thereby enabling QCSE at 1550–5000 nm λo in unstrained (or strain balanced) MQWs. The MSI paper points out SiGeSn reverse-biased PIN unstrained MQW systems for this purpose. Independently, the James S. Harris group at Stanford [1] conceived of a GeSn version. Dr Y. Huo is a member of the Harris group, and in his thesis [47] he indicates (fig. 5.2) that a strain-balanced QCSE MQW with c-GeSn wells and t-SiGeSn claddings on r-SiGeSn buffered Si is ‘in progress.’ As a more specific example, I propose here an unstrained PIN MQW QCSE modulator for the 1900 nm region. I would employ two matched alloys cited in MSI table III; the indirect wells would be Si0.45 Ge0.20 Sn0.35 (EΓg = 0.695 eV, ELg = 0.623 eV) and the indirect barriers would be

Si0.61 Sn0.39 (EΓg = 0.923 eV, ELg = 0.824 eV) both lattice matched to the 5.878 Å VS; making this a high-Sn proposal. It is important to note that the QCSE devices are inherently broadband [48]. This means that QCSE devices provide low-energy modulation over a much wider information passband than that in resonant microdisk modulators. For broad-spectrum applications, I shall also suggest an end-coupled, ultrafast, broadband, electro-optical modulator that employs a hybrid photonic-plasmonic channel-waveguide mode. I am recommending that the 1310 nm Si/ITO/SiO2 /Au device of Sorger et al. [49] should be scaled up in waveguide-cross section for optimum modulation at any wavelength within the 1600–3600 nm range, and that the N-doped-Si modulator body can be changed to N-SiGeSn if wanted. The MSI paper points out that a variety of slightly indirect SiGeSn waveguided components are useful in the hν < Eg(indirect) transparency range, and that the SiGeSn free carrier plasma effects (FCEs) are generally very strong over 1550–5000 nm with strength depending inversely upon the bandgap. In that same MIR range, the SiGeSn nonlinear optical effects are also very strong with χ (3) ∼ 1/Eg .

11. WDM transceiver chips for ultrafast 2 μm communications The two projects launched in this area are listed in [6] and a European team has demonstrated error-free 8 Gb s−1 data transmission in one (of many) wavelength channel near 2008 nm [50]. As group IV enthusiasts, our objective is to demonstrate an Si-based factory-made all-group

.........................................................

10. Electro-optical modulators and switches

10


SiGeSn actives for efficient ‘sensing’ over 1.55 ≤ λo ≤ 5.0 μm (the peak-response wavelength is ‘tuned’ by the choice of composition). Figure 2 simulations, together with 1.55–1.8 μm experimental progress, makes me hopeful, and I feel that the prospects are excellent for detection out to 5 μm. I expect that further research will reveal photodetectors that are fully competitive with their III–V counterparts in the MIR. Perhaps this statement is too strong for the particular case of 1.5–1.8 μm sensing because some III–Vs are ‘more direct’ there.


SiGeSn-on-Si will, I think, join Ge-on-Si as a viable low-loss MIR channel waveguide on bulk silicon. More generally, on the journey to construct group IV MIR PICs, a large number of diverse passive components are going to be called upon: low-loss waveguides, filters, directional couplers, arrayed waveguide gratings, surface gratings, photonic crystals, resonators, add/drop multiplexers, multimode interference couplers, polarization converters, isolators, bends, tapers, splitters and more. I feel that the future prospects for all of these SiGeSn-related components are excellent over the entire 1.55–5.00 μm range. In addition, the strong third-order nonlinear coefficients of SiGeSn will prove useful in the mid-infrared. Surveying the GeSn and SiGeSn material requirements for the various passives, it should be noted that an indirect bandgap is acceptable in most (if not all) cases. For active, electrically biased components, a direct bandgap is desired in some cases. We certainly prefer directness in the category of SiGeSn-related LDs/SOAs/LEDs; however, for all of the other actives (including photodetectors, tuneable filters, WDM cross connects, reconfigurable add/drop multiplexers, electro-optical modulators and electro-optical-routing switches) directness is not essential, and I believe that this large group of actives, similar to the passives, has outstanding prospects for practical development in the 1.55–5.0 μm range. Regarding LDs, LEDs, SOAs, I said above that (i) the hybrid integration of III–V LDs/LEDs/ SOAs on group IV will likely be a highly practical technique within the 1.55–5.0 μm λo range for both interband and cascade devices, (ii) the creation of practical monolithic SiGeSn hetero LDs/LEDs/SOAs in the 1.55–2.30 μm range is going to be challenging but feasible, and (iii) the monolithic fabrication of 2.3–5.0 μm direct-gap SiGeSn/SiGeSn’ LDs/LEDs/SOAs appears straightforward and practical. The ‘reward’ of attaining PDs and LDs motivates research on high-Sn-fraction materials near the binary SiSn composition line in the ternary diagram. More generally, the MSI ternary theory must be put to the test over many compositions, beginning with the GeSn binary to determine experimentally the Sn content (x) at which GeSn’s indirect-to-direct transition occurs (EΓg crosses ELg ) in the unstrained, disordered alloy. For example, MSI puts the crossover at x = 10%, whereas the theory of Yin et al. [51] places the transition at x = 6.3%, where EΓg = 0.65 eV. Looking to the future, it is difficult to predict whether mid-infrared group IV (or ‘IV–IV’) PICs and OEICs will develop more rapidly than their III–V counterparts. Development decisions are investment decisions based upon factors that go beyond the basic materials science. When comparing IV–IV and III–V technologies, what I can do is look at the fundamental materials parameters in order to arrive at an informed opinion. The parameters that should be considered include the index contrast between the waveguide core and its cladding, the infrared matrix elements and absorption coefficients for band-to-band transitions, and the effective masses as well as mobilities of both electrons and holes. As the IV–IV index is well above 4.0, the contrast n > 2.0 is surely competitive with that of the III–Vs. Also, the MIR absorption of the GeSn/Ge MQW is competitive according to [13]. Gupta et al. [1] find GeSn electron mobilities higher than those of Ge. Estimates of m∗e and m∗h in GeSn [1,22] reveal favourable behaviour. Generally speaking, theory predicts a IV–IV device-performance outlook similar to that of III–Vs

.........................................................

12. Summary

11


IV dense-WDM transceiver chip, PIC or OEIC, for this low-loss HC-PBG-fibre system. Plan A is to integrate SiGeSn LDs on-chip together with other monolithic transmitter and receiver components. Plan B is to hybrid-integrate III–V LDs on-chip or to put all 2 μm sources off-chip. Both A and B chips contain a set of integrated, ultrafast, WDM waveguided components. Both chips would be significant in the communications world where B is nearly as important as A. I advocate the construction of these chips as a showcase for SiGeSn technology generally and for FKE, QCSE and FCE switches/modulators particularly. I am confident that the hybrid-LD Z-band PIC could be developed successfully.


The materials Si, Ge and SiGeSn have tremendous untapped potential for practical application in Si-based PICs and OEICs operating in the 1550–5000 nm wavelength range. The active and passive waveguided components in these integrated ‘circuit’ chips also have fine possibilities for cost-effective high-volume manufacture in modern 130 and 65 nm silicon foundry nodes. The ternary SiGeSn composition diagram contains domains that are ripe for experimental exploration, including materials using up to 45% Sn content. The active devices are generally PIN band-toband SiGeSn/SiGeSn’ heterostructure diodes, for example MQW diodes. A caveat is that the heterodevice often requires a local-area VS under the device, a relaxed 5.7–5.9 Å SiGeSn buffer layer that contacts the bulk Si or SOI wafer. In addition to its uses in SiGeSn devices, this VS is automatically a template for lattice-matched growth of MIR InGaAsP devices on Si. A research agenda for specific devices has been given. The future prospects are excellent for creating a complete suite of group IV, high-performance, monolithically integrated MIR components—essentially all conceivable components except LDs in the 1.55–2.30 μm range (seen as problematic). However, the LDs appear feasible for 2.3–5.0 μm uses. Even without onchip group IV LDs, these monolithic PICs and OEICs are valuable contributors to 1.55–5.0 μm applications. The bonding of band-to-band and intersubband III–V MIR LDs to those chips is a practical strategy. Funding statement. The author thanks the US Air Force Office of Scientific Research for sponsoring this work under grant no. FA9550-10-1-0417.

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13. Conclusion

12


for perfect MIR materials. However, the development of SiGeSn requires more attention paid to the real-world issues of strain, defect formation and atomic segregation. With this background, let me estimate the ‘inherent’ performance of PIC/OEIC chips in three categories. The first category is the ‘source-less chip’ in which the LDs/LEDs/SOAs are off-chip and the remainder of the optical circuit is monolithic. The second kind is the fully monolithic chip that contains ‘all conceivable’ components. The third is the hybrid-source chip, a monolithic IC in which the necessary III–V LDs/LEDs/SOAs are bonded on the chip. (Because I am spotlighting group IV competence, I have excluded from consideration here the InP-membrane PIC-on-Si that blurs the lines of demarcation between III–V and IV–IV). The III–Vs sources will include MIR ICLs and QCLs. Let me then compare the III–V and IV–IV versions of these three chips in two wavelength bands: 1.55–2.3 μm (region 1) and 2.3–5.0 μm (region 2). My estimate is that the IV–IV sourceless chip will perform just as well as the III–V sourceless chip over both regions 1 and 2 (and the IV–IV might be more economical as per my foundry discussions). In region 1, we are probably obliged to compare the hybrid-source IV–IV monolithic with the all-monolithic III–V, owing to the uncertainties of making IV–IV sources/amplifiers in that region. Even so, I project equivalent performance for the IV–IV and III–V technologies. Within region 2, I think we can happily pit the IV–IV monolithic chip against the monolithic III–V chip and arrive once again at the judgement that both technologies will produce similar, practical photonic and opto-electronic results. In summary, I am optimistic about the value and contribution of group IV.


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