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T. Uemura,* T. Matsumoto, K. Miyake, M. Uno, S. Ohnishi, T. Kato, M. Katayama, S. Shinamura, M. Hamada, M.-J. Kang, K. Takimiya, C. Mitsui, T. Okamoto, and J. Takeya* Organic field-effect transistors (OFETs) have been intensively studied because of their promising potential for achieving an advanced information society employing flexible, lightweight, and large-area electronics. Specifically, rollable information displays, flexible smart sensors, and plastic logic circuits are practicable candidates for the application of OFETs.[1] In these electronic devices, air-stable and high-speed operating OFETs, which are directly associated with device reliability and response speed, are required. In the past few years, because of the remarkable progress in the material design of organic semiconductors, the mobility of air-stable OFETs are already over 10 cm2/Vs and organic circuits operating in MHz range have Dr. T. Uemura, Dr. M. Uno, Dr. C. Mitsui, Prof. T. Okamoto, Prof. J. Takeya Department of Advanced Materials Science Graduate School of Frontier Sciences The University of Tokyo, 5–1–5 Kashiwanoha, Kashiwa, Chiba, 277–8561, Japan E-mail: [email protected]; [email protected] T. Matsumoto TOPPAN FORMS CO., LTD. 1–7–3 Higashi Shimbashi; Minato-ku Tokyo, 105–8311, Japan K. Miyake Graduate School of Engineering Osaka University 1–1 Yamadaoka, Suita, Osaka, 565–0871, Japan Dr. M. Uno Technology Research Institute of Osaka Prefecture, 2–7–1 Ayumino, Izumi, Osaka, 594–1157, Japan S. Ohnishi, T. Kato, Dr. M. Katayama Research Laboratories, DENSO CORPORATION 500–1 Minamiyama Komenoki-cho Nisshin, Aichi, 470–0111, Japan S. Shinamura, M. Hamada R&D Planning Division, Research & Development Group Nippon Kayaku Co. Ltd., 3–31–12 Shimo; Kita-ku, Tokyo, 115–8588, Japan M.-J. Kang, Prof. K. Takimiya Department of Applied Chemistry Graduate School of Engineering Hiroshima University 1–4–1 Kagamiyama; Higashi-Hiroshima, Hiroshima, 739–8527, Japan Prof. K. Takimiya RIKEN Center for Emergent Matter Science (CEMS), 2–1 Hirosawa, Wako, Saitama, 351–0198, Japan

DOI: 10.1002/adma.201304976

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Split-Gate Organic Field-Effect Transistors for High-Speed Operation

been reported in several studies.[2] Although high mobility semiconductors are essentially important materials for constructing high-speed switching transistors, the intrinsic performance of the materials could not be fully utilized in short-channel transistors, while these structures are highly attractive for highspeed operation and high-scale integration. This is because the contact resistances (Rc) between the electrodes and channel region are considerably large compared to the channel resistances (Rch) in short channel transistors with a channel length of a few microns. For this reason, reducing Rc is still a challenging issue and, therefore, a number of doping techniques and surface modifications of contact metals have been investigated, which are achieving modestly small Rc.[3] In this study, we have developed a sophisticated design of split-gate OFETs for high-speed operation. In the split-gate OFETs, Rc can be reduced and kept constant by the split-gate voltage and a parasitic capacitance contributes to the input capacitance of transistor can be minimized using a self-aligned photolithography. Due to both advantages, the split-gate OFETs operate at high speed. The concept of reduced Rc with the use of the split-gate structure originated in the study of lowtemperature physics on MOSFETs,[4] and the concept has been successfully applied to OFETs in recent reports.[5] In the splitgate devices developed in this study, the split gates are buried just below the top-contact source and drain electrodes, as illustrated in Figures 1a and b. In this device, carrier density near the contact region can be varied by the applied split-gate voltages (Vsplit). Generally, in conventional planar transistors, both Rc and Rch are reduced simultaneously while increasing main gate voltages (VG).[6] In other words, the advantage of the splitgate OFETs is most pronounced in the low VG region because the small and constant value of Rc can be extracted by applying high DC Vsplit voltages. In that sense, split-gate OFETs are highly appealing for high-speed and low-power CMOS circuits, because the transconductance in the lower VG region is critical for the operation speed and power consumption of CMOS circuits. And it should be obvious that the split-gate structure is effective for both P- and N-type OFETs.[7] In addition to the advantage of the reduced and constant value of Rc, the split-gate structure achieves the minimized parasitic capacitance without increasing the Rc. Figure 1c shows the cross sectional image of a conventional top-contact and bottom-gate configuration. In such a planar structure, the unity-gain cutoff frequency (fT), which is an upper limit of operating frequency for transistor circuits, is expressed in the linear regime as the following equation:

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Figure 1. (a) Schematic illustration of the split-gate transistors. The chemical structure of 2,9-di-decyldinaphtho[2,3-b:2′,3′-f ]thieno[3,2-b]thiophene (C10-DNTT) is also shown. (b) Conceptual cross-sectional view of the split-gate transistors. (c) and (d) Schematic cross sections of a conventional top-contact and bottom-gate transistor (c) and the split-gate transistor (d) used in this study.

fT =

μVD 2π L (L + 2 ⋅ ΔL )

(1)

fT is defined as the frequency when the output drain current is equal to the input gate current and, therefore, fT is proportional to effective mobility (µ) and drain voltage (VD). And according to Equation (1), the short channel length (L) and the small overlap length (ΔL) between the gate and source/drain electrodes are preferable for high-speed operation, which corresponds to minimize the input capacitance of the switching transistor. However, the disadvantage of the smaller ΔL is that an aggressively reduced ΔL increases Rc because it limits the charge injection area in conventional planar transistors.[8] On the other hand, in split-gate OFETs, since the overlap region between the split-gate and source/drain electrodes does not contribute to input capacitance, the charge injection area can be widely ensured by the split-gate electrodes. As shown in Figure 1(d), when the ideal source/drain structures can be fabricated, only the overlaps between main-gate and split-gate electrodes (ΔLsplit) contribute to the parasitic capacitance. In this device structure, the most important thing is that the ΔLsplit can be minimized without increasing Rc. For this reason, in this study, we fabricated the split-gate electrodes using self-aligned photolithography for minimizing the ΔLsplit to submicron length. As a result of both the reduced Rc and minimized ΔLsplit, in this study, the splitgate OFETs achieved a high cutoff frequency of up to 20 MHz in a vacuum-evaporated device and 10 MHz in a solution-processed device. Furthermore, the gate-voltage dependence of the performance was small and the devices operated stably in air using high-mobility and air-stable materials of 2,9-didecyldinaphtho[2,3-b:2′,3′-f ]thieno[3,2-b]thiophene (C10-DNTT).[9] 2984

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electrodes with

Figure 2a shows the fabrication processes of a split-gate OFET. First, on a glass substrate, the main gate of a Cr/Au/Cr layer was patterned by a conventional liftoff process and 200-nm thick alumina was deposited as a first insulator by atomic layer deposition (ALD). The split-gate electrodes were patterned using self-aligned photolithography, where the main gate electrode is utilized as a photomask in the process of resist exposure from the backside of the glass substrate. Figure 2b is a scanning transmission electron microscope image representing a cross sectional structure near the main gate and split gate electrodes. As seen in Figure 2b, a small overlap region (ΔLsplit) still remains, which is mainly caused by overexposure of a photo resist and/or the anti-tapered shape of the resist. The typical length of (ΔLsplit) was 500 nm. After the second insulator of 100-nm thick alumina was deposited by ALD, the semiconductor layer of C10-DNTT was deposited by a vacuum evaporation or solution-crystallized method.[10] If the split-gate electrodes are transparent electrodes such as ITO, the top contact electrodes could be fabricated using self-aligned photolithography. In this study, however, we deposited gold a 1-nm thick interface doping material through

Figure 2. (a) Processing steps for the fabrication of the split-gate transistors. (b) Detailed scanning transmission electron microscope image of a split gate region.

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a shadow mask in order to further reduce Rc, where we used F6TNAP as a doping material.[11] Figures 3a and b are optical microscope images of a vacuumdeposited and a solution-crystallized C10-DNTT split-gate transistor, respectively. As seen in Figure 3b, there are a number of cracks in the crystal film, which are produced during the film fabrication process as we mentioned in our previous report about the solution-crystallized method.[10] However, since the direction of the cracks has been controlled to be parallel to the current flow by optimizing the direction of crystalline growth, the influence on device performance has been minimized. Figure 3c shows the typical transfer characteristic of a split-gate transistor with vacuum-evaporated C10-DNTT thin film. The device shows small hysteresis, moderate mobility of 0.4 cm2/Vs, and a good on/off ratio of 107, indicating that the channel region is correctly controlled by the main gate electrode. These measurements were performed with the application of Vsplit of −20 V, which corresponds to the carrier density of 9 × 1012 cm−2

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Figure 3. (a) and (b) Microscopic optical images of split-gate transistors. A typical vacuum-evaporated device (a) and a solution-processed device (b) are shown. (c) and (d) Transfer and output characteristics of vacuumevaporated split-gate transistor with applied split-gate voltages of −20 V.

beneath the source electrode. Although the carrier density induced by the split gate is at least three times greater than that of channel region, moderate nonlinear behavior is still observed in the output characteristics in Figure 3d. To clarify the effect of split-gate electrodes quantitatively, we evaluated several transfer characteristics with different Vsplit in Figure 4. As shown in Figure 4a, the drain current increases with increasing Vsplit with the same off-current level. It appears from this result that the split gate successfully reduces Rc without influence to the main channel. In Figure 4b, channelwidth-normalized total resistance (Rtot) with different Vsplit are shown, where Rtot is the sum of Rc and Rch. More precisely, Rc consists of the resistance at the interface of metal and semiconductor (Rint) and the resistance of the bulk region between the metal-semiconductor interface and the bottom channel region (Rbulk). In Figure 4b, the observation that the total resistance decreases for increasingly negative split-gate voltages is similar to the gate-voltage dependence of Rc in conventional planar OFETs; the minimum value of Rtot was 1.2 kΩ·cm at Vsplit = −20 V. Since Rtot includes the resistance of the pinch-off region, the intrinsic Rtot without the pinch-off region can be roughly estimated at 600 Ω·cm by extrapolating the slope of the linear region in the output characteristics. In addition, we can assume that the intrinsic mobility of vacuum-deposited C10-DNTT on alumina substrate is 3.8 cm2/Vs from our previous report.[12] Therefore, Rch can be calculated to be 120 Ω·cm at a channel length of 2.5 µm. As a result, the remaining 480 Ω·cm can be assigned to Rc. Consequently, under these estimates, we found that the moderate mobility of 0.4 cm2/Vs is plausible.[13] Since the value of Rc = 480 Ω·cm is still larger than that of the other reports,[11,14] we can reduce the Rc further by optimizing the process conditions. Figure 4c shows mobility as a function of VG with different Vsplit, where the mobility considerably improves with increasing Vsplit as a result of the reduction of Rc. The mobility improved from 2.5 × 10−2 cm2/Vs at Vsplit = 0 V to 0.4 cm2/Vs at Vsplit = –20 V. It should be noted that the maximum point of mobility indicated by the arrows are shifted to the lower VG region with the application of high Vsplit. This result demonstrates that the split-gate structure is highly attractive for improving performance at the lower gate voltage region.

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Figure 4. (a) Transfer characteristics of vacuum-evaporated split-gate transistor with different split-gate bias conditions. (b) Width-normalized total channel resistance as a function of applied split-gate voltage. (c) Gate voltage dependence of mobility under different split-gate bias conditions.

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Figure 5. Input gate current and output drain current as a function of operating frequency with different gate voltages. Typical (a) and best (c) characteristics of vacuum-evaporated C10-DNTT thin-film devices with split-gate structures. The inset figure in (a) shows the measurement result of the h21 parameter using the network analyzer. Typical (b) and best (d) characteristics of solution-crystallized C10-DNTT devices with split-gate structures. In these devices, the distance between the source and drain electrode was almost same (∼2.5 µm). However, only the distance between the split gate electrodes was different, which depend on the length of gate electrodes and correspond to the effective channel length in the split-gate transistors. In the devices of (a) and (b), the distances were ~2.5 μm. And in the devices of (c) and (d), the distance was 1.2 μm and 1.7 μm, respectively.

Figures 5a and b show the typical measurement results of cutoff frequencies on a vacuum-deposited device and a solution-processed device, respectively. In these measurements, the input current (IIN) to the input capacitance and the output current (IOUT) through the channel have been obtained simultaneously so that we can determine the unity-gain frequency fT.[2a] As seen in Figure 5a, fT of the vacuum-deposited device was 10 MHz for VG = −20 V, which can also be confirmed using a network analyzer (inset Figure 5a). The value is reasonable because the theoretical value was estimated to be 13 MHz.[15] In Figure 5a, it should be emphasized that fT did not change even at the lower VG of −5 V owing to the constant Rc as a function of VG. In a similar way, in Figure 5b, fT of the solution-processed device was 4 MHz for both VG = −20 and 0 V, where the threshold voltage was +8 V. Compared to the vacuum-deposited devices, we had expected higher fT because the mobility of the solution-crystallized C10-DNTT on alumina is over 10 cm2/Vs.[10b] In fact, on the contrary, the measured values were smaller than that of the vacuum-deposited devices.

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One reason for the decreased performance is that Rc is higher than that of the vacuum-deposited devices due to the difference of Rbulk. In the vacuum-deposited device, we adjusted the thickness to be 30 nm. In contrast, at present, we cannot precisely control the thickness of solution-crystallized film. Therefore, the device partly includes thicker (about 50 nm) film regions. This is the reason for the large Rc in the solution-crystallized devices. As for the other reasons, it also could be possible that the rough surface near the overlap region, as seen in Figure 2b, damages the film. Sometimes, cracks form on the crystalline film perpendicular to the direction of current flow. These cracks can be observed under an optical microscope. Finally, in Figures 5c and d, the best values of fT measured in this study are shown. In these devices, the lengths of the main gates were aggressively reduced. As a result, the distance between the split-gate electrodes were reduced to be 1.2 and 1.7 µm for the vacuum-evaporated device and solutioncrystallized device, respectively. Due to the technical limitations of mask alignment, there are small misalignments between

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Experimental Section The high mobility material of C10-DNTT was supplied by Nippon Kayaku Co. The split-gate structures were fabricated on EAGLE XGR (Corning Inc.) glass substrates. The main gate was fabricated by the conventional liftoff process using TLOR resist (Tokyo Ohka Kogyo Co., Ltd.), where the typical electrode thickness was 7/50/7 nm for Cr/Au/Cr, respectively. The thickness was designed to adequately minimize wiring delay and successfully used for the following self-aligned photolithography process. And we designed the split-gate devices with a typical channel width of 3 mm so that the gate capacitance and output current are large enough to ensure adequate accuracy for measuring the results. The alumina layers were deposited by ALD at 150 °C immediately after UV/O3 cleaning. The dielectric constant of alumina was typically 8.3. The split gate was fabricated by the liftoff process using a self-aligned photolithography process. The thickness was typically 5/20/5 nm with Cr/Au/Cr. After the second deposition of an alumina layer, the surface was treated with self-assembled monolayers (SAMs). In the thermalevaporated and solution-processed devices, n-tetradecylphosphonic acid and 3-phenylpropylphosphonic acid were used for the SAM treatments, respectively. The SAM treatments were performed in a 2-propanol solution at room temperature overnight. After the proper SAM treatments, the substrate temperature was kept at 80 °C during the vacuum evaporation of C10-DNTT. The solution-crystallized films were fabricated from tetralin solution using our original “Edge-cast method,” where the substrate temperature was kept at 83 °C. As for the topcontact fabrication, an original shadow mask was fabricated using a very thin (3 µm diameter) tungsten wire (W-461030, The Nilaco Corp.) and the mask aliment was performed using a homemade alignment system. The transistor characterization was performed using a semiconductor parameter analyzer (Keithley 4200SCS) in air. In the measurements of unity-gain cutoff frequencies, the same experimental setup as reported by Kitamura et al. was used.[2a] The offset voltage and small signal (1 V peak-to-peak) were applied using a bias tee (ZFBT-4R2GW+, Mini Circuits). The h21 parameter was obtained using 2-port S-parameter measurement on the network analyzer (E5061B, Agilent) with RF probes (ACP40, Cascade Microtech). The h21 parameter represents the ratio of the output current to the input current. In this way, the value of the

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current gain, which is given by 20log|h21|, becomes 0 at the unity-gain cutoff frequency.

Acknowledgements We acknowledge the New Energy and Industrial Technology Developing Organization (NEDO), the Japan Science and Technology Agency (JST), the JSPS Strategic Young Researcher Overseas Visits Program for Accelerating Brain Circulation, and the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), Japan for financial support.

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the channel region and the top contact metals. Basically, the distance between the source and drain electrodes are about 2.5 µm; however some areas of source or drain electrodes covers the channel region due to the misalignments. In such devices, Rc varies with the applied VG. However, in fact, we can extract very high fT due to the short channel benefits with large transconductance at the specific voltage conditions. As shown in Figure 5c and d, the value of fT was 20 MHz in a vacuumdeposited device; 10 MHz was obtained in a solution-crystallized device. The 10 MHz operation obtained in the solutioncrystallized device is the fastest speed reported so far among solution-processed devices. In conclusion, in this study, we demonstrated the high-speed and air-stable operation of OFETs with split-gate structures. In the split-gate devices with C10-DNTT semiconductors, the source-gate and drain-gate overlap lengths were minimized by self-aligned photolithography without increasing contact resistances. As a result of the benefit of the short channel with minimized overlap length and reduced contact resistance, unity-gain cutoff frequencies up to 20 and 10 MHz were obtained in vacuum-evaporated devices and solution-processed devices, respectively. To our knowledge, this is the first time that operation at over 10 MHz has been achieved in solution-processed organic transistors.

Received: October 6, 2013 Revised: December 13, 2013 Published online: January 25, 2014

[1] a) M. Noda, N. Kobayashi, M. Katsuhara, A. Yumoto, S. Ushikura, R. Yasuda, N. Hirai, G. Yukawa, I. Yagi, K. Nomoto, T. Urabe, J. Soc. Inf. Display. 2011, 19, 316; b) S. Steudel, K. Myny, S. Schols, P. Vicca, S. Smout, A. Tripathi, B. van der Putten, J.-L. van der Steen, M. van Neer, F. Schütze, O. R. Hild, E. van Veenendaal, P. van Lieshout, M. van Mil, J. Genoe, G. Gelinck, P. Heremans, Org. Electron. 2012, 13, 1729; c) G. Schwartz, B. C.-K. Tee, J. Mei, A. L. Appleton, D. H. Kim, H. Wang, Z. Bao, Nat. Commun. 2013, 4, 1859; d) T. Sekitani, T. Someya, Adv. Mater. 2010, 22, 2228; e) K. Myny, S. Steudel, S. Smout, P. Vicca, F. Furthner, B. van der Putten, A. K. Tripathi, G. H. Gelinck, J. Genoe, W. Dehaene, P. Heremans, Org. Electron. 2010, 11, 1176. [2] a) M. Kitamura, Y. Arakawa, Appl. Phys. Lett. 2009, 95, 023503; b) M. Uno, T. Uemura, Y. Kanaoka, Z. Chen, A. Facchetti, J. Takeya, Org. Electron. 2013, 14, 1656; c) U. Zschieschang, R. Hofmockel, R. Rödel, U. Kraft, M.-J. Kang, K. Takimiya, T. Zaki, F. Letzkus, J. Butschke, H. Richter, J.-N. Burghartz, H. Klauk, Org. Electron. 2013, 14, 1516; d) J. Smith, R. Hamilton, M. Heeney, D. M. de Leeuw, E. Cantatore, J. E. Anthony, I. McCulloch, D. D. C. Bradley, T. D. Anthopoulos, Appl. Phys. Lett. 2008, 93, 253301. [3] a) P. Darmawan, T. Minari, Y. Xu, S. Li, H. Song, M. Chan, K. Tsukagoshi, Adv. Funct. Mater. 2012, 22, 4577; b) B. Stadlober, U. Haas, H. Gold, A. Haase, G. Jakopic, G. Leising, N. Koch, S. Rentenberger, E. Zojer, Adv. Funct. Mater. 2007, 17, 2687; c) M. Kitamura, S. Aomori, J. H. Na, Y. Arakawa, Appl. Phys. Lett. 2008, 93, 033313. [4] J. Jaroszyn´ski, D. Popovic´, T. M. Klapwijk, Phys. Rev. Lett. 2002, 89, 276401. [5] K. Nakayama, T. Uemura, M. Uno, J. Takeya, Appl. Phys. Lett. 2009, 95, 113308. [6] M. Marinkovic, D. Belaineh, V. Wagner, D. Knipp, Adv. Mater. 2012, 24, 4005. [7] K. Nakayama, K. Hara, Y. Tominari, M. Yamagishi, J. Takeya, Appl. Phys. Lett. 2008, 93, 153302. [8] F. Ante, D. Kälblein, T. Zaki, U. Zschieschang, K. Takimiya, M. Ikeda, T. Sekitani, T. Someya, J. N. Burghartz, K. Kern, H. Klauk, Small 2012, 8, 73. [9] M.-J. Kang, I. Doi, H. Mori, E. Miyazaki, K. Takimiya, M. Ikeda, H. Kuwabara, Adv. Mater. 2011, 23, 1222. [10] a) T. Uemura, Y. Hirose, M. Uno, K. Takimiya, J. Takeya, Appl. Phys. Exp. 2009, 2, 111501; b) K. Nakayama, Y. Hirose, J. Soeda, M. Yoshizumi, T. Uemura, M. Uno, W. Li, M. J. Kang, M. Yamagishi, Y. Okada, E. Miyazaki, Y. Nakazawa, A. Nakao, K. Takimiya, J. Takeya, Adv. Mater. 2011, 23, 1626.

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[11] T. Matsumoto, W. Ou-Yang, K. Miyake, T. Uemura, J. Takeya, Org. Electron. 2013, 14, 2590. [12] W. Ou-Yang, T. Uemura, K. Miyake, S. Onish, T. Kato, M. Katayama, M. Kang, K. Takimiya, M. Ikeda, H. Kuwabara, M. Hamada, J. Takeya, Appl. Phys. Lett. 2012, 101, 223304. [13] R. Hofmockel, U. Zschieschang, U. Kraft, R. Rödel, N. H. Hansenb, M. Stolte, F. Würthner, K. Takimiya, K. Kern, J. Pflaum, H. Klauk, Org. Electron. 2013, 14, 3213.

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[14] Effective mobility can be calculated from the following equation: µ = µintrinsic·Rch/(Rch + Rc). Using this equation, mobility is estimated to be 0.76 cm2/Vs. [15] In split-gate transistors, equation (1) should be modified. When the thickness of the first insulator is 200 nm and that of the second insulator is 100 nm, the equation can be modified as fT = µVD/ [2πL(L+3ΔLsplit)]. Here, ΔLsplit is the overlap length between the main gate and split gates as illustrated in Figure 1(d).

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Split-gate organic field-effect transistors for high-speed operation.

Split-gate organic field-effect transistors have been developed for high-speed operation. Owing to the combination of reduced contact resistance and m...
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