ARTICLES PUBLISHED ONLINE: 9 MARCH 2015 | DOI: 10.1038/NMAT4237
Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics Hanul Moon1,2†, Hyejeong Seong2,3†, Woo Cheol Shin1,2†, Won-Tae Park4, Mincheol Kim1,2, Seungwon Lee1,2, Jae Hoon Bong1,2, Yong-Young Noh4, Byung Jin Cho1,2*, Seunghyup Yoo1,2* and Sung Gap Im2,3* Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.
I
nsulating layers are an essential component enabling reliable operation of field-effect transistors (FETs), flash memory and capacitors in modern electronic systems1 . With the emergence of next-generation, ‘soft’ electronics relying on the mechanical flexibility of materials involved, the new generation of electronic devices requires insulating layers to work with unconventional substrates and newly emerging semiconductor materials2–5 . To this end, polymeric layers are being intensively investigated as new insulating layers6–8 . Owing to the relatively low dielectric constants (k) of most polymeric materials, however, ultrathin layers are required to achieve the high capacitance density (Ci ) essential for low-power operation. Unfortunately, it is challenging to reproducibly make pinhole-free polymeric films thinner than a few tens of nanometres over large areas6,7 . Further complications arise from incomplete removal of solvent residues and required solvent orthogonality with underlying layers in the case of solutionprocessed polymeric layers. As an alternative, molecularly thin selfassembled monolayers (SAMs) or ultrathin oxide layers grown by a low-temperature process (for example, anodized AlOx layers) could also be used as insulating layers in flexible devices9–11 . However, the surface-specific nature of SAMs and anodized oxides makes it difficult to extend their application across various device configurations and material sets, calling for the development of insulators that can provide a greater degree of freedom in designing the architecture and process flow for soft electronic devices. Here, we demonstrate poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) as a versatile
polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. We show that the iCVD process enables the formation of highly uniform, ultrathin films of pV3D3 with excellent insulating properties, owing to the advantageous characteristics of the iCVD process, including low process temperature, conformal surface growth and high purity. Consequently, iCVD pV3D3 layers are demonstrated as reliable polymeric insulating layers that are non-destructive and have electrical and mechanical characteristics suitable for soft electronic devices. iCVD is an all-dry vapour-phase technique, where vapourized monomers form polymeric films directly on the surface of a substrate. Inherited from conventional CVD processes, iCVD has a good scalability and compatibility with high-throughput manufacturing12 , can be set up mostly with standard, off-the-shelf parts, and operates at a moderate vacuum level in a mild temperature range13 . Polymeric films in iCVD are formed by the following mechanism: (i) introduction of vapourized monomers and initiators; (ii) thermal dissociation of initiators to form radicals on contact with heated filaments; (iii) physical adsorption of monomers onto cooled substrates; and (iv) free-radical polymerization of adsorbed monomers on the surface (Fig. 1a)14,15 . The surface-growing characteristics of the iCVD process enable the conformal coverage of polymeric films with a high degree of uniformity over a large area with virtually no surface or substrate limitations13 . Also, iCVD-grown polymer films generally have high chemical purity with no residues because the deposition process is inherently free of solvents and additives13 . Furthermore, the optimal substrate temperature (Tsub ) is near room
1 Department of Electrical Engineering, Korea Advanced Institute of Science and technology (KAIST), Daejeon 305-701, Republic of Korea. 2 Graphene Research Center, KI for Nanocentury, KAIST, Daejeon 305-701, Republic of Korea. 3 Department of Chemical and Biomolecular Engineering, KAIST, Daejeon 305-701, Republic of Korea. 4 Department of Energy and Materials Engineering, Dongguk University, Seoul 100-715, Republic of Korea. †These authors contributed equally to this work. *e-mail: [email protected]; [email protected]; [email protected]
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES a
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Figure 1 | pV3D3 polymer insulating layers produced by iCVD. a, Schematic of the iCVD process mechanism: (i) vapourized monomers and initiators are introduced, (ii) initiators are thermally dissociated into radicals by contact with filaments (red lines) heated at ∼200 ◦ C, which are positioned away from the substrate, (iii) then monomers and initiator radicals are adsorbed onto the surface of a cooled substrate (40 ◦ C), (iv) where they undergo free-radical polymerization to form pV3D3 thin films. b, Chemical structures of V3D3 monomer, initiator (tert-butyl peroxide; TBPO), and pV3D3 polymer. c, Eg of pV3D3 determined by EELS (left) and the energy band diagram of pV3D3 obtained from UPS and EELS data (right). Inset shows the zoomed-out EELS spectra of pV3D3 (blue) and SiO2 (black). d, Structure of an Al/pV3D3/Al MIM device (top left) and cross-sectional HRTEM images with dpV3D3 of 58 nm (top right) and 11 nm (bottom right). The zoomed-in TEM image of the 11-nm-thick pV3D3 layer is shown in bottom left. e, Cross-sectional scanning electron microscope (SEM) image of an Al/pV3D3(∼10 nm)/Al MIM device, and elemental analysis results by EDS. The graph shows an EDS line scan corresponding to the arrows in the cross-sectional SEM image (top left). The dashed red box indicates the area of pV3D3 layer. The remaining images show EDS 2D mapping results of Al, O, and Si, corresponding to the SEM image.
temperature for most iCVD polymers. Coupled with its solvent-free nature, the low Tsub of the iCVD process enables non-destructive deposition onto underlying device layers and substrates that are thermally and/or chemically sensitive13 . All these benefits make the iCVD-based polymers an ideal candidate for a versatile insulator that can cope with the various demands of emerging soft electronic devices. A variety of iCVD-based polymer layers were tested in a metal/insulator/metal (MIM) structure and exhibit excellent insulating properties with leakage current densities (Ji ) lower than 10−8 –10−9 A cm−2 (see Supplementary Fig. 1). In particular, pV3D3, polymerized from a monomer of 1,3,5-trimethyl-1,3,5trivinyl cyclotrisiloxane (V3D3; Fig. 1b for molecular structure; and Supplementary Fig. 2a,b, and Supplementary Table 1 for analytical data), has the potential to make compact thin films with good chemical stability owing to its high crosslinking density16,17 . In fact, its film morphology and thickness is shown to remain virtually unchanged after a 24-h soak in a highly solvating solvent such as acetone and toluene (see Supplementary Table 2 and Supplementary Fig. 3). Furthermore, pV3D3 exhibits a good thermal stability up to 250 ◦ C (Supplementary Fig. 4)11,18 . Electron energy loss spectroscopy (EELS) and ultraviolet photoelectron spectroscopy (UPS) results (Fig. 1c and Supplementary Fig. 5) indicate that pV3D3 has a shallow lowest unoccupied molecular orbital (LUMO) level (1.2 eV) and a deep highest occupied molecular orbital (HOMO) level (9.45 eV), leading to a wide energy gap (Eg ) of 8.25 V, comparable to that of Al2 O3 and SiO2 (ref. 19). This has a significant implication for its insulating properties in devices, in that it can provide 2
a sufficient energy barrier for both electron and hole injection. Furthermore, X-ray diffraction (XRD) data show that the pV3D3 films are amorphous (Supplementary Fig. 2c), which is favourable for spatial uniformity of its insulating characteristics. The MIM devices prepared over the relatively large substrate area of 5 × 10 cm2 show virtually identical characteristics with a relative standard deviation of 2.5%, exhibiting a high degree of uniformity of the iCVD process (Supplementary Fig. 6 and Supplementary Table 3). Capacitance being proportional to the ratio of k to insulator thickness, thinning down the insulating layers is a key route to low-power device operation1,7 . This is especially important for pV3D3, which has relatively low k of 2.2. Most applications in soft electronics do not require the same level of integration density as modern CMOS-based electronics20 , whose ever-growing needs for down-sizing demanded both ultrathin dielectrics and highk technology1 ; nevertheless, the gate capacitance should be made sufficiently high to realize low-voltage operation and the necessary driving capability required by a target application. According to the high-resolution transmission electron microscopy (HRTEM) images (Fig. 1d), thin films of pV3D3 in Al/pV3D3/Al devices form a sharp interface with adjacent layers with a good film integrity, at pV3D3 thicknesses (dpV3D3 ) of both 58 nm and 11 nm. The quality of ultrathin pV3D3 layers is further confirmed in energy dispersive X-ray spectroscopy (EDS) results (Fig. 1e), showing a sharp but homogeneous distribution of Si and O, the signature elements of the pV3D3 layer, in the thin region between two Al electrodes with a gap of ∼10 nm. The down-scalability of pV3D3 thin films is reflected also in their macroscopic electrical properties. That is, dpV3D3 in
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NATURE MATERIALS DOI: 10.1038/NMAT4237
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Figure 2 | Insulating properties of pV3D3 layers, analysed for Al/pV3D3/Al MIM devices. a, Ci versus frequency (left), Ci versus Ei (middle) and Ji versus Ei (right) measured for various dpV3D3 . b, Ji –Ei characteristics of an Al/pV3D3/Al MIM device (dpV3D3 = 6 nm) measured at various device temperatures (Tdev ) (left) and the corresponding Arrhenius plots (right). The inset indicates the enlarged Ji –Ei plot of the dashed red box area, showing that the Ji plots collapse onto a single line in the temperature range −140–0 ◦ C. c, ln|Ji /Ei2 | versus 1/Ei curves revealing a F–N tunnelling region. Inset shows an enlarged F–N region in which the plot was fitted to an apparent linear curve of the F–N tunnelling equation. d, Photographs showing Al/pV3D3/Al MIM devices (dpV3D3 = 19.6 nm) fabricated on PET substrates under tensile (left) and compressive (right) bending tests. Each inset image shows the side view of the corresponding bending. e, Ji measured at 3 MV cm−1 for various values of bending radius (R) and corresponding strain (S) calculated using the relation of S = dsub /2R, in which dsub is the thickness of a substrate. The inset illustrates the schematic of the bending test.
MIM devices, estimated through the capacitance measurement as described in Methods, can be reduced to as low as 6–7 nm, resulting in a high Ci of 250–300 nF cm−2 , which is stable over a wide range of operating frequencies and applied electric field (Ei ) (Fig. 2a). (See also Supplementary Fig. 7 for the down-scalability of the MIM devices with M being TaN or Au; refs 21–23.) Ji –Ei characteristics are also shown to overlap well for dpV3D3 from ∼70 nm to ∼6 nm (Fig. 2a; see also Supplementary Figs 6 and 7 for the reproducibility of the MIM devices with ultrathin pV3D3 layers.). A voltage ramp stress test indicates that the Ji of the MIM device with 6 nmthick pV3D3 layers can be maintained up to an Ei as high as ∼5.5 MV cm−1 , after which it begins to exhibit soft breakdown at 6 MV cm−1 (Supplementary Fig. 8). The observed level of insulating properties and sub-10 nm thickness scalability of the iCVD pV3D3 layer are unprecedented for polymeric films and comparable to that of inorganic insulating layers such as thermally grown SiO2 and high-k materials prepared by atomic layer deposition (ALD; refs 6,7,24,25). X-ray reflectivity (XRR) data measured for pV3D3 layers (Supplementary Fig. 9) indicate that the iCVD-based pV3D3 layers have a bulk density of 1.70 ± 0.02 g cm−3 , higher than those of most organosilicon polymers, regardless of dpV3D3 in the range ∼7.5 to 21 nm. The excellent down-scalability of their insulating properties may thus be regarded as coming from the capability of the iCVD process to form dense thin films down to such a low thickness with a high degree of consistency. To further elucidate the origin of the insulating properties of the pV3D3 layer, its charge transport mechanism was investigated by measuring Ji –Ei characteristics as a function of device temperature (Tdev ) using MIM devices with 6 nm-thick pV3D3 layers. The measured Ji –Ei characteristics match closely over a wide Tdev range from −140 ◦ C to 10 ◦ C (Fig. 2b), indicating that charge transport
through the pV3D3 layer is governed by tunnelling26,27 . It should be noted that such temperature-independent carrier conduction can be seen only when the defect density is sufficiently low that thermally assisted conduction is significantly suppressed26 . Ideal tunnellingbased conduction can also be confirmed by the Ji –Ei characteristics at relatively high Ei . A plot of ln|Ji /Ei2 | versus 1/Ei presented in Fig. 2c clearly shows two distinct regions at high Ei with good fit to those expected by Fowler–Nordheim (F–N) tunnelling28 . The transition from direct to F–N tunnelling occurs at approximately 4 MV cm−1 , which corresponds to ∼2.4 V for the 6-nm-thick pV3D3. This observation is consistent with the prediction of F–N tunnelling, considering the nominal injection barrier for electrons from Al electrodes to the LUMO level of pV3D3 layers to be ∼3 eV, estimated from the difference between the work function of Al and the LUMO level of pV3D3 (see Supplementary Fig. 10)26,28 . These observations are in good support of the notion that the iCVD process leads to the formation of pure polymeric films with low defect density. It can be attributed partly to its solvent-free nature leaving no solvent residues in the final polymer films, thus making them less subject to formation of occasional pinholes, and to its unique film-forming mechanism, where the polymerization reaction is triggered by dissociation of the initiator without damaging the input monomers. The latter is in contrast to conventional CVD methods such as plasma-enhanced or pyrolysis-based CVDs, where polymeric films are formed by the direct decomposition of monomers and thus are prone to defects or by-products originating from plasma-induced or thermally induced damage13,29 . For application in soft electronic devices, mechanical flexibility of dielectric layers cannot be overemphasized30 . As can be seen in Fig. 2d,e, the leakage characteristics of flexible MIM devices (dpV3D3 = 19.6 nm) prepared on 125-µm-thick polyethylene
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES 10−6
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Figure 3 | Bottom-gated C60 FETs with ultrathin pV3D3 GIs on various gate electrodes and substrates. a,b, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) (a) and ID versus VD (b) characteristics of bottom-gated C60 FETs with 15.3 nm-thick pV3D3 GIs. Inset in a: Structure of bottom-gated C60 FETs with pV3D3 GIs. c, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics of bottom-gated C60 FETs with pV3D3 GIs and various gate electrodes of Cu, Au, ITO and Ag processed from Ag-ink. d, C60 FET array fabricated on a cellophane tape. Steps for transfer from a carrier substrate to a hemispherical object are as follows: first, C60 FETs with pV3D3 GIs were fabricated on the cellophane tape attached on a glass substrate (top left). The cellophane tape with the C60 FETs was carefully detached from the glass substrate (top right), and reattached on a curved surface (bottom right). The device characteristics of the transferred C60 FETs on cellophane tape were then analysed (bottom left). e, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics measured before and after transfer of the C60 TFT array on cellophane tape onto a curved surface. Channel length (L) and width (W) are 200 µm and 1,000 µm respectively for all C60 FETs.
terephthalate (PET) substrates remained virtually unchanged on bending to a radius of curvature (R) as small as 1.5 mm for tensile stress and 2 mm for compressive stress. These values correspond to a tensile strain of 4% and a compressive strain of 3%, respectively. When compared to inorganic insulating layers (for example, anodized AlOx that withstood a tensile strain of up to 1.4%11 ), the tolerance of the proposed pV3D3 layers to mechanical strain is significantly larger. This will thus be advantageous for flexible electronics, in that it allows a larger degree of freedom in designing device architecture as well as in choosing substrates, encapsulation layers, and so on. Considering that typical crosslinked films are relatively 4
rigid, the excellent mechanical flexibility observed for pV3D3 films is probably associated with its elastic hexagonal siloxane structure. The fact that ultrathin pV3D3 films are readily achievable is also beneficial because the mechanical flexibility of a film typically improves for thinner layers9 . Note that the thickness of pV3D3 has been chosen to be larger for flexible devices than the minimum value (∼6 nm) used for MIM devices grown on rigid substrates. Great care must be taken when ultrathin dielectrics are applied in actual device configurations and/or prepared on non-conventional substrates, because the thinner a dielectric layer is, the more vulnerable to failure devices based thereon are. The optimal dielectric thickness should
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NATURE MATERIALS DOI: 10.1038/NMAT4237 b
1.0
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Figure 4 | Top-gated P3HT, IGZO and graphene FETs with pV3D3 GIs. a, Photograph of a top-gated P3HT FET array (dpV3D3 = 15.4 nm; on a 10 × 10 cm2 PEN substrate). b, Distribution of µFET obtained in a saturation region (left) and of VT (right) measured from 124 FETs across the array. c, Evolution of drain current (ID ) normalized to its initial value during constant voltage stress test in the ‘diode connection’ at a stress bias (Vstr ) of −4 V (measured from 10 FETs). L and W were 50 µm and 1,000 µm, respectively. d, Cross-sectional HRTEM image of a P3HT FET device corresponding to the region represented by the dashed line in the schematic device structure shown in the inset. e, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics of top-gated IGZO FETs (dpV3D3 = 32 nm; L = 200 µm; and W = 1,000 µm) with the device structure shown in the inset. f, HRTEM image of a graphene/pV3D3 stack with dpV3D3 of 7 nm fabricated on SiO2 . g, Raman spectroscopy results of graphene with (red) and without a pV3D3 layer (black) deposited. The enlarged Raman spectra of the red box region is shown in the inset. The schematic graphene film structures used for Raman spectroscopy are also shown (right). h, Transfer characteristics of top-gated graphene FETs with pV3D3 GIs (dpV3D3 = 7.8 nm). L and W were 10 µm and 8 µm, respectively for the graphene FETs. Inset shows the schematic structure of the graphene FETs.
be chosen considering the non-ideal situations such as high surface roughness of underlying layers, structured electrode edges, and/or asymmetric electrode structures leading to high built-in fields (for example, those in FETs whose gate and source/drain electrodes have a large difference in their work functions). To test the feasibility of the iCVD-grown pV3D3 film as a gate insulator (GI), OFETs were fabricated using evaporated fullerene (C60 ) as a channel layer (Fig. 3a). As shown in Fig. 3a,b and Table 1, C60 -based OFETs with a pV3D3 GI layer (dpV3D3 = 15.3 nm) exhibit ideal, hysteresis-free transfer characteristics with a µFET of 1.3 cm2 V−1 s−1 in the saturation regime, on/off ratios greater than 105 , a subthreshold swing (SS) of 0.173 V per decade, and a threshold voltage (VT ) as low as 0.64 V (ref. 31). High-performance FETs with low gate leakage current (IG ) were also achieved for a wide range of dpV3D3 , between 12–43 nm (see Supplementary Fig. 11 and Supplementary Table 4), in good agreement with results from the MIM
experiment. Because the iCVD process is surface independent13 , bottom-gated C60 FETs with various gate electrodes, including Cu, Au, indium tin oxide (ITO), and even solution-processed Ag-ink layers could be fabricated with pV3D3 GIs (dpV3D3 = 30 ± 10 nm). Each device exhibits outstanding device characteristics with low IG , regardless of the gate electrode material (Fig. 3c and Table 1). In particular, the conformal growth characteristic of the iCVD process allows the formation of highly insulating pV3D3 layers even on a Ag-ink-based gate electrode with a root-mean-square (r.m.s.) roughness as high as 19.8 nm (Supplementary Fig. 12)13,32 . Together with the conformal growth characteristics, the low Tsub of the iCVD process makes it possible to grow polymeric thin films even on low-cost plastics that are vulnerable to thermal damage and have a relatively rough surface morphology (Supplementary Fig. 13 and Supplementary Table 5)13 . Figure 3d shows photographs of C60 FETs fabricated directly on a conventional cellophane tape (without any
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES Table 1 | Electrical characteristics of bottom-gated C60 FETs using pV3D3 GIs. Substrate
Gate
Glass Glass Glass Glass Glass Cell.-tape
Al Cu Au ITO Ag-ink Al
Rq.Gate ∗ (nm) 2.9 – – 1.2 19.8 –
Ci (nF cm−2 ) 127 59.5 66.9 83.8 53.0 45.4
dpV3D3 (nm) 15.3 32.7 29.1 23.2 36.7 42.9
µFET† (cm2 V−1 s−1 ) 1.32 1.83 1.66 1.52 1.69 1.20
VT (V) 0.64 1.57 1.64 2.09 1.99 2.03
SS (V per decade) 0.173 0.301 0.277 0.210 0.314 0.506
on/off >105 >105 >105 >105 >105 >105
IG.on‡ (A)
Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics Hanul Moon1,2†, Hyejeong Seong2,3†, Woo Cheol Shin1,2†, Won-Tae Park4, Mincheol Kim1,2, Seungwon Lee1,2, Jae Hoon Bong1,2, Yong-Young Noh4, Byung Jin Cho1,2*, Seunghyup Yoo1,2* and Sung Gap Im2,3* Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.
I
nsulating layers are an essential component enabling reliable operation of field-effect transistors (FETs), flash memory and capacitors in modern electronic systems1 . With the emergence of next-generation, ‘soft’ electronics relying on the mechanical flexibility of materials involved, the new generation of electronic devices requires insulating layers to work with unconventional substrates and newly emerging semiconductor materials2–5 . To this end, polymeric layers are being intensively investigated as new insulating layers6–8 . Owing to the relatively low dielectric constants (k) of most polymeric materials, however, ultrathin layers are required to achieve the high capacitance density (Ci ) essential for low-power operation. Unfortunately, it is challenging to reproducibly make pinhole-free polymeric films thinner than a few tens of nanometres over large areas6,7 . Further complications arise from incomplete removal of solvent residues and required solvent orthogonality with underlying layers in the case of solutionprocessed polymeric layers. As an alternative, molecularly thin selfassembled monolayers (SAMs) or ultrathin oxide layers grown by a low-temperature process (for example, anodized AlOx layers) could also be used as insulating layers in flexible devices9–11 . However, the surface-specific nature of SAMs and anodized oxides makes it difficult to extend their application across various device configurations and material sets, calling for the development of insulators that can provide a greater degree of freedom in designing the architecture and process flow for soft electronic devices. Here, we demonstrate poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) as a versatile
polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. We show that the iCVD process enables the formation of highly uniform, ultrathin films of pV3D3 with excellent insulating properties, owing to the advantageous characteristics of the iCVD process, including low process temperature, conformal surface growth and high purity. Consequently, iCVD pV3D3 layers are demonstrated as reliable polymeric insulating layers that are non-destructive and have electrical and mechanical characteristics suitable for soft electronic devices. iCVD is an all-dry vapour-phase technique, where vapourized monomers form polymeric films directly on the surface of a substrate. Inherited from conventional CVD processes, iCVD has a good scalability and compatibility with high-throughput manufacturing12 , can be set up mostly with standard, off-the-shelf parts, and operates at a moderate vacuum level in a mild temperature range13 . Polymeric films in iCVD are formed by the following mechanism: (i) introduction of vapourized monomers and initiators; (ii) thermal dissociation of initiators to form radicals on contact with heated filaments; (iii) physical adsorption of monomers onto cooled substrates; and (iv) free-radical polymerization of adsorbed monomers on the surface (Fig. 1a)14,15 . The surface-growing characteristics of the iCVD process enable the conformal coverage of polymeric films with a high degree of uniformity over a large area with virtually no surface or substrate limitations13 . Also, iCVD-grown polymer films generally have high chemical purity with no residues because the deposition process is inherently free of solvents and additives13 . Furthermore, the optimal substrate temperature (Tsub ) is near room
1 Department of Electrical Engineering, Korea Advanced Institute of Science and technology (KAIST), Daejeon 305-701, Republic of Korea. 2 Graphene Research Center, KI for Nanocentury, KAIST, Daejeon 305-701, Republic of Korea. 3 Department of Chemical and Biomolecular Engineering, KAIST, Daejeon 305-701, Republic of Korea. 4 Department of Energy and Materials Engineering, Dongguk University, Seoul 100-715, Republic of Korea. †These authors contributed equally to this work. *e-mail: [email protected]; [email protected]; [email protected]
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES a
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Figure 1 | pV3D3 polymer insulating layers produced by iCVD. a, Schematic of the iCVD process mechanism: (i) vapourized monomers and initiators are introduced, (ii) initiators are thermally dissociated into radicals by contact with filaments (red lines) heated at ∼200 ◦ C, which are positioned away from the substrate, (iii) then monomers and initiator radicals are adsorbed onto the surface of a cooled substrate (40 ◦ C), (iv) where they undergo free-radical polymerization to form pV3D3 thin films. b, Chemical structures of V3D3 monomer, initiator (tert-butyl peroxide; TBPO), and pV3D3 polymer. c, Eg of pV3D3 determined by EELS (left) and the energy band diagram of pV3D3 obtained from UPS and EELS data (right). Inset shows the zoomed-out EELS spectra of pV3D3 (blue) and SiO2 (black). d, Structure of an Al/pV3D3/Al MIM device (top left) and cross-sectional HRTEM images with dpV3D3 of 58 nm (top right) and 11 nm (bottom right). The zoomed-in TEM image of the 11-nm-thick pV3D3 layer is shown in bottom left. e, Cross-sectional scanning electron microscope (SEM) image of an Al/pV3D3(∼10 nm)/Al MIM device, and elemental analysis results by EDS. The graph shows an EDS line scan corresponding to the arrows in the cross-sectional SEM image (top left). The dashed red box indicates the area of pV3D3 layer. The remaining images show EDS 2D mapping results of Al, O, and Si, corresponding to the SEM image.
temperature for most iCVD polymers. Coupled with its solvent-free nature, the low Tsub of the iCVD process enables non-destructive deposition onto underlying device layers and substrates that are thermally and/or chemically sensitive13 . All these benefits make the iCVD-based polymers an ideal candidate for a versatile insulator that can cope with the various demands of emerging soft electronic devices. A variety of iCVD-based polymer layers were tested in a metal/insulator/metal (MIM) structure and exhibit excellent insulating properties with leakage current densities (Ji ) lower than 10−8 –10−9 A cm−2 (see Supplementary Fig. 1). In particular, pV3D3, polymerized from a monomer of 1,3,5-trimethyl-1,3,5trivinyl cyclotrisiloxane (V3D3; Fig. 1b for molecular structure; and Supplementary Fig. 2a,b, and Supplementary Table 1 for analytical data), has the potential to make compact thin films with good chemical stability owing to its high crosslinking density16,17 . In fact, its film morphology and thickness is shown to remain virtually unchanged after a 24-h soak in a highly solvating solvent such as acetone and toluene (see Supplementary Table 2 and Supplementary Fig. 3). Furthermore, pV3D3 exhibits a good thermal stability up to 250 ◦ C (Supplementary Fig. 4)11,18 . Electron energy loss spectroscopy (EELS) and ultraviolet photoelectron spectroscopy (UPS) results (Fig. 1c and Supplementary Fig. 5) indicate that pV3D3 has a shallow lowest unoccupied molecular orbital (LUMO) level (1.2 eV) and a deep highest occupied molecular orbital (HOMO) level (9.45 eV), leading to a wide energy gap (Eg ) of 8.25 V, comparable to that of Al2 O3 and SiO2 (ref. 19). This has a significant implication for its insulating properties in devices, in that it can provide 2
a sufficient energy barrier for both electron and hole injection. Furthermore, X-ray diffraction (XRD) data show that the pV3D3 films are amorphous (Supplementary Fig. 2c), which is favourable for spatial uniformity of its insulating characteristics. The MIM devices prepared over the relatively large substrate area of 5 × 10 cm2 show virtually identical characteristics with a relative standard deviation of 2.5%, exhibiting a high degree of uniformity of the iCVD process (Supplementary Fig. 6 and Supplementary Table 3). Capacitance being proportional to the ratio of k to insulator thickness, thinning down the insulating layers is a key route to low-power device operation1,7 . This is especially important for pV3D3, which has relatively low k of 2.2. Most applications in soft electronics do not require the same level of integration density as modern CMOS-based electronics20 , whose ever-growing needs for down-sizing demanded both ultrathin dielectrics and highk technology1 ; nevertheless, the gate capacitance should be made sufficiently high to realize low-voltage operation and the necessary driving capability required by a target application. According to the high-resolution transmission electron microscopy (HRTEM) images (Fig. 1d), thin films of pV3D3 in Al/pV3D3/Al devices form a sharp interface with adjacent layers with a good film integrity, at pV3D3 thicknesses (dpV3D3 ) of both 58 nm and 11 nm. The quality of ultrathin pV3D3 layers is further confirmed in energy dispersive X-ray spectroscopy (EDS) results (Fig. 1e), showing a sharp but homogeneous distribution of Si and O, the signature elements of the pV3D3 layer, in the thin region between two Al electrodes with a gap of ∼10 nm. The down-scalability of pV3D3 thin films is reflected also in their macroscopic electrical properties. That is, dpV3D3 in
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NATURE MATERIALS DOI: 10.1038/NMAT4237
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Figure 2 | Insulating properties of pV3D3 layers, analysed for Al/pV3D3/Al MIM devices. a, Ci versus frequency (left), Ci versus Ei (middle) and Ji versus Ei (right) measured for various dpV3D3 . b, Ji –Ei characteristics of an Al/pV3D3/Al MIM device (dpV3D3 = 6 nm) measured at various device temperatures (Tdev ) (left) and the corresponding Arrhenius plots (right). The inset indicates the enlarged Ji –Ei plot of the dashed red box area, showing that the Ji plots collapse onto a single line in the temperature range −140–0 ◦ C. c, ln|Ji /Ei2 | versus 1/Ei curves revealing a F–N tunnelling region. Inset shows an enlarged F–N region in which the plot was fitted to an apparent linear curve of the F–N tunnelling equation. d, Photographs showing Al/pV3D3/Al MIM devices (dpV3D3 = 19.6 nm) fabricated on PET substrates under tensile (left) and compressive (right) bending tests. Each inset image shows the side view of the corresponding bending. e, Ji measured at 3 MV cm−1 for various values of bending radius (R) and corresponding strain (S) calculated using the relation of S = dsub /2R, in which dsub is the thickness of a substrate. The inset illustrates the schematic of the bending test.
MIM devices, estimated through the capacitance measurement as described in Methods, can be reduced to as low as 6–7 nm, resulting in a high Ci of 250–300 nF cm−2 , which is stable over a wide range of operating frequencies and applied electric field (Ei ) (Fig. 2a). (See also Supplementary Fig. 7 for the down-scalability of the MIM devices with M being TaN or Au; refs 21–23.) Ji –Ei characteristics are also shown to overlap well for dpV3D3 from ∼70 nm to ∼6 nm (Fig. 2a; see also Supplementary Figs 6 and 7 for the reproducibility of the MIM devices with ultrathin pV3D3 layers.). A voltage ramp stress test indicates that the Ji of the MIM device with 6 nmthick pV3D3 layers can be maintained up to an Ei as high as ∼5.5 MV cm−1 , after which it begins to exhibit soft breakdown at 6 MV cm−1 (Supplementary Fig. 8). The observed level of insulating properties and sub-10 nm thickness scalability of the iCVD pV3D3 layer are unprecedented for polymeric films and comparable to that of inorganic insulating layers such as thermally grown SiO2 and high-k materials prepared by atomic layer deposition (ALD; refs 6,7,24,25). X-ray reflectivity (XRR) data measured for pV3D3 layers (Supplementary Fig. 9) indicate that the iCVD-based pV3D3 layers have a bulk density of 1.70 ± 0.02 g cm−3 , higher than those of most organosilicon polymers, regardless of dpV3D3 in the range ∼7.5 to 21 nm. The excellent down-scalability of their insulating properties may thus be regarded as coming from the capability of the iCVD process to form dense thin films down to such a low thickness with a high degree of consistency. To further elucidate the origin of the insulating properties of the pV3D3 layer, its charge transport mechanism was investigated by measuring Ji –Ei characteristics as a function of device temperature (Tdev ) using MIM devices with 6 nm-thick pV3D3 layers. The measured Ji –Ei characteristics match closely over a wide Tdev range from −140 ◦ C to 10 ◦ C (Fig. 2b), indicating that charge transport
through the pV3D3 layer is governed by tunnelling26,27 . It should be noted that such temperature-independent carrier conduction can be seen only when the defect density is sufficiently low that thermally assisted conduction is significantly suppressed26 . Ideal tunnellingbased conduction can also be confirmed by the Ji –Ei characteristics at relatively high Ei . A plot of ln|Ji /Ei2 | versus 1/Ei presented in Fig. 2c clearly shows two distinct regions at high Ei with good fit to those expected by Fowler–Nordheim (F–N) tunnelling28 . The transition from direct to F–N tunnelling occurs at approximately 4 MV cm−1 , which corresponds to ∼2.4 V for the 6-nm-thick pV3D3. This observation is consistent with the prediction of F–N tunnelling, considering the nominal injection barrier for electrons from Al electrodes to the LUMO level of pV3D3 layers to be ∼3 eV, estimated from the difference between the work function of Al and the LUMO level of pV3D3 (see Supplementary Fig. 10)26,28 . These observations are in good support of the notion that the iCVD process leads to the formation of pure polymeric films with low defect density. It can be attributed partly to its solvent-free nature leaving no solvent residues in the final polymer films, thus making them less subject to formation of occasional pinholes, and to its unique film-forming mechanism, where the polymerization reaction is triggered by dissociation of the initiator without damaging the input monomers. The latter is in contrast to conventional CVD methods such as plasma-enhanced or pyrolysis-based CVDs, where polymeric films are formed by the direct decomposition of monomers and thus are prone to defects or by-products originating from plasma-induced or thermally induced damage13,29 . For application in soft electronic devices, mechanical flexibility of dielectric layers cannot be overemphasized30 . As can be seen in Fig. 2d,e, the leakage characteristics of flexible MIM devices (dpV3D3 = 19.6 nm) prepared on 125-µm-thick polyethylene
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES 10−6
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Figure 3 | Bottom-gated C60 FETs with ultrathin pV3D3 GIs on various gate electrodes and substrates. a,b, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) (a) and ID versus VD (b) characteristics of bottom-gated C60 FETs with 15.3 nm-thick pV3D3 GIs. Inset in a: Structure of bottom-gated C60 FETs with pV3D3 GIs. c, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics of bottom-gated C60 FETs with pV3D3 GIs and various gate electrodes of Cu, Au, ITO and Ag processed from Ag-ink. d, C60 FET array fabricated on a cellophane tape. Steps for transfer from a carrier substrate to a hemispherical object are as follows: first, C60 FETs with pV3D3 GIs were fabricated on the cellophane tape attached on a glass substrate (top left). The cellophane tape with the C60 FETs was carefully detached from the glass substrate (top right), and reattached on a curved surface (bottom right). The device characteristics of the transferred C60 FETs on cellophane tape were then analysed (bottom left). e, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics measured before and after transfer of the C60 TFT array on cellophane tape onto a curved surface. Channel length (L) and width (W) are 200 µm and 1,000 µm respectively for all C60 FETs.
terephthalate (PET) substrates remained virtually unchanged on bending to a radius of curvature (R) as small as 1.5 mm for tensile stress and 2 mm for compressive stress. These values correspond to a tensile strain of 4% and a compressive strain of 3%, respectively. When compared to inorganic insulating layers (for example, anodized AlOx that withstood a tensile strain of up to 1.4%11 ), the tolerance of the proposed pV3D3 layers to mechanical strain is significantly larger. This will thus be advantageous for flexible electronics, in that it allows a larger degree of freedom in designing device architecture as well as in choosing substrates, encapsulation layers, and so on. Considering that typical crosslinked films are relatively 4
rigid, the excellent mechanical flexibility observed for pV3D3 films is probably associated with its elastic hexagonal siloxane structure. The fact that ultrathin pV3D3 films are readily achievable is also beneficial because the mechanical flexibility of a film typically improves for thinner layers9 . Note that the thickness of pV3D3 has been chosen to be larger for flexible devices than the minimum value (∼6 nm) used for MIM devices grown on rigid substrates. Great care must be taken when ultrathin dielectrics are applied in actual device configurations and/or prepared on non-conventional substrates, because the thinner a dielectric layer is, the more vulnerable to failure devices based thereon are. The optimal dielectric thickness should
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NATURE MATERIALS DOI: 10.1038/NMAT4237 b
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Figure 4 | Top-gated P3HT, IGZO and graphene FETs with pV3D3 GIs. a, Photograph of a top-gated P3HT FET array (dpV3D3 = 15.4 nm; on a 10 × 10 cm2 PEN substrate). b, Distribution of µFET obtained in a saturation region (left) and of VT (right) measured from 124 FETs across the array. c, Evolution of drain current (ID ) normalized to its initial value during constant voltage stress test in the ‘diode connection’ at a stress bias (Vstr ) of −4 V (measured from 10 FETs). L and W were 50 µm and 1,000 µm, respectively. d, Cross-sectional HRTEM image of a P3HT FET device corresponding to the region represented by the dashed line in the schematic device structure shown in the inset. e, |ID | versus VG (solid lines) and |IG | versus VG (dotted lines) characteristics of top-gated IGZO FETs (dpV3D3 = 32 nm; L = 200 µm; and W = 1,000 µm) with the device structure shown in the inset. f, HRTEM image of a graphene/pV3D3 stack with dpV3D3 of 7 nm fabricated on SiO2 . g, Raman spectroscopy results of graphene with (red) and without a pV3D3 layer (black) deposited. The enlarged Raman spectra of the red box region is shown in the inset. The schematic graphene film structures used for Raman spectroscopy are also shown (right). h, Transfer characteristics of top-gated graphene FETs with pV3D3 GIs (dpV3D3 = 7.8 nm). L and W were 10 µm and 8 µm, respectively for the graphene FETs. Inset shows the schematic structure of the graphene FETs.
be chosen considering the non-ideal situations such as high surface roughness of underlying layers, structured electrode edges, and/or asymmetric electrode structures leading to high built-in fields (for example, those in FETs whose gate and source/drain electrodes have a large difference in their work functions). To test the feasibility of the iCVD-grown pV3D3 film as a gate insulator (GI), OFETs were fabricated using evaporated fullerene (C60 ) as a channel layer (Fig. 3a). As shown in Fig. 3a,b and Table 1, C60 -based OFETs with a pV3D3 GI layer (dpV3D3 = 15.3 nm) exhibit ideal, hysteresis-free transfer characteristics with a µFET of 1.3 cm2 V−1 s−1 in the saturation regime, on/off ratios greater than 105 , a subthreshold swing (SS) of 0.173 V per decade, and a threshold voltage (VT ) as low as 0.64 V (ref. 31). High-performance FETs with low gate leakage current (IG ) were also achieved for a wide range of dpV3D3 , between 12–43 nm (see Supplementary Fig. 11 and Supplementary Table 4), in good agreement with results from the MIM
experiment. Because the iCVD process is surface independent13 , bottom-gated C60 FETs with various gate electrodes, including Cu, Au, indium tin oxide (ITO), and even solution-processed Ag-ink layers could be fabricated with pV3D3 GIs (dpV3D3 = 30 ± 10 nm). Each device exhibits outstanding device characteristics with low IG , regardless of the gate electrode material (Fig. 3c and Table 1). In particular, the conformal growth characteristic of the iCVD process allows the formation of highly insulating pV3D3 layers even on a Ag-ink-based gate electrode with a root-mean-square (r.m.s.) roughness as high as 19.8 nm (Supplementary Fig. 12)13,32 . Together with the conformal growth characteristics, the low Tsub of the iCVD process makes it possible to grow polymeric thin films even on low-cost plastics that are vulnerable to thermal damage and have a relatively rough surface morphology (Supplementary Fig. 13 and Supplementary Table 5)13 . Figure 3d shows photographs of C60 FETs fabricated directly on a conventional cellophane tape (without any
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NATURE MATERIALS DOI: 10.1038/NMAT4237
ARTICLES Table 1 | Electrical characteristics of bottom-gated C60 FETs using pV3D3 GIs. Substrate
Gate
Glass Glass Glass Glass Glass Cell.-tape
Al Cu Au ITO Ag-ink Al
Rq.Gate ∗ (nm) 2.9 – – 1.2 19.8 –
Ci (nF cm−2 ) 127 59.5 66.9 83.8 53.0 45.4
dpV3D3 (nm) 15.3 32.7 29.1 23.2 36.7 42.9
µFET† (cm2 V−1 s−1 ) 1.32 1.83 1.66 1.52 1.69 1.20
VT (V) 0.64 1.57 1.64 2.09 1.99 2.03
SS (V per decade) 0.173 0.301 0.277 0.210 0.314 0.506
on/off >105 >105 >105 >105 >105 >105
IG.on‡ (A)
