www.advmat.de www.MaterialsViews.com
COMMUNICATION
The Origin of Excellent Gate-Bias Stress Stability in Organic Field-Effect Transistors Employing Fluorinated-Polymer Gate Dielectrics Jiye Kim, Jaeyoung Jang, Kyunghun Kim, Haekyoung Kim, Se Hyun Kim,* and Chan Eon Park* Over the past several decades, organic field-effect transistors (OFETs) have emerged as promising devices for applications in flexible displays, radio-frequency identification tags, and chemical or biological sensing.[1,2] The gate-bias stress instability, which decreases the current in a channel and shifts the threshold voltage (Vth) under an applied bias, has presented a significant barrier to commercializing OFETs.[3] The gate-bias stress instability in amorphous Si-based devices arises from charge trapping in dangling bond defects and can be analyzed using a stretched exponential function.[4] Although the OFET instability behavior can be satisfactorily fit to these quantitative functions, the detailed mechanisms underlying the behavior remain unclear. Previous studies aimed at understanding the gate-bias stress instability in OFETs have shown that the instability may be influenced by the following factors: 1) the environment (e.g., water molecules), 2) charge trapping in the semiconductor layer, the dielectric layer, or at the interface between the two, and 3) charge injection from the gate into the dielectric layer.[5–8] The utilization of fluorinated polymer dielectrics has enabled OFETs to achieve good stability against sustained gate-bias stress.[9] It is generally accepted that the high stability of these OFETs results from the extremely hydrophobic nature of the fluorine functional groups. The highly water-repellent character of the fluorine functional groups suppresses trap formation in the semiconductor/dielectric interface and prevents the adsorption of water/oxygen molecules that potentially induce charge
J. Kim, Dr. J. Jang, K. Kim, Prof. C. E. Park POSTECH Organic Electronics Laboratory Department of Chemical Engineering Pohang University of Science and Technology (POSTECH) 77 Cheongam-Ro, Nam-Gu, Pohang, Gyungbuk 790-784, Republic of Korea E-mail: [email protected] Prof. H. Kim School of Materials Science and Engineering Yeungnam University 280 Daehak-Ro, Gyungsan, Gyeongbuk 712-749, Republic of Korea Prof. S. H. Kim Department of Nano Medical and Polymer Materials Yeungnam University 280 Daehak-Ro, Gyungsan, Gyeongbuk 712-749, Republic of Korea E-mail: [email protected]
DOI: 10.1002/adma.201402363
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
trapping.[9] Recently, our group demonstrated decent levels of gate-bias stress stability of OFETs using less-hydrophobic fluorinated polymer dielectrics.[10] These results imply that the hydrophobicity of the dielectric surface is not the only factor affecting the gate-bias stress instability behavior in OFETs. To reach excellent levels of gate bias-stress stability, it is therefore important to understand the mechanisms that contribute to charge trapping under a gate bias-stress in OFETs prepared with hydrophobic fluorinated gate dielectrics. In the study reported here, we examined the origins and mechanisms underlying the gate-bias stress instabilities observed in OFETs by quantitatively investigating both the physico-chemical properties and the electronic structures of the interfaces between p-type pentacene layers and a series of hydrophobic polymer dielectrics containing methoxy-, methyl-, or fluoro-functionalized polystyrene moieties. We demonstrated the existence of an energetic barrier to charge trapping related to the gate-bias stress instability at the semiconductor/ gate dielectric interface. This energetic barrier concept was supported both by the gate-bias stress instability tests, performed over a range of applied voltage levels and durations, and by the electronic structures of the semiconductor/gate dielectric interface, as characterized by ultraviolet photoemission spectroscopy (UPS). Figure 1a shows the chemical structures of the dielectric polymer materials used in this work: poly(4-methoxystyrene) (PMOS), poly(4-methylstyrene) (PMS), and poly(pentafluorostyrene) (PFS). As shown in the device structure, the gate dielectrics combined topmost ultrathin polymer (ca. 10 nm) and 300 nm-thick thermally grown SiO2 layers to rule out charge injection effects from the gate into the dielectric bulk (Figure 1c). All these bilayer gate dielectrics showed smooth and featureless surface morphologies (Figure S1a–c, Supporting Information), and similar capacitances (ca. 10 nF cm–2). The dielectric constants (k) of the polymer layers were 3.24, 2.62, and 2.64 for PMOS, PMS, and PFS, respectively. The surface potentials for the polymer surfaces were characterized by secondary electron emission spectra (Figure 1b). The onset of the secondary electrons, which corresponded to the surface potential of the polymer surface, was determined by extrapolating two solid lines from the background and straight onsets of each spectrum. As shown in Figure 1b, the kinetic energies for the onsets of the secondary electrons followed the order PFS (5.78 eV) > PMOS (5.34 eV) > PMS (5.27 eV). Higher kinetic energies indicate a higher surface potential, namely, a stronger
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
1
www.advmat.de
COMMUNICATION
www.MaterialsViews.com
Figure 1. a) Chemical structures of dielectric polymer materials. b) Secondary electron emission of PMOS, PMS, and PFS films on Au substrates. c) Schematic diagram of a top-contact OFET. d) Transfer characteristics of OFETs employing polymer-treated SiO2 dielectrics, and e) the corresponding parameters µFET and Vth.
electron-withdrawing character. The atom with the highest electronegativity, fluorine, produces a C–F bond with the largest dipole moment (compared to C–O and C–H), leading to a high surface potential at the PFS surface.[11] Interestingly, the difference of surface potential between PMOS and PMS was quite small (ca. 0.07 eV), even though the methoxy-substituent is more polar than the methyl one. This means that the differing effects that the methoxy- and methyl-substituents have on the surface potential are much more minor than expected. A possible explanation is that the oxygen atom in the methoxy-substituent could be “blocked” from the surface by the pendant methyl group. Generally, UPS measurement gives information related to the electronic structures of materials in the proximity of the corresponding surface (the electron inelastic mean free path is about 5–10 Å).[12] Therefore, pendant methyl groups pointing out to the surface are likely to have a significant influence on the surface potential of PMOS. The presence of molecular dipoles at the semiconductor/gate dielectric interface modulated the charge carrier density in the channel of the OFET and tailored the electrical parameters, such as the field-effect mobility (µFET), turn-on voltage (Vturn-on), and Vth.[13,14] Another factor that contributes to the dielectric surface properties is the surface energy (γs), which provides a direct indication of the intermolecular forces. PFS-, PMS-, and PMOStreated bilayer dielectrics showed γs values of 30.88, 42.24, and 48.48 mJ m−2, respectively (Table S1, Supporting Information). Although the PFS exhibited a high surface potential, the inherent characteristics of fluorine (such as the small atomic radius, comparable to that of hydrogen, and the lowest polarizability among all atoms) produced a nonpolar or weakly interactive surface.[11,15] These factors explain why the PFS surface displayed the lowest value of γs. In general, the γs value of 2
wileyonlinelibrary.com
dielectrics has been a critical factor for determining the crystal growth of overlying organic semiconductors, particularly by generating competing interactions between the semiconductor and the dielectric surface during the first seeding stage.[16] PMOS and PMS dielectrics with γs values comparable to that of the pentacene crystal planes (48.0 mJ m−2) were found to induce the “layer and island” growth mode (“Stranski–Krastanov mode”) of pentacene. By contrast, the three-dimensional (3D) pentacene islands on the PFS dielectric with the lower γs value displayed a Volmer-Weber growth mode (see the Supporting Information). Consequently, the pentacene films grown on the PMOS and PMS dielectrics showed terrace-like crystals with an average grain size of ca. 1.7 µm and ca. 1.3 µm, respectively, whereas those on the PFS surfaces showed granular pentacene grains with smaller grain sizes (200–300 nm) (Figure S1g–i in the Supporting Information). The 2D grazing incidence X-ray diffraction (GIXD) pattern of the pentacene film supported the growth of smaller crystals on the PFS dielectric (Figure S2c, Supporting Information). Clear (00l)* reflections along the qz direction and in-plane reflections were observed together with more scattering along the Debye ring, which indicates the presence of the bulk phase of the pentacene film. Figure 1d shows the drain current–gate voltage (ID–VG) transfer characteristics of top-contact pentacene OFETs employing PMOS-, PMS-, and PFS-treated SiO2 bilayer dielectrics. The electrical characteristics of these OFETs are summarized in Figure 1e. Although PFS samples showed the fastest Vturn-on (ca. 0 V, see Table S2 in the Supporting Information), the µFET of PMS samples exceeded those of other samples and reached values as high as 1.07 cm2 V–1 s–1, whereas the PFS sample yielded a lower µFET of 0.33 cm2 V–1 s–1. The electronwithdrawing properties of the PFS surface (due to the highest
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
www.advmat.de www.MaterialsViews.com
COMMUNICATION Figure 2. Transfer characteristics under nitrogen conditions of OFETs containing a) PMOS, b) PMS, and c) PFS dielectric surfaces before, during, and after an applied gate bias stress of VG = –60 V (VD = 0) for 12 h.
surface potential) induced extra holes in the off-regime to balance charge neutrality, leading to faster Vturn-on of the device compared with other devices. The unfavorable growth of pentacene film on the PFS surface should produce trap states at the channel and reduce µFET for the PFS-based OFET. Interestingly, the device stabilities (e.g., hysteresis and gate-bias stress stability) in the corresponding OFETs show a different tendency to µFET. All devices tested exhibited negligible hysteresis (see Figure 1d). In addition, the application of a sustained VG of –60 V (VD = 0 V) for 12 h to each of the three devices yielded ΔVth values after the gate-bias stress of –13.14 V (PMOS-), –9.28 V (PMS-), and –5.05 V (PFS-based OFETs) (Figure 2). These results are rather counterintuitive because the PFS-based OFET exhibited better device stability than the other samples, despite having the largest numbers of traps and the lowest µFET. To obtain more insight into the effect of the surface of the fluorinated gate dielectric on the gate-bias stress stability, we performed additional experiments with different device geometry and gate dielectric/semiconductor combinations: 1) top-gate/ bottom-contact pentacene OFETs, 2) bottom-gate OFETs with solution-processed semiconductor showing similar crystalline morphologies regardless of different dielectric surfaces, and 3) bottom-gate pentacene OFETs with aliphatic self-assembled monolayer treated dielectrics (Figures S3–S7 in the Supporting Information). This set of experiments revealed that OFETs with fluorinated gate dielectric surfaces exhibit superior gate-bias stress stability. The inherent characteristics of traps in OFETs can be characterized according to the state lifetime or the energetic position relative to the band edge. Shallow traps with short lifetimes (10−3–10−6 s), distributed near the band edge, can disturb the transport of free carriers in the channel.[17] Structural defects (e.g., misorientations, voids, and grain boundaries) or polar dielectric functionalities can broaden the density of states at the band edge and create shallow traps that reduce µFET of the device and enlarge the subthreshold regime (from Vturn-on to Vth). Deep traps with longer lifetimes, located far from the band edge, can capture the free carriers and create immobile charges. Therefore, the number of free carriers in the channel can be reduced by increasing the number of immobile charges present in the
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
channel. The decrease of channel current and change in Vth, that is, ΔVth, occur during device operation, in terms of hysteresis and bias-induced ΔVth.[3,18] The time scales of the trap lifetimes associated with the hysteresis and bias-induced ΔVth have been reported to be, respectively, 10–60 s (comparable to oneloop OFET measurement times) and on the order of hours.[4,18] Recent studies reported that structural defects can significantly influence µFET, but not the device stability properties.[19] The question then becomes: what are the fundamental reasons for the gate-bias stress instability? This question was able to be addressed by examining the gate-bias stress instabilities in the OFETs as a function of the applied gate-bias intensity. Figure S8 (Supporting Information) shows the transfer curves of the pentacene OFETs prepared with PMOS-, PMS-, or PFS-treated SiO2 under a sustained VG of –10, –20, –40, and –80 V for 12 h. The bias-induced ΔVth values as a function of the stress time under various applied VG are summarized in Figure 3. Under a sustained VG of –10 V, all OFETs exhibited ΔVth of less than –0.85 V, indicating that the device could tolerate gate-bias stressing at this VG value. The application of a VG stress of –20 V to the OFETs did not induce a further increase ΔVth for the PMS- and PFS-treated OFETs (–0.681 V and –0.617 V, respectively). On the other hand, for the PMOStreated OFETs, ΔVth increased from –0.83 V (at a VG of –10 V) to –1.05 V (at a VG of –20 V). Both the PMOS- and PMS-treated OFETs exhibited an abrupt increase in ΔVth under a VG stress greater than –40 V (i.e., –60 V and –80 V), and the value of ΔVth for the former exceeded that of the latter (Figure 3). By contrast, the PFS-treated OFETs showed more stable values of ΔVth, from –1.40 V (at a VG of –40 V) to –5.08 V (at a VG of –80 V), compared to the other devices, which gave –23.38 V (PMOS-) and –21.61 V (PMS-treated device) at a VG of –80 V. If the gatebias stress instability arose from pre-existing deep traps in the band gap, a significant ΔVth would occur at lower VG stresses because the carriers injected by the VG would fill the traps at the energy levels far from the band edge, thereby generating immobile charges in the channel to cause ΔVth; however, the largest ΔVth observed in our system remained at –1.05 V (for PMOS sample) until the stressed VG reached –20 V, after which ΔVth increased with VG.
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
3
www.advmat.de
COMMUNICATION
www.MaterialsViews.com
Figure 3. a–c) Threshold voltage shift (ΔVth) as a function of stress time under various applied gate-bias stress: a) PMOS, b) PMS, and c) PFS. d) ΔVth as a function of bias voltage applied for 3 h.
We speculated that the carrier transfer from the channel to the dielectric surface, as a function of VG, was an important factor determining gate-bias stress instability in the OFETs. During a prolonged period of gate-bias stress, free carriers (holes) in the channel of our OFETs were forced to migrate to the localized states of the dielectric surface under the electric field perpendicular to the channel direction. As a result, immobile charges that had accumulated on the dielectric side of the interface should decrease the number of free carriers in the channel and give rise to device instability behaviors. The charge transfer would be proportional to the applied external voltage and its duration; however, an effective pathway for charge transfer must be formed by the overlap between the highest occupied molecular orbital (HOMO) levels of the semiconductor and gate dielectric layers. In this case, the energetic difference between the HOMO levels of the two layers at the interface will act as an energetic barrier to limit the charge transfer. In other words, the application of a sustained VG to the 4
wileyonlinelibrary.com
two layers at the interface, such that VG is lower than the energetic barrier and is biased to the semiconductor/gate dielectric interface, will preclude the formation of immobile charges due to carrier transfer. On the other hand, the application of a VG exceeding the energetic barrier can accelerate carrier transfer at the interface, thereby dramatically increasing the number of immobile charges in the dielectrics. Recently, Podzorov's group reported similar results from tests of the gate-bias stress instabilities in OFETs containing three organic single-crystal semiconductors and a parylene dielectric.[20] The ΔVth values measured under gate-bias stress decreased as the magnitude of the energetic barrier increased, regardless of the mobilities of the corresponding OFETs.[20] The energy barrier concept was applied to the gate-bias stress instability behavior by conducting a UPS study that investigated the electronic structures of the interface, including the HOMOs of the semiconductor and polymer dielectric surfaces. The presence of contaminations at the interface, such as
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
www.advmat.de www.MaterialsViews.com
COMMUNICATION Figure 4. a–c) Magnified view of the region of the HOMO peak on comparative valence band structures of pentacene layers deposited on PMOS(a), PMS- (b), and PFS-treated (c) surfaces. d–f) Band diagram of the interface between the pentacene and polymer layers.
the adsorption of water, oxygen, and organic molecules, can perturb the electronic structure. To avoid these contaminations, we used a UPS characterization apparatus configured such that the semiconductor deposition and UPS characterization chambers were connected under a high vacuum (10−10 Torr). The measurements revealed the energetic barrier at the interface. A pentacene layer with a different thickness (1.5, 5, 10, or 20 nm) was deposited onto each of the dielectric samples, and the corresponding UPS measurements were collected in situ. Figure 4 shows the UPS spectra of the interfaces between the pentacene and the PMOS, PMS, or PFS layers. The UPS spectra obtained at the pentacene/polymer interface were used to establish the band diagram for each interface, as shown in Figure 4d–f. The energetic barrier at the interface, which was defined as the difference between the HOMO edges of the pentacene and the polymer, was 3.35 eV for PFS, 2.08 eV for PMS, and 1.54 eV for PMOS. As expected, the PFS sample showed the highest energetic barrier, which agreed well with the gate-bias stress instability results obtained from the OFETs. Obviously, the PMS sample exhibits a higher energetic barrier than the PMOS one, although both polymers exhibit similar surface potentials, as mentioned above. The energetic barrier is closely related to the ionization energy (IE), which is the energy required to remove an electron from the molecule. After an electron is removed by a photon during the UPS experiment, the created cation can be more stabilized by the methoxy-substituent of PMOS due to the resonance effect, in which an unshared electron pair present in the oxygen of the methoxy group can be delocalized into the conjugated aromatic ring.[21] As a result, the IE of PMOS is lower than that of PMS (see Figure S9 in the Supporting Information), thereby leading to a lower energetic barrier. In conclusion, we have established the origin of the outstanding gate-bias stress stability in an OFET prepared with a fluorinated polymer dielectric under gate-bias stressing. Among the OFETs based on methoxy-, methyl-, or fluorofunctionalized polystyrene dielectric surfaces, the fluorinated polymer–based OFETs showed the most stable performance
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
under a bias stress, despite lower values of electrical properties such as µFET. The UPS measurements revealed the existence of an energetic barrier between the pentacene and each polymer dielectric. Gate-bias stress tests of the devices under various bias voltage conditions suggested that the energetic barrier affected charge transfer from the channel to the dielectric surface under gate-bias stressing. The OFETs prepared with a fluorinated-polymer dielectric yielded the highest energetic barrier, reduced the density of the carriers transferred to the dielectric surface, and improved the gate-bias stress instability. Consequently, OFETs with a fluorinated-polymer dielectric, owing to its high energetic barrier for charge transfer, show excellent gate-bias stress stability under harsh conditions (VG = –80 V for up to 12 h), while preserving the relatively low µFET of 0.33 cm2 V–1 s–1.
Experimental Section Materials and Sample Preparation: Highly doped n-type (100) Si wafers with 300 nm thick thermally grown SiO2 layers were used as the substrates. PMOS (MW = 23780, Polymer Source, Inc.), PMS (MW = 72000, Aldrich), and PFS (MW = 29000, Polymer Source, Inc.) were used without any purification. Polymer solutions, 1 wt% PMOS, 0.2 wt% PMS in toluene (Aldrich), and 0.5 wt% PFS in 1-butanone (Aldrich), were spin-coated onto SiO2 substrates to fabricate ultrathin polymer/SiO2 bilayer dielectrics. The resulting films were annealed at 120 °C for 60 min under N2 conditions to remove residual solvents. The polymer layers on SiO2 dielectrics were characterized by ellipsometry (for layer thickness) and atomic force microscopy (AFM) (for surface roughness). Pentacene films (50 nm thick) were deposited onto the bilayer dielectrics by means of organic molecular beam deposition (deposition rate 0.1–0.2 Å s–1; vacuum pressure 10−6 Torr; substrate temperature 25 °C). Finally, the source/drain electrodes were deposited on the semiconductor films by thermal evaporation of Au through a shadow mask. Characterization: Capacitance measurements were carried out using an Agilent 4284 precision LCR meter to determine the dielectric constants of the dielectrics in a metal–insulator–metal (MIM) structure. The electrical parameters of the pentacene-based OFETs were measured using a Keithley 4200 SCS in a N2-purged glove box. The µFET and Vth
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
5
www.advmat.de www.MaterialsViews.com
COMMUNICATION
were calculated in the saturation regime (VD = –40 V) using the equation ID = µFET(CiW/2L)(VG–Vth)2. The Cis were measured using an Agilent 4284 precision LCR meter. UPS was used to characterize the various thicknesses of the pentacene (1.5, 5, 10 and 20 nm) in situ in normal emission mode at the 4D beamline in the Pohang Accelerator Laboratory in Korea.
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements J.K. and J.J. contributed equally to this work. This work was also supported by a grant from the Korea Science and Engineering Foundation (KOSEF), funded by the Korean Government (MEST) (NRF2014R1A2A1A05004993 and NRF-2014R1A1A1005896). Received: May 27, 2014 Revised: August 9, 2014 Published online:
[1] T. Sekitani, U. Zschieschang, H. Klauk, T. Someya, Nat. Mater. 2010, 9, 1015. [2] H. Klauk, U. Zschieschang, J. Pflaum, M. Halik, Nature 2007, 445, 745. [3] H. Sirringhaus, Adv. Mater. 2009, 21, 3859. [4] W. Jackson, J. Marshall, M. Moyer, Phys. Rev. B 1989, 39, 1164.
6
wileyonlinelibrary.com
[5] B. J. Jung, K. Lee, J. Sun, A. G. Andreou, H. E. Katz, Adv. Funct. Mater. 2010, 20, 2930. [6] S. Fabiano, S. Braun, M. Fahlman, X. Crispin, M. Berggren, Adv. Funct. Mater. 2014, 24, 695. [7] H. H. Choi, W. H. Lee, K. Cho, Adv. Funct. Mater. 2012, 22, 4833. [8] S. G. J. Mathijssen, M.-J. Spijkman, A.-M. Andringa, P. A. van Hal, I. McCulloch, M. Kemerink, R. A. J. Janssen, D. M. de Leeuw, Adv. Mater. 2010, 22, 5105. [9] W. L. Kalb, T. Mathis, S. Haas, A. F. Stassen, B. Batlogg, Appl. Phys. Lett. 2007, 90, 092104. [10] J. Kim, S. H. Kim, T. K. An, S. Park, C. E. Park, J. Mater. Chem. C 2013, 1, 1272. [11] B. Lee, Y. Chen, D. Fu, H. T. Yi, K. Czelen, H. Najafov, V. Podzorov, Nat. Mater. 2013, 12, 1125. [12] P. J. Cumpson, Surf. Interface Anal. 2001, 31, 23. [13] S. Kobayashi, T. Nishikawa, T. Takenobu, S. Mori, T. Shimoda, T. Mitani, H. Shimotani, N. Yoshimoto, S. Ogawa, Y. Iwasa, Nat. Mater. 2004, 3, 317. [14] M. Park, J. Jang, S. Park, J. Kim, J. Seong, J. Hwang, C. E. Park, Appl. Phys. Lett. 2012, 100, 102110. [15] P. Kirsch, Modern Fluoroorganic Chemistry: Synthesis, Reactivity, Applications, Wiley-VCH, Weinheim, Germany 2005, Ch. 1.4. [16] S. Y. Yang, K. Shin, C. E. Park, Adv. Funct. Mater. 2005, 15, 1806. [17] A. Bolognesi, M. Berliocchi, M. Manenti, A. DiCarlo, P. Lugli, K. Lmimouni, C. Dufour, IEEE Trans. Electron Devices 2004, 51, 1997. [18] G. Gu, M. G. Kane, J. E. Doty, A. H. Firester, Appl. Phys. Lett. 2005, 87, 243512. [19] T. Miyadera, S. D. Wang, T. Minari, K. Tsukagoshi, Y. Aoyagi, Appl. Phys. Lett. 2008, 93, 033304. [20] B. Lee, A. Wan, D. Mastrogiovanni, J. Anthony, E. Garfunkel, V. Podzorov, Phys. Rev. B 2010, 82, 085302. [21] F. A. Carey, Organic Chemistry, 4th ed., McGraw-Hill, New York 2000, pp. 443–486.
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
COMMUNICATION
The Origin of Excellent Gate-Bias Stress Stability in Organic Field-Effect Transistors Employing Fluorinated-Polymer Gate Dielectrics Jiye Kim, Jaeyoung Jang, Kyunghun Kim, Haekyoung Kim, Se Hyun Kim,* and Chan Eon Park* Over the past several decades, organic field-effect transistors (OFETs) have emerged as promising devices for applications in flexible displays, radio-frequency identification tags, and chemical or biological sensing.[1,2] The gate-bias stress instability, which decreases the current in a channel and shifts the threshold voltage (Vth) under an applied bias, has presented a significant barrier to commercializing OFETs.[3] The gate-bias stress instability in amorphous Si-based devices arises from charge trapping in dangling bond defects and can be analyzed using a stretched exponential function.[4] Although the OFET instability behavior can be satisfactorily fit to these quantitative functions, the detailed mechanisms underlying the behavior remain unclear. Previous studies aimed at understanding the gate-bias stress instability in OFETs have shown that the instability may be influenced by the following factors: 1) the environment (e.g., water molecules), 2) charge trapping in the semiconductor layer, the dielectric layer, or at the interface between the two, and 3) charge injection from the gate into the dielectric layer.[5–8] The utilization of fluorinated polymer dielectrics has enabled OFETs to achieve good stability against sustained gate-bias stress.[9] It is generally accepted that the high stability of these OFETs results from the extremely hydrophobic nature of the fluorine functional groups. The highly water-repellent character of the fluorine functional groups suppresses trap formation in the semiconductor/dielectric interface and prevents the adsorption of water/oxygen molecules that potentially induce charge
J. Kim, Dr. J. Jang, K. Kim, Prof. C. E. Park POSTECH Organic Electronics Laboratory Department of Chemical Engineering Pohang University of Science and Technology (POSTECH) 77 Cheongam-Ro, Nam-Gu, Pohang, Gyungbuk 790-784, Republic of Korea E-mail: [email protected] Prof. H. Kim School of Materials Science and Engineering Yeungnam University 280 Daehak-Ro, Gyungsan, Gyeongbuk 712-749, Republic of Korea Prof. S. H. Kim Department of Nano Medical and Polymer Materials Yeungnam University 280 Daehak-Ro, Gyungsan, Gyeongbuk 712-749, Republic of Korea E-mail: [email protected]
DOI: 10.1002/adma.201402363
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
trapping.[9] Recently, our group demonstrated decent levels of gate-bias stress stability of OFETs using less-hydrophobic fluorinated polymer dielectrics.[10] These results imply that the hydrophobicity of the dielectric surface is not the only factor affecting the gate-bias stress instability behavior in OFETs. To reach excellent levels of gate bias-stress stability, it is therefore important to understand the mechanisms that contribute to charge trapping under a gate bias-stress in OFETs prepared with hydrophobic fluorinated gate dielectrics. In the study reported here, we examined the origins and mechanisms underlying the gate-bias stress instabilities observed in OFETs by quantitatively investigating both the physico-chemical properties and the electronic structures of the interfaces between p-type pentacene layers and a series of hydrophobic polymer dielectrics containing methoxy-, methyl-, or fluoro-functionalized polystyrene moieties. We demonstrated the existence of an energetic barrier to charge trapping related to the gate-bias stress instability at the semiconductor/ gate dielectric interface. This energetic barrier concept was supported both by the gate-bias stress instability tests, performed over a range of applied voltage levels and durations, and by the electronic structures of the semiconductor/gate dielectric interface, as characterized by ultraviolet photoemission spectroscopy (UPS). Figure 1a shows the chemical structures of the dielectric polymer materials used in this work: poly(4-methoxystyrene) (PMOS), poly(4-methylstyrene) (PMS), and poly(pentafluorostyrene) (PFS). As shown in the device structure, the gate dielectrics combined topmost ultrathin polymer (ca. 10 nm) and 300 nm-thick thermally grown SiO2 layers to rule out charge injection effects from the gate into the dielectric bulk (Figure 1c). All these bilayer gate dielectrics showed smooth and featureless surface morphologies (Figure S1a–c, Supporting Information), and similar capacitances (ca. 10 nF cm–2). The dielectric constants (k) of the polymer layers were 3.24, 2.62, and 2.64 for PMOS, PMS, and PFS, respectively. The surface potentials for the polymer surfaces were characterized by secondary electron emission spectra (Figure 1b). The onset of the secondary electrons, which corresponded to the surface potential of the polymer surface, was determined by extrapolating two solid lines from the background and straight onsets of each spectrum. As shown in Figure 1b, the kinetic energies for the onsets of the secondary electrons followed the order PFS (5.78 eV) > PMOS (5.34 eV) > PMS (5.27 eV). Higher kinetic energies indicate a higher surface potential, namely, a stronger
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
1
www.advmat.de
COMMUNICATION
www.MaterialsViews.com
Figure 1. a) Chemical structures of dielectric polymer materials. b) Secondary electron emission of PMOS, PMS, and PFS films on Au substrates. c) Schematic diagram of a top-contact OFET. d) Transfer characteristics of OFETs employing polymer-treated SiO2 dielectrics, and e) the corresponding parameters µFET and Vth.
electron-withdrawing character. The atom with the highest electronegativity, fluorine, produces a C–F bond with the largest dipole moment (compared to C–O and C–H), leading to a high surface potential at the PFS surface.[11] Interestingly, the difference of surface potential between PMOS and PMS was quite small (ca. 0.07 eV), even though the methoxy-substituent is more polar than the methyl one. This means that the differing effects that the methoxy- and methyl-substituents have on the surface potential are much more minor than expected. A possible explanation is that the oxygen atom in the methoxy-substituent could be “blocked” from the surface by the pendant methyl group. Generally, UPS measurement gives information related to the electronic structures of materials in the proximity of the corresponding surface (the electron inelastic mean free path is about 5–10 Å).[12] Therefore, pendant methyl groups pointing out to the surface are likely to have a significant influence on the surface potential of PMOS. The presence of molecular dipoles at the semiconductor/gate dielectric interface modulated the charge carrier density in the channel of the OFET and tailored the electrical parameters, such as the field-effect mobility (µFET), turn-on voltage (Vturn-on), and Vth.[13,14] Another factor that contributes to the dielectric surface properties is the surface energy (γs), which provides a direct indication of the intermolecular forces. PFS-, PMS-, and PMOStreated bilayer dielectrics showed γs values of 30.88, 42.24, and 48.48 mJ m−2, respectively (Table S1, Supporting Information). Although the PFS exhibited a high surface potential, the inherent characteristics of fluorine (such as the small atomic radius, comparable to that of hydrogen, and the lowest polarizability among all atoms) produced a nonpolar or weakly interactive surface.[11,15] These factors explain why the PFS surface displayed the lowest value of γs. In general, the γs value of 2
wileyonlinelibrary.com
dielectrics has been a critical factor for determining the crystal growth of overlying organic semiconductors, particularly by generating competing interactions between the semiconductor and the dielectric surface during the first seeding stage.[16] PMOS and PMS dielectrics with γs values comparable to that of the pentacene crystal planes (48.0 mJ m−2) were found to induce the “layer and island” growth mode (“Stranski–Krastanov mode”) of pentacene. By contrast, the three-dimensional (3D) pentacene islands on the PFS dielectric with the lower γs value displayed a Volmer-Weber growth mode (see the Supporting Information). Consequently, the pentacene films grown on the PMOS and PMS dielectrics showed terrace-like crystals with an average grain size of ca. 1.7 µm and ca. 1.3 µm, respectively, whereas those on the PFS surfaces showed granular pentacene grains with smaller grain sizes (200–300 nm) (Figure S1g–i in the Supporting Information). The 2D grazing incidence X-ray diffraction (GIXD) pattern of the pentacene film supported the growth of smaller crystals on the PFS dielectric (Figure S2c, Supporting Information). Clear (00l)* reflections along the qz direction and in-plane reflections were observed together with more scattering along the Debye ring, which indicates the presence of the bulk phase of the pentacene film. Figure 1d shows the drain current–gate voltage (ID–VG) transfer characteristics of top-contact pentacene OFETs employing PMOS-, PMS-, and PFS-treated SiO2 bilayer dielectrics. The electrical characteristics of these OFETs are summarized in Figure 1e. Although PFS samples showed the fastest Vturn-on (ca. 0 V, see Table S2 in the Supporting Information), the µFET of PMS samples exceeded those of other samples and reached values as high as 1.07 cm2 V–1 s–1, whereas the PFS sample yielded a lower µFET of 0.33 cm2 V–1 s–1. The electronwithdrawing properties of the PFS surface (due to the highest
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
www.advmat.de www.MaterialsViews.com
COMMUNICATION Figure 2. Transfer characteristics under nitrogen conditions of OFETs containing a) PMOS, b) PMS, and c) PFS dielectric surfaces before, during, and after an applied gate bias stress of VG = –60 V (VD = 0) for 12 h.
surface potential) induced extra holes in the off-regime to balance charge neutrality, leading to faster Vturn-on of the device compared with other devices. The unfavorable growth of pentacene film on the PFS surface should produce trap states at the channel and reduce µFET for the PFS-based OFET. Interestingly, the device stabilities (e.g., hysteresis and gate-bias stress stability) in the corresponding OFETs show a different tendency to µFET. All devices tested exhibited negligible hysteresis (see Figure 1d). In addition, the application of a sustained VG of –60 V (VD = 0 V) for 12 h to each of the three devices yielded ΔVth values after the gate-bias stress of –13.14 V (PMOS-), –9.28 V (PMS-), and –5.05 V (PFS-based OFETs) (Figure 2). These results are rather counterintuitive because the PFS-based OFET exhibited better device stability than the other samples, despite having the largest numbers of traps and the lowest µFET. To obtain more insight into the effect of the surface of the fluorinated gate dielectric on the gate-bias stress stability, we performed additional experiments with different device geometry and gate dielectric/semiconductor combinations: 1) top-gate/ bottom-contact pentacene OFETs, 2) bottom-gate OFETs with solution-processed semiconductor showing similar crystalline morphologies regardless of different dielectric surfaces, and 3) bottom-gate pentacene OFETs with aliphatic self-assembled monolayer treated dielectrics (Figures S3–S7 in the Supporting Information). This set of experiments revealed that OFETs with fluorinated gate dielectric surfaces exhibit superior gate-bias stress stability. The inherent characteristics of traps in OFETs can be characterized according to the state lifetime or the energetic position relative to the band edge. Shallow traps with short lifetimes (10−3–10−6 s), distributed near the band edge, can disturb the transport of free carriers in the channel.[17] Structural defects (e.g., misorientations, voids, and grain boundaries) or polar dielectric functionalities can broaden the density of states at the band edge and create shallow traps that reduce µFET of the device and enlarge the subthreshold regime (from Vturn-on to Vth). Deep traps with longer lifetimes, located far from the band edge, can capture the free carriers and create immobile charges. Therefore, the number of free carriers in the channel can be reduced by increasing the number of immobile charges present in the
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
channel. The decrease of channel current and change in Vth, that is, ΔVth, occur during device operation, in terms of hysteresis and bias-induced ΔVth.[3,18] The time scales of the trap lifetimes associated with the hysteresis and bias-induced ΔVth have been reported to be, respectively, 10–60 s (comparable to oneloop OFET measurement times) and on the order of hours.[4,18] Recent studies reported that structural defects can significantly influence µFET, but not the device stability properties.[19] The question then becomes: what are the fundamental reasons for the gate-bias stress instability? This question was able to be addressed by examining the gate-bias stress instabilities in the OFETs as a function of the applied gate-bias intensity. Figure S8 (Supporting Information) shows the transfer curves of the pentacene OFETs prepared with PMOS-, PMS-, or PFS-treated SiO2 under a sustained VG of –10, –20, –40, and –80 V for 12 h. The bias-induced ΔVth values as a function of the stress time under various applied VG are summarized in Figure 3. Under a sustained VG of –10 V, all OFETs exhibited ΔVth of less than –0.85 V, indicating that the device could tolerate gate-bias stressing at this VG value. The application of a VG stress of –20 V to the OFETs did not induce a further increase ΔVth for the PMS- and PFS-treated OFETs (–0.681 V and –0.617 V, respectively). On the other hand, for the PMOStreated OFETs, ΔVth increased from –0.83 V (at a VG of –10 V) to –1.05 V (at a VG of –20 V). Both the PMOS- and PMS-treated OFETs exhibited an abrupt increase in ΔVth under a VG stress greater than –40 V (i.e., –60 V and –80 V), and the value of ΔVth for the former exceeded that of the latter (Figure 3). By contrast, the PFS-treated OFETs showed more stable values of ΔVth, from –1.40 V (at a VG of –40 V) to –5.08 V (at a VG of –80 V), compared to the other devices, which gave –23.38 V (PMOS-) and –21.61 V (PMS-treated device) at a VG of –80 V. If the gatebias stress instability arose from pre-existing deep traps in the band gap, a significant ΔVth would occur at lower VG stresses because the carriers injected by the VG would fill the traps at the energy levels far from the band edge, thereby generating immobile charges in the channel to cause ΔVth; however, the largest ΔVth observed in our system remained at –1.05 V (for PMOS sample) until the stressed VG reached –20 V, after which ΔVth increased with VG.
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
3
www.advmat.de
COMMUNICATION
www.MaterialsViews.com
Figure 3. a–c) Threshold voltage shift (ΔVth) as a function of stress time under various applied gate-bias stress: a) PMOS, b) PMS, and c) PFS. d) ΔVth as a function of bias voltage applied for 3 h.
We speculated that the carrier transfer from the channel to the dielectric surface, as a function of VG, was an important factor determining gate-bias stress instability in the OFETs. During a prolonged period of gate-bias stress, free carriers (holes) in the channel of our OFETs were forced to migrate to the localized states of the dielectric surface under the electric field perpendicular to the channel direction. As a result, immobile charges that had accumulated on the dielectric side of the interface should decrease the number of free carriers in the channel and give rise to device instability behaviors. The charge transfer would be proportional to the applied external voltage and its duration; however, an effective pathway for charge transfer must be formed by the overlap between the highest occupied molecular orbital (HOMO) levels of the semiconductor and gate dielectric layers. In this case, the energetic difference between the HOMO levels of the two layers at the interface will act as an energetic barrier to limit the charge transfer. In other words, the application of a sustained VG to the 4
wileyonlinelibrary.com
two layers at the interface, such that VG is lower than the energetic barrier and is biased to the semiconductor/gate dielectric interface, will preclude the formation of immobile charges due to carrier transfer. On the other hand, the application of a VG exceeding the energetic barrier can accelerate carrier transfer at the interface, thereby dramatically increasing the number of immobile charges in the dielectrics. Recently, Podzorov's group reported similar results from tests of the gate-bias stress instabilities in OFETs containing three organic single-crystal semiconductors and a parylene dielectric.[20] The ΔVth values measured under gate-bias stress decreased as the magnitude of the energetic barrier increased, regardless of the mobilities of the corresponding OFETs.[20] The energy barrier concept was applied to the gate-bias stress instability behavior by conducting a UPS study that investigated the electronic structures of the interface, including the HOMOs of the semiconductor and polymer dielectric surfaces. The presence of contaminations at the interface, such as
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
www.advmat.de www.MaterialsViews.com
COMMUNICATION Figure 4. a–c) Magnified view of the region of the HOMO peak on comparative valence band structures of pentacene layers deposited on PMOS(a), PMS- (b), and PFS-treated (c) surfaces. d–f) Band diagram of the interface between the pentacene and polymer layers.
the adsorption of water, oxygen, and organic molecules, can perturb the electronic structure. To avoid these contaminations, we used a UPS characterization apparatus configured such that the semiconductor deposition and UPS characterization chambers were connected under a high vacuum (10−10 Torr). The measurements revealed the energetic barrier at the interface. A pentacene layer with a different thickness (1.5, 5, 10, or 20 nm) was deposited onto each of the dielectric samples, and the corresponding UPS measurements were collected in situ. Figure 4 shows the UPS spectra of the interfaces between the pentacene and the PMOS, PMS, or PFS layers. The UPS spectra obtained at the pentacene/polymer interface were used to establish the band diagram for each interface, as shown in Figure 4d–f. The energetic barrier at the interface, which was defined as the difference between the HOMO edges of the pentacene and the polymer, was 3.35 eV for PFS, 2.08 eV for PMS, and 1.54 eV for PMOS. As expected, the PFS sample showed the highest energetic barrier, which agreed well with the gate-bias stress instability results obtained from the OFETs. Obviously, the PMS sample exhibits a higher energetic barrier than the PMOS one, although both polymers exhibit similar surface potentials, as mentioned above. The energetic barrier is closely related to the ionization energy (IE), which is the energy required to remove an electron from the molecule. After an electron is removed by a photon during the UPS experiment, the created cation can be more stabilized by the methoxy-substituent of PMOS due to the resonance effect, in which an unshared electron pair present in the oxygen of the methoxy group can be delocalized into the conjugated aromatic ring.[21] As a result, the IE of PMOS is lower than that of PMS (see Figure S9 in the Supporting Information), thereby leading to a lower energetic barrier. In conclusion, we have established the origin of the outstanding gate-bias stress stability in an OFET prepared with a fluorinated polymer dielectric under gate-bias stressing. Among the OFETs based on methoxy-, methyl-, or fluorofunctionalized polystyrene dielectric surfaces, the fluorinated polymer–based OFETs showed the most stable performance
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
under a bias stress, despite lower values of electrical properties such as µFET. The UPS measurements revealed the existence of an energetic barrier between the pentacene and each polymer dielectric. Gate-bias stress tests of the devices under various bias voltage conditions suggested that the energetic barrier affected charge transfer from the channel to the dielectric surface under gate-bias stressing. The OFETs prepared with a fluorinated-polymer dielectric yielded the highest energetic barrier, reduced the density of the carriers transferred to the dielectric surface, and improved the gate-bias stress instability. Consequently, OFETs with a fluorinated-polymer dielectric, owing to its high energetic barrier for charge transfer, show excellent gate-bias stress stability under harsh conditions (VG = –80 V for up to 12 h), while preserving the relatively low µFET of 0.33 cm2 V–1 s–1.
Experimental Section Materials and Sample Preparation: Highly doped n-type (100) Si wafers with 300 nm thick thermally grown SiO2 layers were used as the substrates. PMOS (MW = 23780, Polymer Source, Inc.), PMS (MW = 72000, Aldrich), and PFS (MW = 29000, Polymer Source, Inc.) were used without any purification. Polymer solutions, 1 wt% PMOS, 0.2 wt% PMS in toluene (Aldrich), and 0.5 wt% PFS in 1-butanone (Aldrich), were spin-coated onto SiO2 substrates to fabricate ultrathin polymer/SiO2 bilayer dielectrics. The resulting films were annealed at 120 °C for 60 min under N2 conditions to remove residual solvents. The polymer layers on SiO2 dielectrics were characterized by ellipsometry (for layer thickness) and atomic force microscopy (AFM) (for surface roughness). Pentacene films (50 nm thick) were deposited onto the bilayer dielectrics by means of organic molecular beam deposition (deposition rate 0.1–0.2 Å s–1; vacuum pressure 10−6 Torr; substrate temperature 25 °C). Finally, the source/drain electrodes were deposited on the semiconductor films by thermal evaporation of Au through a shadow mask. Characterization: Capacitance measurements were carried out using an Agilent 4284 precision LCR meter to determine the dielectric constants of the dielectrics in a metal–insulator–metal (MIM) structure. The electrical parameters of the pentacene-based OFETs were measured using a Keithley 4200 SCS in a N2-purged glove box. The µFET and Vth
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
wileyonlinelibrary.com
5
www.advmat.de www.MaterialsViews.com
COMMUNICATION
were calculated in the saturation regime (VD = –40 V) using the equation ID = µFET(CiW/2L)(VG–Vth)2. The Cis were measured using an Agilent 4284 precision LCR meter. UPS was used to characterize the various thicknesses of the pentacene (1.5, 5, 10 and 20 nm) in situ in normal emission mode at the 4D beamline in the Pohang Accelerator Laboratory in Korea.
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements J.K. and J.J. contributed equally to this work. This work was also supported by a grant from the Korea Science and Engineering Foundation (KOSEF), funded by the Korean Government (MEST) (NRF2014R1A2A1A05004993 and NRF-2014R1A1A1005896). Received: May 27, 2014 Revised: August 9, 2014 Published online:
[1] T. Sekitani, U. Zschieschang, H. Klauk, T. Someya, Nat. Mater. 2010, 9, 1015. [2] H. Klauk, U. Zschieschang, J. Pflaum, M. Halik, Nature 2007, 445, 745. [3] H. Sirringhaus, Adv. Mater. 2009, 21, 3859. [4] W. Jackson, J. Marshall, M. Moyer, Phys. Rev. B 1989, 39, 1164.
6
wileyonlinelibrary.com
[5] B. J. Jung, K. Lee, J. Sun, A. G. Andreou, H. E. Katz, Adv. Funct. Mater. 2010, 20, 2930. [6] S. Fabiano, S. Braun, M. Fahlman, X. Crispin, M. Berggren, Adv. Funct. Mater. 2014, 24, 695. [7] H. H. Choi, W. H. Lee, K. Cho, Adv. Funct. Mater. 2012, 22, 4833. [8] S. G. J. Mathijssen, M.-J. Spijkman, A.-M. Andringa, P. A. van Hal, I. McCulloch, M. Kemerink, R. A. J. Janssen, D. M. de Leeuw, Adv. Mater. 2010, 22, 5105. [9] W. L. Kalb, T. Mathis, S. Haas, A. F. Stassen, B. Batlogg, Appl. Phys. Lett. 2007, 90, 092104. [10] J. Kim, S. H. Kim, T. K. An, S. Park, C. E. Park, J. Mater. Chem. C 2013, 1, 1272. [11] B. Lee, Y. Chen, D. Fu, H. T. Yi, K. Czelen, H. Najafov, V. Podzorov, Nat. Mater. 2013, 12, 1125. [12] P. J. Cumpson, Surf. Interface Anal. 2001, 31, 23. [13] S. Kobayashi, T. Nishikawa, T. Takenobu, S. Mori, T. Shimoda, T. Mitani, H. Shimotani, N. Yoshimoto, S. Ogawa, Y. Iwasa, Nat. Mater. 2004, 3, 317. [14] M. Park, J. Jang, S. Park, J. Kim, J. Seong, J. Hwang, C. E. Park, Appl. Phys. Lett. 2012, 100, 102110. [15] P. Kirsch, Modern Fluoroorganic Chemistry: Synthesis, Reactivity, Applications, Wiley-VCH, Weinheim, Germany 2005, Ch. 1.4. [16] S. Y. Yang, K. Shin, C. E. Park, Adv. Funct. Mater. 2005, 15, 1806. [17] A. Bolognesi, M. Berliocchi, M. Manenti, A. DiCarlo, P. Lugli, K. Lmimouni, C. Dufour, IEEE Trans. Electron Devices 2004, 51, 1997. [18] G. Gu, M. G. Kane, J. E. Doty, A. H. Firester, Appl. Phys. Lett. 2005, 87, 243512. [19] T. Miyadera, S. D. Wang, T. Minari, K. Tsukagoshi, Y. Aoyagi, Appl. Phys. Lett. 2008, 93, 033304. [20] B. Lee, A. Wan, D. Mastrogiovanni, J. Anthony, E. Garfunkel, V. Podzorov, Phys. Rev. B 2010, 82, 085302. [21] F. A. Carey, Organic Chemistry, 4th ed., McGraw-Hill, New York 2000, pp. 443–486.
© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Adv. Mater. 2014, DOI: 10.1002/adma.201402363
