Letter pubs.acs.org/NanoLett
Vertical III−V Nanowire Device Integration on Si(100) Mattias Borg,† Heinz Schmid,*,† Kirsten E. Moselund,† Giorgio Signorello,† Lynne Gignac,‡ John Bruley,‡ Chris Breslin,‡ Pratyush Das Kanungo,† Peter Werner,§ and Heike Riel† †
IBM Research-Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland IBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, United States § Max Planck Institute of Microstructure Physics, Weinberg 2, 06120 Halle, Germany ‡
S Supporting Information *
ABSTRACT: We report complementary metal−oxide−semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si−InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process. KEYWORDS: Nanowires, III−V semiconductors, InAs, GaAs, Si, integration
I
particles for a limited range of growth conditions and yield.23,24 Thus, despite intensive efforts, a scalable and epitaxial integration method that provides material with sufficiently low defect densities, and is compliant with industry-standard Si(100) substrates, has yet to be demonstrated. Here we report on the local integration of InAs and GaAs vertical nanowires epitaxially grown on a variety of Si substrate orientations as well as on nanocrystalline (nc) Si, using SiO2 nanotube templates to guide the growth. Our process is completely CMOS-compatible, independent of substrate orientation and with demonstrated scalability at least down to 25 nm nanowire diameter. We determine the top-facet morphology of InAs nanowires of various crystal orientation, assess the crystal structure of [110]-oriented InAs nanowires by transmission electron microscopy (TEM), and investigate the optical properties of GaAs nanowires by photoluminescence (PL) measurements. We also demonstrate vertical Si−InAs nanowire tunnel diodes fabricated on industry-standard Si(100) substrates and evaluate the homogeneity and robustness of the method from their performance. Figure 1a−d displays scanning electron microscopy (SEM) images of InAs nanowires grown on exactly (±0.5°) oriented Si (100), (110), (111), and (112) wafers. The nanowires are vertically oriented, regardless of the substrate orientation. To accomplish this, nanowire growth was guided within SiO2
ntegration of group III−V semiconductors on Si has become a vibrant field of research because of the possibility to further improve the performance of transistors in the next generation of CMOS circuits and to integrate laser light sources on Si for on-chip optical communication.1 In particular the materials, InGaAs and InAs, which have high charge carrier mobilities and a direct bandgap, are among the most promising candidates.2 While the superior device performance of these materials over that of Si has already been demonstrated,3−5 a viable method for integrating them onto a Si platform still remains a key obstacle. Heteroepitaxy of III−V semiconductors on Si with low defect density has been pursued through the use of buffer layers,6−8 wafer bonding,9−11 and by promoting the formation of an interfacial misfit dislocation array to suppress the formation of threading dislocations.12 It is also recognized that defects stemming from the joining of dissimilar materials can be reduced by patterning the substrate in various ways. Patterned substrates can act as dislocation sinks,13 enable strain relaxation at the nanometer scale,14,15 and can be used to direct the growing crystal away from the defective heterointerface.16,17 Although the defect density is reduced with these techniques, threading dislocation densities on the order of 109 cm−2 are still reported.18 Other approaches to locally integrate III−V materials on Si are based on nanowire epitaxy using catalyst particles19,20 or selective area epitaxy.21,22 Although strain relaxation is efficient in nanowire epitaxy, III−V nanowire growth in directions other than ⟨111⟩ has only been observed by the use of catalyst © 2014 American Chemical Society
Received: December 20, 2013 Revised: March 7, 2014 Published: March 14, 2014 1914
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Figure 1. (a−d) SEM images taken at 45° tilt angle of vertical InAs nanowires grown using template-assisted epitaxy on Si nanowires on (a) [100]-, (b) [110]-, (c) [111]-, and (d) [112]-oriented Si substrates. The template has been removed in these images. (e) TEM image of GaAs nanowire grown on nc-Si nanowire. (f) Schematic illustrations of the main steps to fabricate templates on substrates with arbitrary crystal orientation. (I) Etching of Si nanowire, (II) silicon dioxide mask deposition and top opening, (III) back etching of α-Si, (IV) III−V growth in template, and (V) nanowire after removal of the template.
cleaned in a Piranha solution (90 °C) (II). The sacrificial α-Si layer is then etched away using a 25% tetramethylammonium hydroxide (TMAH) solution or alternatively a XeF2 dry etch (III). TMAH has a very low etch rate on the Si {111} planes and thus is self-terminating at the Si/α-Si interface. For substrate orientations other than Si(111), inclined {111} facets form at the floor of the templates, and a flat interface is attained only if an ESL is used or if the p-doping level of the substrate is sufficiently high to suppress wet etching.25 As a final step, the wafers are cleaned in Piranha solution and annealed at 750 °C in Ar/H2 for 30s to densify the SiO2 nanotube. Sub-40-nm nanotube templates were fabricated by etching out crystalline Si nanowires with a nominal diameter of 40 nm by ICP/RIE as described above and then thinning them down further by thermal oxidation. After opening the top of the template, the Si nanowires were back-etched using a 2% TMAH solution, which has a higher etch rate on the Si {111} planes than the standard solution. Directly before loading the wafer into the MOCVD reactor, the wafer is dipped into HF to remove the native oxide and to leave an H-terminated Si surface at the floor of the templates. InAs is then selectively grown within the templates at 520−580 °C with V/III ratios ranging from 10 to 100 (IV). The precursors used were trimethylindium (TMIn) and tertiarybutylarsenic (TBAs). For GaAs growth, a growth temperature of 650 °C and V/III ratio of 88 were used, with trimethylgallium (TMGa) and TBAs as precursors. Selected nanowires were prepared and characterized in detail by TEM and high-resolution TEM (HRTEM) at 300 keV. For the case of InAs nanowires grown on (110) Si, the nanowires were initially cross-sectioned in a direction perpendicular to the [110̅ ] using an in situ lift-out technique in a dual beam focused ion beam (DB-FIB) system. In one specific case, a sample that was initially cross-sectioned and analyzed in the TEM was then placed back in the DB-FIB and resectioned in the direction perpendicular to the [110], forming a planview (or top-down) section of the previously sectioned nanowires.26 Single GaAs nanowires were investigated by μ-PL using a spectrometer equipped with a He−Ne laser (λ = 633 nm, power < 15 μW/μm2) and a liquid-N2-cooled CCD detector.
nanotube templates, which determine the shape and direction of the nanowire crystal. After growth, the SiO2 templates were selectively removed by an HF etch. All nanowires in Figure 1 were produced using identical template fabrication processes, the only difference being the substrate orientation. In fact, as revealed by the TEM image in Figure 1e, the process even allows for nanowire growth (in this case GaAs) on nc-Si, still with a predefined vertical orientation and position. In this case, the crystalline orientation of Si at the growth interface is undefined, because of the random grain orientation of the nc-Si. Even so, the GaAs nanowire is single-crystalline, albeit with a crystallographic orientation that varies from nanowire to nanowire. This further illustrates the versatility of our approach, which enables the fabrication of aligned, single-crystalline nanowire devices on arbitrary substrates, the only requirement being the existence of a single nucleation seed in the nanotube template. To enable the growth of III−V nanowires as those shown in Figure 1, vertically oriented nanotube templates were fabricated on 2 in. Si wafers of the desired crystal orientation. The typical process is illustrated in Figure 1f and begins with the sputter deposition of a 500−800 nm thick layer of sacrificial amorphous Si (α-Si) on a Si wafer. The thickness of the α-Si layer later determines the depth of the nanotube template. Optionally, a thin (5−6 nm) SiO2 etch-stop layer (ESL) underneath the α-Si can be incorporated by plasma-enhanced chemical vapor deposition (PECVD). Electron-beam lithography is then performed using a hydrogen silsesquioxane (HSQ) negative resist to define dots with a diameter between 40 and 120 nm, marking the location and later defining the inner diameter of the templates. Inductively coupled plasma reactive-ion etching (ICP-RIE) using the HBr:O2 chemistry is then applied to etch out vertical nanowires using the HSQ hard-mask, as depicted in part I of Figure 1f. In the next step, SiO2 is deposited by PECVD at 400 °C using tetraethyl orthosilicate (TEOS) and O2 precursors. The top surface of the Si nanowires is exposed by dry-etching the top SiO2 in a CHF3/ O2 plasma while protecting the template sidewalls with photoresist. After removing the photoresist, the sample is 1915
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template-assisted epitaxy process is also a requirement for the fabrication of advanced electronic devices. In view of these benefits, we investigated the scalability of our method for growing nanowires with diameters below 40 nm. Figure 2c and d show the results of the down-scaled template fabrication and growth experiments on Si(111). Here, InAs segments with 25 nm diameter are grown in nanotube templates with an aspect ratio as high as 1:18. Even in this case do the InAs nanowires nucleate with close to 100% yield, which suggests that further down-scaling is feasible. A significant decrease in growth rate is observed in deep templates, related to a reduction in the supply of growth material with increased template aspect ratio. The top surfaces of the nanowires shown in the SEM images of Figures 1 and 2 have distinct and regular faceting. An inclined top facet structure is observed in the case of nanowires with [100], [110], and [112] orientation, whereas nanowires oriented in [111] typically exhibit a single horizontal top facet, as in our previous work.32 In Figure 3a, the top facets of a
For investigation of the electrical properties, Si(100)-InAs diodes were fabricated by etching away the empty part of the template by a timed buffered HF etch, leaving a SiO2 insulation layer on the substrate and side walls of the nanowires. Contact pads were then defined by Ti/Pd (50 nm/40 nm) evaporation and lift-off. The Si substrate back-side was metalized and used as ground, while bias was applied to the top contacts. In Figure 2a an overview image of an array of InAs nanowires in nanotube templates on Si(100) is shown. In each template,
Figure 3. Top-facet morphology of InAs nanowires with (a−b) [110] and (c−d) [111] growth direction. Each SEM image is paired with a schematic image to illustrate the planes constituting the top-facets. SEM images are taken at (a) 90°, (b) 45°, and (c−d) 60° tilt angle, respectively. (a) Nanowire with inclined top-facet morphology comprising two {110} facets and one (111)B facet. (b) Nanowire with flat top-facet morphology consisting only of {110} facets, one of which is horizontal. (c) Nanowire with [111]B growth direction. (d) Nanowire with [111]A growth direction exhibiting a (111)B facet inclined by 70.5° to the plane of the substrate.
Figure 2. (a−b) SEM image taken at 60° tilt angle of InAs nanowires grown in nanotube templates on a Si(100) substrate at low and high magnification, respectively. (c) SEM image of InAs nanowires grown in 25-nm-diameter nanotube templates on Si(111) taken at 60° tilt angle. The InAs segments are colored for better visibility. (d) Close-up SEM image at 85° tilt angle of a single InAs nanowire from (c).
nanowire grown on a [110]-oriented Si substrate is displayed. The inclined planes are identified, by measuring their angle to the wafer flat and the substrate surface normal, as being one {111} and two {110} planes. Because the As-terminated {111} facet (B) facet is more stable than the In-terminated {111} facet (A) for these growth conditions,33 the observed {111} facet is indexed as [111]B. In addition, we find that a significant fraction (10−15%) of the [110]-oriented InAs nanowires exhibit a horizontal top facet, often with additional inclined {110} facets. An example of such a nanowire is shown in Figure 3b. On Si(111), the polarity of the III−V materials allow two distinct orientations for epitaxial III−V growth; either [111]A or [111]B orientation. With appropriate surface preparation, the preferred orientation can be tuned.34 The distinction between the two crystal polarities is revealed by the differences in the morphology of the top facets; see Figure 3c−d. We either observe a single horizontal [111]B top facet (Figure 3c) or an inclined top facet morphology similar to those of the other substrate orientations. The inclined case belongs to a crystal with [111]A orientation, which is even clearer in those cases where the crystal extends beyond the confinement of the template. The [111]B-oriented nanowire then evolves into a
InAs has nucleated and filled up the width of the nanotube. There is no crystal growth outside the templates, highlighting the selectivity of the growth process and also that InAs is grown preferentially at the desired locations. Regardless of substrate orientation, the yield of successful InAs nucleation on the wafer can be close to 100%. However, the yield strongly depends on the growth and sample conditions. To achieve a high yield of nanowire growth, a molar flow of TMIn above 2 μmol/min at growth temperatures up to 550 °C is necessary. Above this temperature, a higher TMIn flow is needed to compensate for the high rate of In desorption from Si surfaces.27 High selectivity between the intended nanowire growth and the parasitic growth on the masked area is readily obtained when using a clean growth mask and low precursor flows. In the highly lattice-mismatched Si-InAs system (11.6% mismatch), the high level of strain is typically relieved by forming a dislocation network at the interface.12,28,29 If the diameter of the junction were to be scaled down, strain partitioning across the heterojunction could reduce the misfit dislocation density.14,30,31 In addition, down-scaling of the 1916
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hexagonal shape (Figure 3c), whereas the [111]A-oriented nanowire changes direction and evolves into a hexagonal shape inclined by 70.5° to the substrate normal (Figure 3d). Because of the crystal symmetry, equivalent structures in this case are found by rotation in steps of 120° around the surface normal. Likewise, for [100]- and [110]-oriented nanowires equivalent structures are observed with rotation in steps of 90° and 180°, respectively (see Supporting Information for details on the rotational symmetry of the top facet morphology). The fact that in all cases we observe consistent top facet morphologies is an indication that each InAs nanowire crystal originates from a single nucleus in each template. This is a significant finding as it means that here antiphase boundary (APB) defects, typically an important concern for III−V integration on Si, could be suppressed. APB defects are formed when two nuclei with different polarity or from separate surface steps merge, and in planar heteroepitaxy great care has to be taken to limit the APB density.35−37 In the nanotube templates, the merging of nuclei and the associated creation of defects is avoided because the diameter of the exposed Si in each template is much smaller than the mean adatom diffusion length, so that as soon as the first nucleation event occurs it will consume all available material within the template, thus preventing further nucleation events. This model was tested by performing very short growth runs, where indeed a single small crystallite is found within each template. Likewise, a single nucleus per mask opening was previously reported by Kondo et al.38 and Björk et al.22 by selective area epitaxy. Summarizing the above findings, the template-assisted epitaxy technique (1) enables vertical nanowire growth independent of the substrate orientation, (2) is scalable at least down to 25 nm diameter, and (3) enables growth from a single nucleus per template, thus likely avoiding the problem of APB defect formation. In contrast to other fabrication methods, the side-wall surfaces of the nanowires in this work are protected by the template wall and are therefore not exposed to the ambient air after growth. Thus, the properties of the side-wall surfaces may differ significantly from those of other types of nanowires. This is especially true for oxidized GaAs surfaces, which typically have a high surface state density, leading to strong nonradiative recombination processes.39−41 We have therefore evaluated the optical properties of single GaAs nanowires in nanotube templates on Si(110) substrates. In total, room temperature PL measurements of 65 individual GaAs nanowires were collected. When excited by laser light, the nanowires exhibit stable luminescence, and there is no sign of degradation even after several weeks of exposure in air. In Figure 4, PL spectra of a representative GaAs nanowire before and after template removal are displayed. To allow a quantitative comparison, both spectra were normalized so that the Si Raman optical phonon peaks (521 cm−1) have equal intensity in both cases. The PL intensity after template removal dropped by about a factor of 5 for the particular nanowire shown, but even larger differences were observed. Although this could in part be explained by a difference in light coupling strengths, it is likely that the GaAs/SiO2 interface provides enhanced surface passivation. An investigation of the crystal structure of InAs nanowires grown on Si(110) was performed by TEM/HRTEM. From the TEM images in Figure 5 and the diffraction patterns included, it is clear that the nanowires are single-crystalline and have a direct epitaxial relationship to the Si substrate. The spacing
Figure 4. Room-temperature PL spectra of single GaAs nanowires on Si(110). Comparison of PL spectra from an as-grown nanowire in a nanotube template and after removal of the template. The intensity of the Si Raman optical phonon peak (521 cm−1) was used for data normalization.
between diffraction spots originating from the InAs nanowires correspond to bulk values for InAs, and the nanowires contain a high density of planar defects. These defects are most likely stacking faults, as is typical for nanoscale selective area epitaxy.22,42−45 Using the acquired HRTEM data it cannot be completely ruled out that they are not APB defects, although this is unlikely due to the consistent top facet morphologies and uniform defect density observed throughout the nanowires. We will therefore denote these defects as stacking faults in the following. Misfit dislocations are expected to form at the Si/InAs heterojunction because of the large lattice-mismatch between the materials (11.6%). Surprisingly, misfit dislocations are not visible in standard TEM images, possibly because they are hidden by the interface roughness. By geometric phase analysis (GPA) of cross-sectional HRTEM images we have measured the mismatch across the heterojunction, which we find to be 11.3% ± 0.6% over a distance of 1 nm indicating that the InAs nanowire is fully relaxed (see the Supporting Information for details on the determination of the strain relaxation). There are occasional local high strain points at the heterointerface, revealed by GPA in Figure 5e−f, which are confirmed to be misfit dislocations by Burger circuit loop analysis. The number of observed misfit dislocations is approximately 15 across the nanowire. In contrast to the case of [111]-oriented nanowires, it is possible that here the mismatch is in part relieved by stacking faults that originate from the heterojunction. Despite the presence of misfit dislocations we do not observe threading dislocations in any of the investigated nanowires. Since threading dislocations are a major concern for III−V integration on Si, the absence of dislocation threading here is of great significance. In nanowires with inclined top facets (Figure 5a), stacking-faults are seen edge-on in the [11̅0] viewing direction and are oriented parallel to the inclined (111) or (111)̅ planes. In contrast, InAs nanowires with horizontal top facets appear stacking-fault-free when viewed in the [11̅0] direction (Figure 5b). However, when viewed along the [110] direction in cross-sectional images26 (the planview image in Figure 5d), the (111̅ )-oriented stacking faults that run vertically through the entire length of the nanowire become visible. The observation of differences in stacking-fault orientation can explain the existence of the two 1917
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To investigate the suitability of template-assisted epitaxy for device fabrication, we fabricated vertical Si/InAs tunnel diodes from InAs nanowires grown in templates on highly p-doped Si(100) substrates (NA = 2 × 1020 cm−3). The nanowires used were 50 nm in diameter and Si-doped (n-type) during growth using Si2H6 (estimated ND = 1 × 1018 cm−3).46 In Figure 6 the
Figure 6. (a−b) Semilogarithmic I−V characteristics of 50-nmdiameter Si(100)-InAs nanowire tunnel diodes fabricated. (a) Semilogarithmic I−V plot of devices containing 1, 4, 25, or 49 contacted nanowires. The current scales well with the number of nanowires, as is clear from (b) where the current densities of representative devices with varying numbers of nanowires are shown. The inset in (b) is a schematic of the device structure. (c) SEM image (70° tilt) of a nanowire from the same wafer before metallization and (d) SEM image of a 49 nanowire device after metallization. The inset in (d) shows an overview image of the complete contact pad.
Figure 5. TEM images of InAs nanowires grown on a Si(110) substrate with the template removed. (a) An InAs nanowire viewed in the [110̅ ] direction with an inclined top-facet morphology containing a high concentration of stacking-faults. (b) InAs nanowire viewed in the [110̅ ] direction with horizontal top-facets that exhibits vertically oriented stacking-faults only visible in the cross-sectional image (d). Insets in (a) and (b) are diffraction patterns for the parts of the images indicated by the arrows. (c, d) HRTEM images of nanowires viewed in the [110] direction (planview from cross-section), corresponding to the same nanowires in (a) and (b), respectively. The nanowire crosssection is truncated on the top and bottom because of the vertical cut, which was done first. The cross-section samples were obtained at positions in the lower half of the InAs nanowire, and were approximately 100 nm thick. In (c) part of the Si stem is included, causing a Moiré pattern due to the different lattice parameters of Si and InAs. (e) HRTEM image of the Si/InAs heterojunction of a [110]-oriented nanowire and (f) GPA lattice mismatch map of the same picture, in which high strain regions are indicated by arrows. The inset displays a fast Fourier transform filtered high-resolution image of a single such region, where a Burgers circuit loop has been done to verify the presence of a misfit dislocation (black arrow points to the dislocation core).
current−voltage (I−V) characteristics of 50-nm-diameter Si(100)-InAs diodes with varying number of contacted nanowires is shown. The I−V curves exhibit typical tunnel diode characteristics,47 such as a high subexponential current in reverse bias (VDS > 0 V), a peak in current at low forward bias (VDS ∼ −0.1 V) followed by an exponentially increasing diode current at higher forward bias (VDS < −0.4 V). The region of negative differential resistance (NDR) is masked by a high level of excess current, which is attributed to defect states located at the heterojunction. As seen in Figure 6b, the current levels scale well with respect to the number of contacted nanowires, both in terms of current level and curve shape. The average current level at 0.5 V is roughly 150 kA/cm2, normalized to the InAs nanowire cross-sectional area. This value is comparable to the current density level of Si/InAs tunnel diodes with similar doping levels fabricated on Si(111) using other techniques.48 Because of the template-assisted nanowire growth, a high uniformity of the measured devices is achieved, which is very promising in view of implementations into logic circuits where reproducibility and uniformity are vital.
distinct facet morphologies (Figure 3c and d). Similarly, in the case of GaAs nanowires, it can explain an observed difference in PL line-shapes depending on the top facet morphology (see Supporting Information for details on the correlation between PL line shape and nanowire morphology). 1918
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(4) Egard, M.; Ohlsson, L.; Borg, B. M.; Lenrick, F.; Wallenberg, R.; Wernersson, L.-E.; Lind, E. In Electron Devices Meeting (IEDM), 2011: IEEE International: Washington, DC, 2011; pp 13.2.1−13.2.4. (5) Gu, J. J.; Wang, X. W.; Shao, J.; Neal, A. T.; Manfra, M. J.; Gordon, R. G.; Ye, P. D. 2012 Int. Electron Devices Meeting 2012, 23.7.1−23.7.4. (6) Ghalamestani, S. G.; Berg, M.; Dick, K. A.; Wernersson, L.-E. J. Cryst. Growth 2011, 332, 12−16. (7) Fang, S. F.; Adomi, K.; Iyer, S.; Morkoç, H.; Zabel, H.; Choi, C.; Otsuka, N. J. Appl. Phys. 1990, 68, R31−R58. (8) Tsaur, B.-Y.; McClelland, R. W.; Fan, J. C. C.; Gale, R. P.; Salerno, J. P.; Vojak, B. A.; Bozler, C. O. Appl. Phys. Lett. 1982, 41, 347. (9) Ford, A. C.; Yeung, C. W.; Chuang, S.; Kim, H. S.; Plis, E.; Krishna, S.; Hu, C.; Javey, A. Appl. Phys. Lett. 2011, 98, 113105. (10) Czornomaz, L.; Daix, N.; Caimi, D.; Sousa, M.; Erni, R.; Rossell, M. D.; El-Kazzi, M.; Rossel, C.; Marchiori, C.; Uccelli, E.; Richter, M.; Siegwart, H.; Fompeyrine, J. In 2012 International Electron Devices Meeting; IEEE: San Francisco, CA, 2012; pp 23.4.1−23.4.4. (11) Bolkhovityanov, Y. B.; Pchelyakov, O. P. Open Nanosci. J. 2009, 3, 20−33. (12) Huang, S.; Balakrishnan, G.; Huffaker, D. L. J. Appl. Phys. 2009, 105, 103104. (13) Fitzgerald, E. A.; Watson, G. P.; Proano, R. E.; Ast, D. G.; Kirchner, P. D.; Pettit, G. D.; Woodall, J. M. J. Appl. Phys. 1989, 65, 2220. (14) Zubia, D.; Hersee, S. D. J. Appl. Phys. 1999, 85, 6492. (15) Luryi, S.; Suhir, E. Appl. Phys. Lett. 1986, 49, 140. (16) Rathman, D. D.; Silversmith, D. J.; Burns, J. A. J. Electrochem. Soc. 1982, 129, 2303−2306. (17) Nishinaga, T. J. Cryst. Growth 2002, 237−239, 1410−1417. (18) Waldron, N.; Wang, G.; Nguyen, N. D.; Orzali, T.; Merckling, C.; Brammertz, G.; Ong, P.; Winderickx, G.; Hellings, G.; Eneman, G.; Caymax, M.; Meuris, M.; Horiguchi, N.; Thean, A. ECS Trans. 2012, 45, 115−128. (19) Plissard, S.; Larrieu, G.; Wallart, X.; Caroff, P. Nanotechnology 2011, 22, 275602. (20) Alarcón-Lladó, E.; Conesa-Boj, S.; Wallart, X.; Caroff, P.; Fontcuberta I Morral, A. Nanotechnology 2013, 24, 405707. (21) Tomioka, K.; Kobayashi, Y.; Motohisa, J.; Hara, S.; Fukui, T. Nanotechnology 2009, 20, 145302. (22) Björk, M. T.; Schmid, H.; Breslin, C. M.; Gignac, L.; Riel, H. J. Cryst. Growth 2012, 344, 31−37. (23) Krishnamachari, U.; Borgström, M.; Ohlsson, B. J.; Panev, N.; Samuelson, L.; Seifert, W.; Larsson, M. W.; Wallenberg, L. R. Appl. Phys. Lett. 2004, 85, 2077. (24) Wang, J.; Plissard, S. R.; Verheijen, M. A.; Feiner, L.-F.; Cavalli, A.; Bakkers, E. P. A. M. Nano Lett. 2013, 13, 3802−6. (25) Steinsland, E.; Nese, M.; Hanneborg, A.; Bernstein, R. W.; Sandmo, H.; Kittilsland, G. In Solid-State Sensors and Actuators 1995, International Conference on, Stockholm, 1995; pp 190−193. (26) Gignac, L. M.; Mittal, S.; Bangsaruntip, S.; Cohen, G. M.; Sleight, J. W. Microsc. Microanal. 2011, 17, 889−95. (27) Kuyyalil, J.; Govind; Kumar, M.; Shivaprasad, S. M. Surf. Sci. 2010, 604, 1972−1977. (28) Bessire, C. D.; Björk, M. T.; Schmid, H.; Schenk, A.; Reuter, K. B.; Riel, H. Nano Lett. 2011, 11, 4195−9. (29) Tomioka, K.; Yoshimura, M.; Fukui, T. Nano Lett. 2013, 13, 5822−5826. (30) Zaumseil, P.; Kozlowski, G.; Schubert, M. A.; Yamamoto, Y.; Bauer, J.; Schülli, T. U.; Tillack, B.; Schroeder, T. Nanotechnology 2012, 23, 355706. (31) Montalenti, F.; Salvalaglio, M.; Marzegalli, A.; Zaumseil, P.; Capellini, G.; Schülli, T. U.; Schubert, M. A.; Yamamoto, Y.; Tillack, B.; Schroeder, T. Phys. Rev. B 2014, 89, 014101. (32) Das Kanungo, P.; Schmid, H.; Björk, M. T.; Gignac, L. M.; Breslin, C.; Bruley, J.; Bessire, C. D.; Riel, H. Nanotechnology 2013, 24, 225304.
In conclusion, we have demonstrated vertical III−V nanowire growth on [100]-, [110]-, [112]-, and [111]-oriented Si substrates and on nc-Si through the use of SiO2 nanotube templates. The template fabrication process is fully CMOScompatible and scalable at least down to 25 nm nanowire diameter. The consistent faceting observed on the top of all nanowires implies well-defined growth planes and an absence of APB defects. Moreover, no threading dislocations are observed in the InAs nanowires despite the large lattice-mismatch between InAs and Si, although a high density of stacking-faults is observed. GaAs nanowires in templates exhibit stable roomtemperature PL, which is stronger for nanowires surrounded by a template. The template-assisted InAs nanowire growth exhibits a high yield and uniformity across full 2 in. wafers, which is also reflected in a consistent and scalable device performance of vertical nanowire tunnel diodes fabricated on Si(100). We believe that template-assisted epitaxy provides a viable path toward large-scale local integration of III−V materials on Si for integrated high-speed electronic and optoelectronic devices.
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ASSOCIATED CONTENT
S Supporting Information *
Details on the rotational symmetry of the top facet morphology, the process to extract the peak position from the photoluminescence measurement data, and the determination of the lattice misfit profile across the Si/InAs heterojunction. This material is available free of charge via the Internet at http://pubs.acs.org.
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AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected]. Present Address
P.D.K.: Paul Scherrer Institut, 5232 Villigen PSI, Switzerland Author Contributions
H.S., M.B., and H.R. have conceived and designed the experiment. The template and device processing was done by M.B., K.E.M., and H.S., the growth experiments by M.B. and P.D.K., optical measurements by G.S., HRTEM investigation by L.G., J.B., C.B., and P.W. The manuscript was written by M.B. and H.S., with contributions of all authors, and all authors have given approval to the final version of the manuscript. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors gratefully acknowledge H. Blumtritt, K. Lister, L. Czornomaz, J. Gonsalves, C. Bolliger, D. Cutaia, and W. Riess. The research leading to these results has received funding from the European Union Seventh Framework Program (FP7/20072013) Steeper under grant agreement no. 257267 and E2Switch under grant agreement no. 619509, and the Marie Curie Actions-Intra-European Fellowship (IEF-PHY) WISE under grant agreement no. 276595.
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REFERENCES
(1) Justice, J.; Bower, C.; Meitl, M.; Mooney, M. B.; Gubbins, M. A.; Corbett, B. Nat. Photonics 2012, 6, 610−614. (2) Del Alamo, J. A. Nature 2011, 479, 317−23. (3) Kim, D.-H.; del Alamo, J. A. IEEE Electron Device Lett. 2008, 29, 830−833. 1919
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(33) Moll, N.; Scheffler, M.; Pehlke, E. Phys. Rev. B 1998, 58, 4566− 4571. (34) Tomioka, K.; Motohisa, J.; Hara, S.; Fukui, T. Nano Lett. 2008, 8, 3475−80. (35) Grassman, T. J.; Brenner, M. R.; Rajagopalan, S.; Unocic, R.; Dehoff, R.; Mills, M.; Fraser, H.; Ringel, S. A. Appl. Phys. Lett. 2009, 94, 232106. (36) Grassman, T. J.; Carlin, J. A.; Galiana, B.; Yang, L.-M.; Yang, F.; Mills, M. J.; Ringel, S. A. Appl. Phys. Lett. 2013, 102, 142102. (37) Sieg, R. M.; Ringel, S. A.; Ting, S. M.; Fitzgerald, E. A.; Sacks, R. N. J. Electron. Mater. 1998, 27, 900−907. (38) Kondo, Y.; Deura, M.; Terada, Y.; Hoshii, T.; Takenaka, M.; Takagi, S.; Nakano, Y.; Sugiyama, M. J. Cryst. Growth 2010, 312, 1348−1352. (39) Demichel, O.; Heiss, M.; Bleuse, J.; Mariette, H.; Fontcuberta i Morral, A. Appl. Phys. Lett. 2010, 97, 201907. (40) Hong, M.; Passlack, M.; Mannaerts, J. P.; Kwo, J.; Chu, S. N. G.; Moriya, N.; Hou, S. Y.; Fratello, V. J. J. Vac. Sci. Technol. B: Microelectron. Nanom. Struct. 1996, 14, 2297−2300. (41) Joyce, H. J.; Qiang, G.; Yong, K.; Tan, H. H.; Jagadish, C. LEOS 2007 - IEEE Lasers Electro-Optics Soc. Annu. Meet. Conf. Proc. 2007, 407−408. (42) Mandl, B.; Stangl, J.; Mårtensson, T.; Mikkelsen, A.; Eriksson, J.; Karlsson, L. S.; Bauer, G. U. N.; Samuelson, L.; Seifert, W. Nano Lett. 2006, 6, 1817−21. (43) Ikejiri, K.; Sato, T.; Yoshida, H.; Hiruma, K.; Motohisa, J.; Hara, S.; Fukui, T. Nanotechnology 2008, 19, 265604. (44) Chi, C.-Y.; Chang, C.-C.; Hu, S.; Yeh, T.-W.; Cronin, S. B.; Dapkus, P. D. Nano Lett. 2013, 13, 2506−15. (45) Deura, M.; Hoshii, T.; Yamamoto, T.; Ikuhara, Y.; Takenaka, M.; Takagi, S.; Nakano, Y.; Sugiyama, M. Appl. Phys. Express 2009, 2, 011101. (46) Ghoneim, H.; Mensch, P.; Schmid, H.; Bessire, C. D.; Rhyner, R.; Schenk, A.; Rettner, C.; Karg, S.; Moselund, K. E.; Riel, H.; Björk, M. T. Nanotechnology 2012, 23, 505708. (47) Björk, M. T.; Schmid, H.; Bessire, C. D.; Moselund, K. E.; Ghoneim, H.; Karg, S.; Lortscher, E.; Riel, H. Appl. Phys. Lett. 2010, 97, 163501−1635013. (48) Riel, H.; Moselund, K. E.; Bessire, C.; Björk, M. T.; Schenk, A.; Ghoneim, H.; Schmid, H. In Electron Devices Meeting (IEDM), 2012: IEEE International; San Francisco, CA, 2012; pp 16.6.1−16.6.4.
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Vertical III−V Nanowire Device Integration on Si(100) Mattias Borg,† Heinz Schmid,*,† Kirsten E. Moselund,† Giorgio Signorello,† Lynne Gignac,‡ John Bruley,‡ Chris Breslin,‡ Pratyush Das Kanungo,† Peter Werner,§ and Heike Riel† †
IBM Research-Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland IBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, United States § Max Planck Institute of Microstructure Physics, Weinberg 2, 06120 Halle, Germany ‡
S Supporting Information *
ABSTRACT: We report complementary metal−oxide−semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si−InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process. KEYWORDS: Nanowires, III−V semiconductors, InAs, GaAs, Si, integration
I
particles for a limited range of growth conditions and yield.23,24 Thus, despite intensive efforts, a scalable and epitaxial integration method that provides material with sufficiently low defect densities, and is compliant with industry-standard Si(100) substrates, has yet to be demonstrated. Here we report on the local integration of InAs and GaAs vertical nanowires epitaxially grown on a variety of Si substrate orientations as well as on nanocrystalline (nc) Si, using SiO2 nanotube templates to guide the growth. Our process is completely CMOS-compatible, independent of substrate orientation and with demonstrated scalability at least down to 25 nm nanowire diameter. We determine the top-facet morphology of InAs nanowires of various crystal orientation, assess the crystal structure of [110]-oriented InAs nanowires by transmission electron microscopy (TEM), and investigate the optical properties of GaAs nanowires by photoluminescence (PL) measurements. We also demonstrate vertical Si−InAs nanowire tunnel diodes fabricated on industry-standard Si(100) substrates and evaluate the homogeneity and robustness of the method from their performance. Figure 1a−d displays scanning electron microscopy (SEM) images of InAs nanowires grown on exactly (±0.5°) oriented Si (100), (110), (111), and (112) wafers. The nanowires are vertically oriented, regardless of the substrate orientation. To accomplish this, nanowire growth was guided within SiO2
ntegration of group III−V semiconductors on Si has become a vibrant field of research because of the possibility to further improve the performance of transistors in the next generation of CMOS circuits and to integrate laser light sources on Si for on-chip optical communication.1 In particular the materials, InGaAs and InAs, which have high charge carrier mobilities and a direct bandgap, are among the most promising candidates.2 While the superior device performance of these materials over that of Si has already been demonstrated,3−5 a viable method for integrating them onto a Si platform still remains a key obstacle. Heteroepitaxy of III−V semiconductors on Si with low defect density has been pursued through the use of buffer layers,6−8 wafer bonding,9−11 and by promoting the formation of an interfacial misfit dislocation array to suppress the formation of threading dislocations.12 It is also recognized that defects stemming from the joining of dissimilar materials can be reduced by patterning the substrate in various ways. Patterned substrates can act as dislocation sinks,13 enable strain relaxation at the nanometer scale,14,15 and can be used to direct the growing crystal away from the defective heterointerface.16,17 Although the defect density is reduced with these techniques, threading dislocation densities on the order of 109 cm−2 are still reported.18 Other approaches to locally integrate III−V materials on Si are based on nanowire epitaxy using catalyst particles19,20 or selective area epitaxy.21,22 Although strain relaxation is efficient in nanowire epitaxy, III−V nanowire growth in directions other than ⟨111⟩ has only been observed by the use of catalyst © 2014 American Chemical Society
Received: December 20, 2013 Revised: March 7, 2014 Published: March 14, 2014 1914
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Figure 1. (a−d) SEM images taken at 45° tilt angle of vertical InAs nanowires grown using template-assisted epitaxy on Si nanowires on (a) [100]-, (b) [110]-, (c) [111]-, and (d) [112]-oriented Si substrates. The template has been removed in these images. (e) TEM image of GaAs nanowire grown on nc-Si nanowire. (f) Schematic illustrations of the main steps to fabricate templates on substrates with arbitrary crystal orientation. (I) Etching of Si nanowire, (II) silicon dioxide mask deposition and top opening, (III) back etching of α-Si, (IV) III−V growth in template, and (V) nanowire after removal of the template.
cleaned in a Piranha solution (90 °C) (II). The sacrificial α-Si layer is then etched away using a 25% tetramethylammonium hydroxide (TMAH) solution or alternatively a XeF2 dry etch (III). TMAH has a very low etch rate on the Si {111} planes and thus is self-terminating at the Si/α-Si interface. For substrate orientations other than Si(111), inclined {111} facets form at the floor of the templates, and a flat interface is attained only if an ESL is used or if the p-doping level of the substrate is sufficiently high to suppress wet etching.25 As a final step, the wafers are cleaned in Piranha solution and annealed at 750 °C in Ar/H2 for 30s to densify the SiO2 nanotube. Sub-40-nm nanotube templates were fabricated by etching out crystalline Si nanowires with a nominal diameter of 40 nm by ICP/RIE as described above and then thinning them down further by thermal oxidation. After opening the top of the template, the Si nanowires were back-etched using a 2% TMAH solution, which has a higher etch rate on the Si {111} planes than the standard solution. Directly before loading the wafer into the MOCVD reactor, the wafer is dipped into HF to remove the native oxide and to leave an H-terminated Si surface at the floor of the templates. InAs is then selectively grown within the templates at 520−580 °C with V/III ratios ranging from 10 to 100 (IV). The precursors used were trimethylindium (TMIn) and tertiarybutylarsenic (TBAs). For GaAs growth, a growth temperature of 650 °C and V/III ratio of 88 were used, with trimethylgallium (TMGa) and TBAs as precursors. Selected nanowires were prepared and characterized in detail by TEM and high-resolution TEM (HRTEM) at 300 keV. For the case of InAs nanowires grown on (110) Si, the nanowires were initially cross-sectioned in a direction perpendicular to the [110̅ ] using an in situ lift-out technique in a dual beam focused ion beam (DB-FIB) system. In one specific case, a sample that was initially cross-sectioned and analyzed in the TEM was then placed back in the DB-FIB and resectioned in the direction perpendicular to the [110], forming a planview (or top-down) section of the previously sectioned nanowires.26 Single GaAs nanowires were investigated by μ-PL using a spectrometer equipped with a He−Ne laser (λ = 633 nm, power < 15 μW/μm2) and a liquid-N2-cooled CCD detector.
nanotube templates, which determine the shape and direction of the nanowire crystal. After growth, the SiO2 templates were selectively removed by an HF etch. All nanowires in Figure 1 were produced using identical template fabrication processes, the only difference being the substrate orientation. In fact, as revealed by the TEM image in Figure 1e, the process even allows for nanowire growth (in this case GaAs) on nc-Si, still with a predefined vertical orientation and position. In this case, the crystalline orientation of Si at the growth interface is undefined, because of the random grain orientation of the nc-Si. Even so, the GaAs nanowire is single-crystalline, albeit with a crystallographic orientation that varies from nanowire to nanowire. This further illustrates the versatility of our approach, which enables the fabrication of aligned, single-crystalline nanowire devices on arbitrary substrates, the only requirement being the existence of a single nucleation seed in the nanotube template. To enable the growth of III−V nanowires as those shown in Figure 1, vertically oriented nanotube templates were fabricated on 2 in. Si wafers of the desired crystal orientation. The typical process is illustrated in Figure 1f and begins with the sputter deposition of a 500−800 nm thick layer of sacrificial amorphous Si (α-Si) on a Si wafer. The thickness of the α-Si layer later determines the depth of the nanotube template. Optionally, a thin (5−6 nm) SiO2 etch-stop layer (ESL) underneath the α-Si can be incorporated by plasma-enhanced chemical vapor deposition (PECVD). Electron-beam lithography is then performed using a hydrogen silsesquioxane (HSQ) negative resist to define dots with a diameter between 40 and 120 nm, marking the location and later defining the inner diameter of the templates. Inductively coupled plasma reactive-ion etching (ICP-RIE) using the HBr:O2 chemistry is then applied to etch out vertical nanowires using the HSQ hard-mask, as depicted in part I of Figure 1f. In the next step, SiO2 is deposited by PECVD at 400 °C using tetraethyl orthosilicate (TEOS) and O2 precursors. The top surface of the Si nanowires is exposed by dry-etching the top SiO2 in a CHF3/ O2 plasma while protecting the template sidewalls with photoresist. After removing the photoresist, the sample is 1915
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template-assisted epitaxy process is also a requirement for the fabrication of advanced electronic devices. In view of these benefits, we investigated the scalability of our method for growing nanowires with diameters below 40 nm. Figure 2c and d show the results of the down-scaled template fabrication and growth experiments on Si(111). Here, InAs segments with 25 nm diameter are grown in nanotube templates with an aspect ratio as high as 1:18. Even in this case do the InAs nanowires nucleate with close to 100% yield, which suggests that further down-scaling is feasible. A significant decrease in growth rate is observed in deep templates, related to a reduction in the supply of growth material with increased template aspect ratio. The top surfaces of the nanowires shown in the SEM images of Figures 1 and 2 have distinct and regular faceting. An inclined top facet structure is observed in the case of nanowires with [100], [110], and [112] orientation, whereas nanowires oriented in [111] typically exhibit a single horizontal top facet, as in our previous work.32 In Figure 3a, the top facets of a
For investigation of the electrical properties, Si(100)-InAs diodes were fabricated by etching away the empty part of the template by a timed buffered HF etch, leaving a SiO2 insulation layer on the substrate and side walls of the nanowires. Contact pads were then defined by Ti/Pd (50 nm/40 nm) evaporation and lift-off. The Si substrate back-side was metalized and used as ground, while bias was applied to the top contacts. In Figure 2a an overview image of an array of InAs nanowires in nanotube templates on Si(100) is shown. In each template,
Figure 3. Top-facet morphology of InAs nanowires with (a−b) [110] and (c−d) [111] growth direction. Each SEM image is paired with a schematic image to illustrate the planes constituting the top-facets. SEM images are taken at (a) 90°, (b) 45°, and (c−d) 60° tilt angle, respectively. (a) Nanowire with inclined top-facet morphology comprising two {110} facets and one (111)B facet. (b) Nanowire with flat top-facet morphology consisting only of {110} facets, one of which is horizontal. (c) Nanowire with [111]B growth direction. (d) Nanowire with [111]A growth direction exhibiting a (111)B facet inclined by 70.5° to the plane of the substrate.
Figure 2. (a−b) SEM image taken at 60° tilt angle of InAs nanowires grown in nanotube templates on a Si(100) substrate at low and high magnification, respectively. (c) SEM image of InAs nanowires grown in 25-nm-diameter nanotube templates on Si(111) taken at 60° tilt angle. The InAs segments are colored for better visibility. (d) Close-up SEM image at 85° tilt angle of a single InAs nanowire from (c).
nanowire grown on a [110]-oriented Si substrate is displayed. The inclined planes are identified, by measuring their angle to the wafer flat and the substrate surface normal, as being one {111} and two {110} planes. Because the As-terminated {111} facet (B) facet is more stable than the In-terminated {111} facet (A) for these growth conditions,33 the observed {111} facet is indexed as [111]B. In addition, we find that a significant fraction (10−15%) of the [110]-oriented InAs nanowires exhibit a horizontal top facet, often with additional inclined {110} facets. An example of such a nanowire is shown in Figure 3b. On Si(111), the polarity of the III−V materials allow two distinct orientations for epitaxial III−V growth; either [111]A or [111]B orientation. With appropriate surface preparation, the preferred orientation can be tuned.34 The distinction between the two crystal polarities is revealed by the differences in the morphology of the top facets; see Figure 3c−d. We either observe a single horizontal [111]B top facet (Figure 3c) or an inclined top facet morphology similar to those of the other substrate orientations. The inclined case belongs to a crystal with [111]A orientation, which is even clearer in those cases where the crystal extends beyond the confinement of the template. The [111]B-oriented nanowire then evolves into a
InAs has nucleated and filled up the width of the nanotube. There is no crystal growth outside the templates, highlighting the selectivity of the growth process and also that InAs is grown preferentially at the desired locations. Regardless of substrate orientation, the yield of successful InAs nucleation on the wafer can be close to 100%. However, the yield strongly depends on the growth and sample conditions. To achieve a high yield of nanowire growth, a molar flow of TMIn above 2 μmol/min at growth temperatures up to 550 °C is necessary. Above this temperature, a higher TMIn flow is needed to compensate for the high rate of In desorption from Si surfaces.27 High selectivity between the intended nanowire growth and the parasitic growth on the masked area is readily obtained when using a clean growth mask and low precursor flows. In the highly lattice-mismatched Si-InAs system (11.6% mismatch), the high level of strain is typically relieved by forming a dislocation network at the interface.12,28,29 If the diameter of the junction were to be scaled down, strain partitioning across the heterojunction could reduce the misfit dislocation density.14,30,31 In addition, down-scaling of the 1916
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hexagonal shape (Figure 3c), whereas the [111]A-oriented nanowire changes direction and evolves into a hexagonal shape inclined by 70.5° to the substrate normal (Figure 3d). Because of the crystal symmetry, equivalent structures in this case are found by rotation in steps of 120° around the surface normal. Likewise, for [100]- and [110]-oriented nanowires equivalent structures are observed with rotation in steps of 90° and 180°, respectively (see Supporting Information for details on the rotational symmetry of the top facet morphology). The fact that in all cases we observe consistent top facet morphologies is an indication that each InAs nanowire crystal originates from a single nucleus in each template. This is a significant finding as it means that here antiphase boundary (APB) defects, typically an important concern for III−V integration on Si, could be suppressed. APB defects are formed when two nuclei with different polarity or from separate surface steps merge, and in planar heteroepitaxy great care has to be taken to limit the APB density.35−37 In the nanotube templates, the merging of nuclei and the associated creation of defects is avoided because the diameter of the exposed Si in each template is much smaller than the mean adatom diffusion length, so that as soon as the first nucleation event occurs it will consume all available material within the template, thus preventing further nucleation events. This model was tested by performing very short growth runs, where indeed a single small crystallite is found within each template. Likewise, a single nucleus per mask opening was previously reported by Kondo et al.38 and Björk et al.22 by selective area epitaxy. Summarizing the above findings, the template-assisted epitaxy technique (1) enables vertical nanowire growth independent of the substrate orientation, (2) is scalable at least down to 25 nm diameter, and (3) enables growth from a single nucleus per template, thus likely avoiding the problem of APB defect formation. In contrast to other fabrication methods, the side-wall surfaces of the nanowires in this work are protected by the template wall and are therefore not exposed to the ambient air after growth. Thus, the properties of the side-wall surfaces may differ significantly from those of other types of nanowires. This is especially true for oxidized GaAs surfaces, which typically have a high surface state density, leading to strong nonradiative recombination processes.39−41 We have therefore evaluated the optical properties of single GaAs nanowires in nanotube templates on Si(110) substrates. In total, room temperature PL measurements of 65 individual GaAs nanowires were collected. When excited by laser light, the nanowires exhibit stable luminescence, and there is no sign of degradation even after several weeks of exposure in air. In Figure 4, PL spectra of a representative GaAs nanowire before and after template removal are displayed. To allow a quantitative comparison, both spectra were normalized so that the Si Raman optical phonon peaks (521 cm−1) have equal intensity in both cases. The PL intensity after template removal dropped by about a factor of 5 for the particular nanowire shown, but even larger differences were observed. Although this could in part be explained by a difference in light coupling strengths, it is likely that the GaAs/SiO2 interface provides enhanced surface passivation. An investigation of the crystal structure of InAs nanowires grown on Si(110) was performed by TEM/HRTEM. From the TEM images in Figure 5 and the diffraction patterns included, it is clear that the nanowires are single-crystalline and have a direct epitaxial relationship to the Si substrate. The spacing
Figure 4. Room-temperature PL spectra of single GaAs nanowires on Si(110). Comparison of PL spectra from an as-grown nanowire in a nanotube template and after removal of the template. The intensity of the Si Raman optical phonon peak (521 cm−1) was used for data normalization.
between diffraction spots originating from the InAs nanowires correspond to bulk values for InAs, and the nanowires contain a high density of planar defects. These defects are most likely stacking faults, as is typical for nanoscale selective area epitaxy.22,42−45 Using the acquired HRTEM data it cannot be completely ruled out that they are not APB defects, although this is unlikely due to the consistent top facet morphologies and uniform defect density observed throughout the nanowires. We will therefore denote these defects as stacking faults in the following. Misfit dislocations are expected to form at the Si/InAs heterojunction because of the large lattice-mismatch between the materials (11.6%). Surprisingly, misfit dislocations are not visible in standard TEM images, possibly because they are hidden by the interface roughness. By geometric phase analysis (GPA) of cross-sectional HRTEM images we have measured the mismatch across the heterojunction, which we find to be 11.3% ± 0.6% over a distance of 1 nm indicating that the InAs nanowire is fully relaxed (see the Supporting Information for details on the determination of the strain relaxation). There are occasional local high strain points at the heterointerface, revealed by GPA in Figure 5e−f, which are confirmed to be misfit dislocations by Burger circuit loop analysis. The number of observed misfit dislocations is approximately 15 across the nanowire. In contrast to the case of [111]-oriented nanowires, it is possible that here the mismatch is in part relieved by stacking faults that originate from the heterojunction. Despite the presence of misfit dislocations we do not observe threading dislocations in any of the investigated nanowires. Since threading dislocations are a major concern for III−V integration on Si, the absence of dislocation threading here is of great significance. In nanowires with inclined top facets (Figure 5a), stacking-faults are seen edge-on in the [11̅0] viewing direction and are oriented parallel to the inclined (111) or (111)̅ planes. In contrast, InAs nanowires with horizontal top facets appear stacking-fault-free when viewed in the [11̅0] direction (Figure 5b). However, when viewed along the [110] direction in cross-sectional images26 (the planview image in Figure 5d), the (111̅ )-oriented stacking faults that run vertically through the entire length of the nanowire become visible. The observation of differences in stacking-fault orientation can explain the existence of the two 1917
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To investigate the suitability of template-assisted epitaxy for device fabrication, we fabricated vertical Si/InAs tunnel diodes from InAs nanowires grown in templates on highly p-doped Si(100) substrates (NA = 2 × 1020 cm−3). The nanowires used were 50 nm in diameter and Si-doped (n-type) during growth using Si2H6 (estimated ND = 1 × 1018 cm−3).46 In Figure 6 the
Figure 6. (a−b) Semilogarithmic I−V characteristics of 50-nmdiameter Si(100)-InAs nanowire tunnel diodes fabricated. (a) Semilogarithmic I−V plot of devices containing 1, 4, 25, or 49 contacted nanowires. The current scales well with the number of nanowires, as is clear from (b) where the current densities of representative devices with varying numbers of nanowires are shown. The inset in (b) is a schematic of the device structure. (c) SEM image (70° tilt) of a nanowire from the same wafer before metallization and (d) SEM image of a 49 nanowire device after metallization. The inset in (d) shows an overview image of the complete contact pad.
Figure 5. TEM images of InAs nanowires grown on a Si(110) substrate with the template removed. (a) An InAs nanowire viewed in the [110̅ ] direction with an inclined top-facet morphology containing a high concentration of stacking-faults. (b) InAs nanowire viewed in the [110̅ ] direction with horizontal top-facets that exhibits vertically oriented stacking-faults only visible in the cross-sectional image (d). Insets in (a) and (b) are diffraction patterns for the parts of the images indicated by the arrows. (c, d) HRTEM images of nanowires viewed in the [110] direction (planview from cross-section), corresponding to the same nanowires in (a) and (b), respectively. The nanowire crosssection is truncated on the top and bottom because of the vertical cut, which was done first. The cross-section samples were obtained at positions in the lower half of the InAs nanowire, and were approximately 100 nm thick. In (c) part of the Si stem is included, causing a Moiré pattern due to the different lattice parameters of Si and InAs. (e) HRTEM image of the Si/InAs heterojunction of a [110]-oriented nanowire and (f) GPA lattice mismatch map of the same picture, in which high strain regions are indicated by arrows. The inset displays a fast Fourier transform filtered high-resolution image of a single such region, where a Burgers circuit loop has been done to verify the presence of a misfit dislocation (black arrow points to the dislocation core).
current−voltage (I−V) characteristics of 50-nm-diameter Si(100)-InAs diodes with varying number of contacted nanowires is shown. The I−V curves exhibit typical tunnel diode characteristics,47 such as a high subexponential current in reverse bias (VDS > 0 V), a peak in current at low forward bias (VDS ∼ −0.1 V) followed by an exponentially increasing diode current at higher forward bias (VDS < −0.4 V). The region of negative differential resistance (NDR) is masked by a high level of excess current, which is attributed to defect states located at the heterojunction. As seen in Figure 6b, the current levels scale well with respect to the number of contacted nanowires, both in terms of current level and curve shape. The average current level at 0.5 V is roughly 150 kA/cm2, normalized to the InAs nanowire cross-sectional area. This value is comparable to the current density level of Si/InAs tunnel diodes with similar doping levels fabricated on Si(111) using other techniques.48 Because of the template-assisted nanowire growth, a high uniformity of the measured devices is achieved, which is very promising in view of implementations into logic circuits where reproducibility and uniformity are vital.
distinct facet morphologies (Figure 3c and d). Similarly, in the case of GaAs nanowires, it can explain an observed difference in PL line-shapes depending on the top facet morphology (see Supporting Information for details on the correlation between PL line shape and nanowire morphology). 1918
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Nano Letters
Letter
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In conclusion, we have demonstrated vertical III−V nanowire growth on [100]-, [110]-, [112]-, and [111]-oriented Si substrates and on nc-Si through the use of SiO2 nanotube templates. The template fabrication process is fully CMOScompatible and scalable at least down to 25 nm nanowire diameter. The consistent faceting observed on the top of all nanowires implies well-defined growth planes and an absence of APB defects. Moreover, no threading dislocations are observed in the InAs nanowires despite the large lattice-mismatch between InAs and Si, although a high density of stacking-faults is observed. GaAs nanowires in templates exhibit stable roomtemperature PL, which is stronger for nanowires surrounded by a template. The template-assisted InAs nanowire growth exhibits a high yield and uniformity across full 2 in. wafers, which is also reflected in a consistent and scalable device performance of vertical nanowire tunnel diodes fabricated on Si(100). We believe that template-assisted epitaxy provides a viable path toward large-scale local integration of III−V materials on Si for integrated high-speed electronic and optoelectronic devices.
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ASSOCIATED CONTENT
S Supporting Information *
Details on the rotational symmetry of the top facet morphology, the process to extract the peak position from the photoluminescence measurement data, and the determination of the lattice misfit profile across the Si/InAs heterojunction. This material is available free of charge via the Internet at http://pubs.acs.org.
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AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected]. Present Address
P.D.K.: Paul Scherrer Institut, 5232 Villigen PSI, Switzerland Author Contributions
H.S., M.B., and H.R. have conceived and designed the experiment. The template and device processing was done by M.B., K.E.M., and H.S., the growth experiments by M.B. and P.D.K., optical measurements by G.S., HRTEM investigation by L.G., J.B., C.B., and P.W. The manuscript was written by M.B. and H.S., with contributions of all authors, and all authors have given approval to the final version of the manuscript. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors gratefully acknowledge H. Blumtritt, K. Lister, L. Czornomaz, J. Gonsalves, C. Bolliger, D. Cutaia, and W. Riess. The research leading to these results has received funding from the European Union Seventh Framework Program (FP7/20072013) Steeper under grant agreement no. 257267 and E2Switch under grant agreement no. 619509, and the Marie Curie Actions-Intra-European Fellowship (IEF-PHY) WISE under grant agreement no. 276595.
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Nano Letters
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